From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 17 Mar 2021 20:40:49 +0000 (+0000)
Subject: add CR-based predication to ISACaller
X-Git-Tag: convert-csv-opcode-to-binary~13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a62e46f76219b3c02fee379047d8a18df2f22fc;p=soc.git

add CR-based predication to ISACaller
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 9f3cfc1b..dcdded95 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -228,6 +228,34 @@ def get_predint(gpr, mask):
     if mask == SVP64PredInt.R30_N.value:
         return ~gpr(30).value
 
+# decode SVP64 predicate CR to reg number and invert
+def _get_predcr(mask):
+    if mask == SVP64PredCR.LT.value:
+        return 0, 1
+    if mask == SVP64PredCR.GE.value:
+        return 0, 0
+    if mask == SVP64PredCR.GT.value:
+        return 1, 1
+    if mask == SVP64PredCR.LE.value:
+        return 1, 0
+    if mask == SVP64PredCR.EQ.value:
+        return 2, 1
+    if mask == SVP64PredCR.NE.value:
+        return 2, 0
+    if mask == SVP64PredCR.SO.value:
+        return 3, 1
+    if mask == SVP64PredCR.NS.value:
+        return 3, 0
+
+def get_predcr(crl, mask, vl):
+    idx, noninv = _get_predcr(mask)
+    mask = 0
+    for i in range(vl):
+        cr = crl[i+SVP64CROffs.CRPred]
+        if cr[idx].value == noninv:
+            mask |= (1<<i)
+    return mask
+
 
 class SPR(dict):
     def __init__(self, dec2, initial_sprs={}):
@@ -365,7 +393,7 @@ def get_pdecode_idx_out(dec2, name):
         if out_sel == OutSel.RA.value:
             return out, o_isvec
     elif name == 'RT':
-        print ("get_pdecode_idx_out", out_sel, OutSel.RT.value, 
+        print ("get_pdecode_idx_out", out_sel, OutSel.RT.value,
                                       OutSel.RT_OR_ZERO.value, out, o_isvec)
         if out_sel == OutSel.RT.value:
             return out, o_isvec
@@ -899,6 +927,10 @@ class ISACaller:
                 srcmask = dstmask = get_predint(self.gpr, dstpred)
                 if sv_ptype == SVPtype.P2.value:
                     srcmask = get_predint(srcpred)
+            elif pmode == SVP64PredMode.CR.value:
+                srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
+                if sv_ptype == SVPtype.P2.value:
+                    srcmask = get_predcr(self.crl, srcpred, vl)
             print ("    pmode", pmode)
             print ("    ptype", sv_ptype)
             print ("    srcmask", bin(srcmask))
diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 6863fff3..4ed0577c 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -16,7 +16,8 @@ class Register:
     def __init__(self, num):
         self.num = num
 
-def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False):
+def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
+                                     initial_cr=0):
     if initial_sprs is None:
         initial_sprs = {}
     m = Module()
@@ -30,7 +31,7 @@ def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False):
     instructions = list(zip(gen, insncode))
 
     m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
-    simulator = ISA(pdecode2, initial_regs, initial_sprs, 0,
+    simulator = ISA(pdecode2, initial_regs, initial_sprs, initial_cr,
                     initial_insns=gen, respect_pc=True,
                     initial_svstate=svstate,
                     disassembly=insncode,
diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py
index 2c99af0c..9ab7c790 100644
--- a/src/soc/decoder/isa/test_caller_svp64_predication.py
+++ b/src/soc/decoder/isa/test_caller_svp64_predication.py
@@ -42,8 +42,8 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
             self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
 
-    def test_sv_add(self):
-        # adds, predicated mask r3=0b10
+    def test_sv_add_intpred(self):
+        # adds, integer predicated mask r3=0b10
         #       1 = 5 + 9   => not to be touched (skipped)
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
         isa = SVP64Asm(['svadd/m=r3 1.v, 5.v, 9.v'
@@ -73,6 +73,40 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program, initial_regs, svstate)
             self._check_regs(sim, expected_regs)
 
+    def test_sv_add_cr_pred(self):
+        # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
+        #       1 = 5 + 9   => not to be touched (skipped)
+        #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
+        isa = SVP64Asm(['svadd/m=ne 1.v, 5.v, 9.v'
+                       ])
+        lst = list(isa)
+        print ("listing", lst)
+
+        # initial values in GPR regfile
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xbeef   # not to be altered
+        initial_regs[9] = 0x1234
+        initial_regs[10] = 0x1111
+        initial_regs[5] = 0x4321
+        initial_regs[6] = 0x2223
+        # SVSTATE (in this case, VL=2)
+        svstate = SVP64State()
+        svstate.vl[0:7] = 2 # VL
+        svstate.maxvl[0:7] = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.spr.asint()))
+        # copy before running
+        expected_regs = deepcopy(initial_regs)
+        expected_regs[1] = 0xbeef
+        expected_regs[2] = 0x3334
+
+        # set up CR predicate - CR4.eq=0 and CR5.eq=1
+        cr = (0b0010) << ((7-4)*4) # CR5.eq (we hope)
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_regs, svstate,
+                                       initial_cr=cr)
+            self._check_regs(sim, expected_regs)
+
     def tst_sv_add_2(self):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
@@ -195,10 +229,12 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(CR1, SelectableInt(4, 4))
 
     def run_tst_program(self, prog, initial_regs=None,
-                              svstate=None):
+                              svstate=None,
+                              initial_cr=0):
         if initial_regs is None:
             initial_regs = [0] * 32
-        simulator = run_tst(prog, initial_regs, svstate=svstate)
+        simulator = run_tst(prog, initial_regs, svstate=svstate,
+                            initial_cr=initial_cr)
         simulator.gpr.dump()
         return simulator