From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 30 May 2019 22:50:47 +0000 (-0700)
Subject: Fix spelling
X-Git-Tag: working-ls180~1208^2~230
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a6b9af227cb22e89fd463c665016544060d2acd;p=yosys.git

Fix spelling
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 82f149c8c..4bda388de 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -924,7 +924,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 			else {
 				// Attempt another wideports_split here because there
 				// exists the possibility that different bits of a port
-				// could be an input and output, therefore parse_xiager()
+				// could be an input and output, therefore parse_xaiger()
 				// could not combine it into a wideport
 				auto r = wideports_split(w->name.str());
 				wire = module->wire(r.first);