From: Sa Liu Date: Fri, 9 Mar 2007 18:17:08 +0000 (+0000) Subject: altivec.md: Fix vcond patterns using if_then_else. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a71edd9b8aff0f005c08ce6094aca36e8a33c25;p=gcc.git altivec.md: Fix vcond patterns using if_then_else. 2007-03-09 Sa Liu * config/rs6000/altivec.md: Fix vcond patterns using if_then_else. From-SVN: r122755 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 31d871a7ee1..d6f1d885748 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2007-03-09 Sa Liu + + * config/rs6000/altivec.md: Fix vcond patterns using if_then_else. + 2007-03-09 Ian Lance Taylor * opts.c (common_handle_option): Treat -Wstrict-overflow (with no diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 006fcfbe369..f477979811e 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -131,13 +131,6 @@ (UNSPEC_INTERLO_V8HI 233) (UNSPEC_INTERLO_V16QI 234) (UNSPEC_INTERLO_V4SF 235) - (UNSPEC_VCOND_V4SI 301) - (UNSPEC_VCOND_V4SF 302) - (UNSPEC_VCOND_V8HI 303) - (UNSPEC_VCOND_V16QI 304) - (UNSPEC_VCONDU_V4SI 305) - (UNSPEC_VCONDU_V8HI 306) - (UNSPEC_VCONDU_V16QI 307) (UNSPEC_VMULWHUB 308) (UNSPEC_VMULWLUB 309) (UNSPEC_VMULWHSB 310) @@ -1485,13 +1478,13 @@ [(set_attr "type" "vecfloat")]) (define_expand "vcondv4si" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v") - (match_operand:V4SI 3 "comparison_operator" "") - (match_operand:V4SI 4 "register_operand" "v") - (match_operand:V4SI 5 "register_operand" "v") - ] UNSPEC_VCOND_V4SI))] + [(set (match_operand:V4SI 0 "register_operand" "=v") + (if_then_else:V4SI + (match_operator 3 "comparison_operator" + [(match_operand:V4SI 4 "register_operand" "v") + (match_operand:V4SI 5 "register_operand" "v")]) + (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] "TARGET_ALTIVEC" " { @@ -1504,13 +1497,13 @@ ") (define_expand "vconduv4si" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v") - (match_operand:V4SI 3 "comparison_operator" "") - (match_operand:V4SI 4 "register_operand" "v") - (match_operand:V4SI 5 "register_operand" "v") - ] UNSPEC_VCONDU_V4SI))] + [(set (match_operand:V4SI 0 "register_operand" "=v") + (if_then_else:V4SI + (match_operator 3 "comparison_operator" + [(match_operand:V4SI 4 "register_operand" "v") + (match_operand:V4SI 5 "register_operand" "v")]) + (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] "TARGET_ALTIVEC" " { @@ -1523,13 +1516,13 @@ ") (define_expand "vcondv4sf" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v") - (match_operand:V4SF 3 "comparison_operator" "") - (match_operand:V4SF 4 "register_operand" "v") - (match_operand:V4SF 5 "register_operand" "v") - ] UNSPEC_VCOND_V4SF))] + [(set (match_operand:V4SF 0 "register_operand" "=v") + (if_then_else:V4SF + (match_operator 3 "comparison_operator" + [(match_operand:V4SF 4 "register_operand" "v") + (match_operand:V4SF 5 "register_operand" "v")]) + (match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")))] "TARGET_ALTIVEC" " { @@ -1542,13 +1535,13 @@ ") (define_expand "vcondv8hi" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V8HI 3 "comparison_operator" "") - (match_operand:V8HI 4 "register_operand" "v") - (match_operand:V8HI 5 "register_operand" "v") - ] UNSPEC_VCOND_V8HI))] + [(set (match_operand:V8HI 0 "register_operand" "=v") + (if_then_else:V8HI + (match_operator 3 "comparison_operator" + [(match_operand:V8HI 4 "register_operand" "v") + (match_operand:V8HI 5 "register_operand" "v")]) + (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] "TARGET_ALTIVEC" " { @@ -1561,13 +1554,13 @@ ") (define_expand "vconduv8hi" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V8HI 3 "comparison_operator" "") - (match_operand:V8HI 4 "register_operand" "v") - (match_operand:V8HI 5 "register_operand" "v") - ] UNSPEC_VCONDU_V8HI))] + [(set (match_operand:V8HI 0 "register_operand" "=v") + (if_then_else:V8HI + (match_operator 3 "comparison_operator" + [(match_operand:V8HI 4 "register_operand" "v") + (match_operand:V8HI 5 "register_operand" "v")]) + (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] "TARGET_ALTIVEC" " { @@ -1580,13 +1573,13 @@ ") (define_expand "vcondv16qi" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v") - (match_operand:V16QI 3 "comparison_operator" "") - (match_operand:V16QI 4 "register_operand" "v") - (match_operand:V16QI 5 "register_operand" "v") - ] UNSPEC_VCOND_V16QI))] + [(set (match_operand:V16QI 0 "register_operand" "=v") + (if_then_else:V16QI + (match_operator 3 "comparison_operator" + [(match_operand:V16QI 4 "register_operand" "v") + (match_operand:V16QI 5 "register_operand" "v")]) + (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] "TARGET_ALTIVEC" " { @@ -1599,13 +1592,13 @@ ") (define_expand "vconduv16qi" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v") - (match_operand:V16QI 3 "comparison_operator" "") - (match_operand:V16QI 4 "register_operand" "v") - (match_operand:V16QI 5 "register_operand" "v") - ] UNSPEC_VCONDU_V16QI))] + [(set (match_operand:V16QI 0 "register_operand" "=v") + (if_then_else:V16QI + (match_operator 3 "comparison_operator" + [(match_operand:V16QI 4 "register_operand" "v") + (match_operand:V16QI 5 "register_operand" "v")]) + (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] "TARGET_ALTIVEC" " {