From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 28 May 2019 15:44:59 +0000 (-0700)
Subject: Misspell
X-Git-Tag: working-ls180~1208^2~257
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a76b425cc0588ef5a8e46c06eecbfab869a35d9;p=yosys.git

Misspell
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 1b45085be..328f0e3c3 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -567,7 +567,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
 					// Attempt another wideports_split here because there
 					// exists the possibility that different bits of a port
-					// could be an input and output, therefore parse_xiager()
+					// could be an input and output, therefore parse_xaiger()
 					// could not combine it into a wideport
 					auto r = wideports_split(w->name.str());
 					wire = module->wire(r.first);