From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Dec 2019 07:52:05 +0000 (-0800)
Subject: Even more obvious testcase
X-Git-Tag: working-ls180~845^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a805108776f563bcd7550d1331a73a50512fbe2;p=yosys.git

Even more obvious testcase
---

diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
index 6cb68a8d3..1436724b0 100644
--- a/tests/sat/initval.ys
+++ b/tests/sat/initval.ys
@@ -5,12 +5,11 @@ sat -seq 10 -prove-asserts
 
 design -reset
 read_verilog -icells <<EOT
-module top(input clk, i, output o, p);
-(* init = 1'b0 *)
-wire o;
-(* init = 1'bx *)
-wire p = o;
-$_DFF_P_ dff (.C(clk), .D(i), .Q(o));
+module top(input clk, i, output [1:0] o);
+(* init = 2'bx0 *)
+wire [1:0] o;
+assign o[1] = o[0];
+$_DFF_P_ dff (.C(clk), .D(i), .Q(o[0]));
 endmodule
 EOT
 sat -seq 1