From: lkcl <lkcl@web>
Date: Mon, 20 Sep 2021 14:10:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~47
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a9396fcdb97d1f2b71b9cbeb8ddd52ee3e837f8;p=libreriscv.git

---

diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index ac4d2fa51..54f42ad49 100644
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -70,6 +70,10 @@ full context save/restore (see SVSRR0).  It contains (and permits setting of):
 * vfirst - Vertical First mode.  srcstep, dststep and substep
     **do not advance** unless explicitly requested to do so with
     pseudo-op svstep (a mode of setvl)
+* RMpst - REMAP persistence.  REMAP will apply only to the following
+  instruction unless this bit is set, in which case REMAP "persists".
+  Reset (cleared) on use of the `setvl` instruction if used to
+  alter VL or MVL.
 * hphint - Horizontal Parallelism Hint. In Vertical First Mode
    hardware **MAY** perform up to this many elements in parallel
    per instruction. Set to zero to indicate "no hint".