From: Jordan Justen <jordan.l.justen@intel.com>
Date: Tue, 17 Feb 2015 17:57:35 +0000 (-0800)
Subject: i965/simd8vs: Fix SIMD8 atomics (read-only)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a95be9772a255776309f23180519a4a8560f2dd;p=mesa.git

i965/simd8vs: Fix SIMD8 atomics (read-only)

An update for d9cd982d556be560af3bcbcdaf62b6b93eb934a5.

A similar change was needed for CS to allow the piglit test
tests/spec/arb_compute_shader/execution/simple-barrier-atomics.shader_test
to pass.

The previous change (d9cd982d) should fix cases that write atomics,
such as atomicCounterIncrement, and this change will fix cases than
only read atomics, such as atomicCounter.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
---

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index a7601149d36..24cc1187d7f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -3037,9 +3037,6 @@ void
 fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
                                       fs_reg offset)
 {
-   bool uses_kill =
-      (stage == MESA_SHADER_FRAGMENT) &&
-      ((brw_wm_prog_data*) this->prog_data)->uses_kill;
    int reg_width = dispatch_width / 8;
 
    fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 2);
@@ -3049,13 +3046,24 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
    emit(MOV(sources[0], fs_reg(0u)))
       ->force_writemask_all = true;
 
-   if (uses_kill) {
-      emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
-         ->force_writemask_all = true;
+   if (stage == MESA_SHADER_FRAGMENT) {
+      if (((brw_wm_prog_data*)this->prog_data)->uses_kill) {
+         emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
+            ->force_writemask_all = true;
+      } else {
+         emit(MOV(component(sources[0], 7),
+                  retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
+            ->force_writemask_all = true;
+      }
    } else {
+      /* The execution mask is part of the side-band information sent together with
+       * the message payload to the data port. It's implicitly ANDed with the sample
+       * mask sent in the header to compute the actual set of channels that execute
+       * the atomic operation.
+       */
+      assert(stage == MESA_SHADER_VERTEX);
       emit(MOV(component(sources[0], 7),
-               retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
-         ->force_writemask_all = true;
+               brw_imm_ud(0xff)))->force_writemask_all = true;
    }
 
    /* Set the surface read offset. */