From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 11 Oct 2016 10:12:32 +0000 (+0200)
Subject: Fixed "make test" for git head of iverilog
X-Git-Tag: yosys-0.7~37
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a981a3bd81836cd15059db56f01b60b11068742;p=yosys.git

Fixed "make test" for git head of iverilog
---

diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh
index 19a235c7a..98a45b613 100644
--- a/tests/bram/run-single.sh
+++ b/tests/bram/run-single.sh
@@ -2,7 +2,7 @@
 set -e
 ../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \
 		-l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v
-iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1ns -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \
+iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1 -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \
 		temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v
 temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt
 if grep -q ERROR temp/tb_${1}_${2}.txt; then