From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 18 Jan 2014 17:54:50 +0000 (+0100)
Subject: Fixed a type in $mem model in simlib.v
X-Git-Tag: yosys-0.2.0~160
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a9e133fabe85847f4cdaafed0b8024691be5395;p=yosys.git

Fixed a type in $mem model in simlib.v
---

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index f3d652f0e..321119e37 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1036,7 +1036,7 @@ generate
 				end
 			end
 		end else
-		if (RD_CLK_POLARITY[i] == 1) begin:rd_posclk
+		if (WR_CLK_POLARITY[i] == 1) begin:rd_posclk
 			always @(posedge WR_CLK[i])
 				if (WR_EN[i]) begin
 					data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];