From: Iru Cai Date: Fri, 21 Aug 2020 07:11:39 +0000 (+0800) Subject: arch-arm: Fix build errors with gcc 10.2 X-Git-Tag: v20.1.0.0~42 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4aab23e34fa15395dd0d89e327c46766da0be273;p=gem5.git arch-arm: Fix build errors with gcc 10.2 The "-Werror=type-limits" flag in GCC 10.2 reports these errors, because ``imm`` in neon.isa, and ``imm`` and ``count`` in sve.isa are unsigned, and they're used to do ``imm < 0`` and ``imm * count >= 0`` comparison. Change-Id: I33934357f578a9fc1040a6d9c08ea929fb36eb47 Signed-off-by: Iru Cai Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33154 Reviewed-by: Giacomo Travaglini Reviewed-by: Richard Cooper Maintainer: Giacomo Travaglini Tested-by: kokoro --- diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index aa67353b7..d536d5b8d 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -1416,7 +1416,7 @@ let {{ if readDest: readDestCode = 'destElem = letoh(destReg.elements[i]);' eWalkCode += ''' - if (imm < 0 && imm >= eCount) { + if (imm >= eCount) { fault = std::make_shared(machInst, false, mnemonic); } else { @@ -1468,7 +1468,7 @@ let {{ if readDest: readDestCode = 'destElem = letoh(destReg.elements[i]);' eWalkCode += ''' - if (imm < 0 && imm >= eCount) { + if (imm >= eCount) { fault = std::make_shared(machInst, false, mnemonic); } else { @@ -1518,7 +1518,7 @@ let {{ if readDest: readDestCode = 'destReg = destRegs[i];' eWalkCode += ''' - if (imm < 0 && imm >= eCount) { + if (imm >= eCount) { fault = std::make_shared(machInst, false, mnemonic); } else { diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa index 9314ba9a6..4e49e9294 100644 --- a/src/arch/arm/isa/insts/sve.isa +++ b/src/arch/arm/isa/insts/sve.isa @@ -4335,13 +4335,10 @@ let {{ destElem = srcElem1 - (count * imm); bool negDest = (destElem < 0); bool negSrc = (srcElem1 < 0); - bool posCount = ((count * imm) >= 0); - if ((negDest != negSrc) && (negSrc == posCount)) { + if (!negDest && negSrc) { destElem = static_cast<%(dstType)s>( (%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1) ); - if (negDest) - destElem -= 1; } ''' sveElemCountInst('sqdec', 'Sqdec32', 'SimdAluOp', signedTypes, @@ -4394,13 +4391,11 @@ let {{ destElem = srcElem1 + (count * imm); bool negDest = (destElem < 0); bool negSrc = (srcElem1 < 0); - bool negCount = ((count * imm) < 0); - if ((negDest != negSrc) && (negSrc == negCount)) { + if (negDest && !negSrc) { destElem = static_cast<%(dstType)s>( (%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1) ); - if (negDest) - destElem -= 1; + destElem -= 1; } ''' sveElemCountInst('sqinc', 'Sqinc32', 'SimdAluOp', signedTypes,