From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Jun 2020 18:59:30 +0000 (+0100)
Subject: expand regwid to 64 in l0_cache test
X-Git-Tag: div_pipeline~522
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ab0834c969ff24a69228ec18915c976d32d765e;p=soc.git

expand regwid to 64 in l0_cache test
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 09d0e5f1..1a941a47 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -36,6 +36,7 @@ from nmigen.lib.coding import PriorityEncoder
 # for testing purposes
 from soc.experiment.testmem import TestMemory
 
+
 class PortInterface(RecordObject):
     """PortInterface
 
@@ -568,7 +569,7 @@ def data_merger_merge(dut):
 
 def test_l0_cache():
 
-    dut = TstL0CacheBuffer()
+    dut = TstL0CacheBuffer(regwid=64)
     #vl = rtlil.convert(dut, ports=dut.ports())
     #with open("test_basic_l0_cache.il", "w") as f:
     #    f.write(vl)