From: Tim Newsome Date: Mon, 2 Apr 2018 21:56:45 +0000 (-0700) Subject: Use `gdb_report_register_access_error enable` X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ab18e0f8e6381f0a16e8b812d4ee202e9465192;p=riscv-tests.git Use `gdb_report_register_access_error enable` --- diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg index f420417..083794f 100644 --- a/debug/targets/RISC-V/spike-1.cfg +++ b/debug/targets/RISC-V/spike-1.cfg @@ -11,6 +11,7 @@ set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME gdb_report_data_abort enable +gdb_report_register_access_error enable # Expose an unimplemented CSR so we can test non-existent register access # behavior. diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg index 114d5b8..ef8bab1 100644 --- a/debug/targets/RISC-V/spike-2.cfg +++ b/debug/targets/RISC-V/spike-2.cfg @@ -14,6 +14,7 @@ target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 gdb_report_data_abort enable +gdb_report_register_access_error enable # Expose an unimplemented CSR so we can test non-existent register access # behavior. diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg index 159a70f..d8bd27e 100644 --- a/debug/targets/RISC-V/spike-rtos.cfg +++ b/debug/targets/RISC-V/spike-rtos.cfg @@ -12,6 +12,7 @@ set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv gdb_report_data_abort enable +gdb_report_register_access_error enable # Expose an unimplemented CSR so we can test non-existent register access # behavior. diff --git a/debug/targets/SiFive/HiFive1.cfg b/debug/targets/SiFive/HiFive1.cfg index 8f21b47..333c82e 100644 --- a/debug/targets/SiFive/HiFive1.cfg +++ b/debug/targets/SiFive/HiFive1.cfg @@ -17,6 +17,9 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1 #-rtos riscv +gdb_report_data_abort enable +gdb_report_register_access_error enable + # Expose an unimplemented CSR so we can test non-existent register access # behavior. riscv expose_csrs 2288