From: Iago Toral Quiroga Date: Mon, 21 May 2018 12:34:01 +0000 (+0200) Subject: intel/compiler: add instruction setters for Src1Type and Src2Type. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ab2b97a8fbc8fb07534ec92c9c5326889af290f;p=mesa.git intel/compiler: add instruction setters for Src1Type and Src2Type. The original SrcType is a 3-bit field that takes a subset of the types supported for the hardware for 3-source instructions. Since gen8, when the half-float type was added, 3-source floating point operations can use use mixed precision mode, where not all the operands have the same floating-point precision. While the precision for the first operand is taken from the type in SrcType, the bits in Src1Type (bit 36) and Src2Type (bit 35) define the precision for the other operands (0: normal precision, 1: half precision). Reviewed-by: Topi Pohjolainen Reviewed-by: Matt Turner Acked-by: Jason Ekstrand --- diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index 71316f12215..1f55d45125d 100644 --- a/src/intel/compiler/brw_inst.h +++ b/src/intel/compiler/brw_inst.h @@ -222,6 +222,8 @@ F8(3src_src1_negate, 39, 39, 40, 40) F8(3src_src1_abs, 38, 38, 39, 39) F8(3src_src0_negate, 37, 37, 38, 38) F8(3src_src0_abs, 36, 36, 37, 37) +F8(3src_a16_src1_type, -1, -1, 36, 36) +F8(3src_a16_src2_type, -1, -1, 35, 35) F8(3src_a16_flag_reg_nr, 34, 34, 33, 33) F8(3src_a16_flag_subreg_nr, 33, 33, 32, 32) FF(3src_a16_dst_reg_file,