From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Mon, 8 Jun 2020 16:50:03 +0000 (+0200)
Subject: Rework RAM port for nMigen compliance
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ab34c982c8e182b8c9ced5d5afc58777984a6b4;p=gram.git

Rework RAM port for nMigen compliance
---

diff --git a/gram/core/crossbar.py b/gram/core/crossbar.py
index 1ca18e7..c81abc7 100644
--- a/gram/core/crossbar.py
+++ b/gram/core/crossbar.py
@@ -72,14 +72,13 @@ class gramCrossbar(Elaboratable):
         self.rank_bits = log2_int(self.nranks, False)
 
         self.masters = []
+        self._pending_submodules = []
 
     def get_port(self, mode="both", data_width=None, clock_domain="sys", reverse=False):
-        if self.finalized:
-            raise FinalizeError
-
         if data_width is None:
             # use internal data_width when no width adaptation is requested
             data_width = self.controller.data_width
+            print("data_width=", data_width)
 
         # Crossbar port ----------------------------------------------------------------------------
         port = gramNativePort(
@@ -98,7 +97,7 @@ class gramCrossbar(Elaboratable):
                 data_width    = port.data_width,
                 clock_domain  = clock_domain,
                 id            = port.id)
-            self.submodules += gramNativePortCDC(new_port, port)
+            self._pending_submodules.append(gramNativePortCDC(new_port, port))
             port = new_port
 
         # Data width convertion --------------------------------------------------------------------
@@ -113,8 +112,8 @@ class gramCrossbar(Elaboratable):
                 data_width    = data_width,
                 clock_domain  = clock_domain,
                 id            = port.id)
-            self.submodules += ClockDomainsRenamer(clock_domain)(
-                LiteDRAMNativePortConverter(new_port, port, reverse))
+            self._pending_submodules.append(ClockDomainsRenamer(clock_domain)(
+                gramNativePortConverter(new_port, port, reverse)))
             port = new_port
 
         return port
@@ -122,6 +121,8 @@ class gramCrossbar(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
+        m.submodules += self._pending_submodules
+
         controller = self.controller
         nmasters   = len(self.masters)
 
@@ -203,7 +204,7 @@ class gramCrossbar(Elaboratable):
                 ]
             for nm, master in enumerate(self.masters):
                 with m.Case(2**nm):
-                    m.d.comb = [
+                    m.d.comb += [
                         controller.wdata.eq(master.wdata.data),
                         controller.wdata_we.eq(master.wdata.we),
                     ]