From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 1 Oct 2020 14:56:37 +0000 (+0000)
Subject: add I2C, allow sys_clk_i and sys_pll_48_o out
X-Git-Tag: partial-core-ls180-gdsii~54
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ae1a3c4a3a56b5fd8ca44ac36d1298f68a29b1e;p=soclayout.git

add I2C, allow sys_clk_i and sys_pll_48_o out
---

diff --git a/experiments9/coriolis2/ioring.py b/experiments9/coriolis2/ioring.py
index f06c681..ce856c9 100644
--- a/experiments9/coriolis2/ioring.py
+++ b/experiments9/coriolis2/ioring.py
@@ -48,8 +48,6 @@ for (padnum, name, _), bank in zip(p.muxed_cells, p.muxed_cells_bank):
             padbank[banknum] = name
             print "sys_rst add", bank, banknum, name
             name = None
-        else:
-            name = ''
         #if name:
         #    iopads.append([pname, name, name])
     # SPI Card
@@ -129,6 +127,14 @@ for (padnum, name, _), bank in zip(p.muxed_cells, p.muxed_cells_bank):
         pad = ['p_' + name, name, name2 % 'o', name2 % 'i', name2 % 'oe']
         print ("GPIO pad", name, pad)
         iopads.append(pad)
+    # I2C
+    elif name.startswith('twi'):
+        name = 'i2c' + name[3:]
+        if name.startswith('i2c_sda'):
+            name2 = 'i2c_sda_%s'
+            pad = ['p_' + name, name, name2 % 'o', name2 % 'i', name2 % 'oe']
+            print ("I2C pad", name, pad)
+            iopads.append(pad)
     # EINT
     elif name.startswith('eint'):
         i = name[-1]
@@ -187,8 +193,8 @@ chip = { 'pads.ioPadGauge' : 'pxlib',
           'pads.west'       : pw,
             #[ 'f_3', 'f_2'       , 'p_clk_0', 'f_1'       , 'f_0'     ]
           # core option (big, time-consuming)
-          #'core.size'       : ( l(27500), l(27500) ),
-          #'chip.size'       : ( l(30000), l(30000) ),
+          #'core.size'       : ( l(28000), l(28000) ),
+          #'chip.size'       : ( l(30200), l(30200) ),
           # no-core option (test_issuer but no actual core)
           'core.size'       : ( l(13000), l(13000) ),
           'chip.size'       : ( l(17000), l(17000) ),
diff --git a/experiments9/coriolis2/settings.py b/experiments9/coriolis2/settings.py
index e964021..7e86ca9 100644
--- a/experiments9/coriolis2/settings.py
+++ b/experiments9/coriolis2/settings.py
@@ -61,7 +61,7 @@ with CfgCache('', priority=Cfg.Parameter.Priority.UserFile) as cfg:
 env = CRL.AllianceFramework.get().getEnvironment()
 #env.setCLOCK ('^sys_clk.*|^sys_rst.*')
 #env.setCLOCK ('^clk$|^rst$|ck|cki')
-env.setCLOCK ('^sys_clk.*|^cki$|^ck$')
+env.setCLOCK ('^sys_clk$|^cki$|^ck$')
 #env.setCLOCK ('clk|ck|cki')
 env.setPOWER ('vdd')
 env.setGROUND('vss')