From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 13 Dec 2022 10:38:58 +0000 (-0800)
Subject: working on code some more
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ae9959c37247c50df48c0eca6255c416b7e245c;p=bigint-presentation-code.git

working on code some more
---

diff --git a/src/bigint_presentation_code/_tests/test_register_allocator.py b/src/bigint_presentation_code/_tests/test_register_allocator.py
index 78046fe..0d3ccd2 100644
--- a/src/bigint_presentation_code/_tests/test_register_allocator.py
+++ b/src/bigint_presentation_code/_tests/test_register_allocator.py
@@ -1,5 +1,6 @@
 import sys
 import unittest
+from pathlib import Path
 
 from bigint_presentation_code.compiler_ir import (Fn, GenAsmState, OpKind,
                                                   SSAVal)
@@ -41,22 +42,37 @@ class TestRegisterAllocator(unittest.TestCase):
 
         self.assertEqual(
             repr(reg_assignments),
-            "{<add.outputs[0]: <I64*32>>: "
+            "{"
+            "<add.outputs[0]: <I64*32>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
+            "<add.out0.copy.outputs[0]: <I64*32>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
+            "<st.inp0.copy.outputs[0]: <I64*32>>: "
             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
             "<add.inp1.copy.outputs[0]: <I64*32>>: "
             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
+            "<li.outputs[0]: <I64*32>>: "
+            "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
+            "<li.out0.copy.outputs[0]: <I64*32>>: "
+            "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
             "<add.inp0.copy.outputs[0]: <I64*32>>: "
             "Loc(kind=LocKind.GPR, start=78, reg_len=32), "
-            "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: "
-            "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
+            "<ld.out0.copy.outputs[0]: <I64*32>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
+            "<ld.outputs[0]: <I64*32>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
+            "<arg.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
+            "<arg.out0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
+            "<ld.inp0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
             "<st.inp1.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
-            "<st.inp0.copy.outputs[0]: <I64*32>>: "
-            "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
+            "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: "
+            "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
             "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<add.out0.copy.outputs[0]: <I64*32>>: "
-            "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
             "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
             "<ca.outputs[0]: <CA>>: "
@@ -69,30 +85,17 @@ class TestRegisterAllocator(unittest.TestCase):
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
             "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<li.out0.copy.outputs[0]: <I64*32>>: "
-            "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
             "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<li.outputs[0]: <I64*32>>: "
-            "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
             "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<ld.out0.copy.outputs[0]: <I64*32>>: "
-            "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
             "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<ld.outputs[0]: <I64*32>>: "
-            "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
             "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<ld.inp0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
             "<vl.outputs[0]: <VL_MAXVL>>: "
-            "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<arg.out0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
-            "<arg.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=3, reg_len=1)}"
+            "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1)"
+            "}"
         )
 
     def test_gen_asm(self):
@@ -249,71 +252,51 @@ class TestRegisterAllocator(unittest.TestCase):
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1)"
             "}"
         )
-        # FIXME: is_copy_related is not correct, it's missing a bunch of
-        # edges (which aren't interference edges)
-        self.assertEqual(graphs, {
-            'initial': r"""graph {
-    graph [pack = true]
-    "0" [label = "<arg.outputs[0]: <I64>>: 0"]
-    "1" [label = "<arg.out0.copy.outputs[0]: <I64>>: 0"]
-    "2" [label = "<vl.outputs[0]: <VL_MAXVL>>: 0"]
-    "3" [label = "<ld.inp0.copy.outputs[0]: <I64>>: 0"]
-    "4" [label = "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: 0"]
-    "5" [label = "<ld.outputs[0]: <I64*32>>: 0"]
-    "6" [label = "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: 0"]
-    "7" [label = "<ld.out0.copy.outputs[0]: <I64*32>>: 0"]
-    "8" [label = "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0"]
-    "9" [label = "<li.outputs[0]: <I64*32>>: 0"]
-    "10" [label = "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: 0"]
-    "11" [label = "<li.out0.copy.outputs[0]: <I64*32>>: 0"]
-    "12" [label = "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0"]
-    "13" [label = "<add.inp0.copy.outputs[0]: <I64*32>>: 0"]
-    "14" [label = "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: 0"]
-    "15" [label = "<add.inp1.copy.outputs[0]: <I64*32>>: 0"]
-    "16" [label = "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: 0"]
-    "17" [label = "<add.outputs[0]: <I64*32>>: 0"]
-    "18" [label = "<ca.outputs[0]: <CA>>: 0\n<add.outputs[1]: <CA>>: 0"]
-    "19" [label = "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: 0"]
-    "20" [label = "<add.out0.copy.outputs[0]: <I64*32>>: 0"]
-    "21" [label = "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0"]
-    "22" [label = "<st.inp0.copy.outputs[0]: <I64*32>>: 0"]
-    "23" [label = "<st.inp1.copy.outputs[0]: <I64>>: 0"]
-    "24" [label = "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: 0"]
-    "0" -- "1" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "0" -- "3" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "0" -- "23" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "1" -- "3" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "1" -- "3" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "1" -- "5" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "1" -- "7" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "1" -- "9" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "1" -- "11" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "1" -- "13" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "1" -- "15" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "1" -- "17" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "1" -- "20" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "1" -- "22" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "1" -- "23" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "3" -- "5" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "3" -- "23" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "5" -- "7" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "5" -- "13" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "7" -- "9" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "7" -- "11" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "7" -- "13" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "9" -- "11" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "9" -- "15" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "11" -- "13" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "11" -- "15" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "13" -- "15" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "13" -- "17" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "15" -- "17" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-    "17" -- "20" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "17" -- "22" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "20" -- "22" [label = "copy related", color = "blue", style = "dashed", decorate = true]
-    "22" -- "23" [label = "interferes", color = "darkred", style = "bold", decorate = true]
-}"""
-        })
+        # load expected graphs
+        data_path = Path(__file__).with_suffix("")
+        data_path /= "test_register_allocate_graphs"
+        data_path /= "expected"
+        expected_graphs = {}  # type: dict[str, str]
+        expected_graph_names = [
+            'initial',
+            'step_0_simplify',
+            'step_1_simplify',
+            'step_2_simplify',
+            'step_3_simplify',
+            'step_4_simplify',
+            'step_5_simplify',
+            'step_6_simplify',
+            'step_7_simplify',
+            'step_8_simplify',
+            'step_9_simplify',
+            'step_10_simplify',
+            'step_11_simplify',
+            'step_12_copy_merge',
+            'step_12_copy_merge_result',
+            'step_13_copy_merge',
+            'step_13_copy_merge_result',
+            'step_14_copy_merge',
+            'step_14_copy_merge_result',
+            'step_15_copy_merge',
+            'step_15_copy_merge_result',
+            'step_16_simplify',
+            'step_17_freeze',
+            'step_18_freeze',
+            'step_19_simplify',
+            'step_20_copy_merge',
+            'step_20_copy_merge_result',
+            'step_21_copy_merge',
+            'step_21_copy_merge_result',
+            'step_22_simplify',
+            'step_23_copy_merge',
+            'step_23_copy_merge_result',
+            'step_24_simplify',
+            'final',
+        ]
+        for name in expected_graph_names:
+            file_path = (data_path / name).with_suffix(".dot")
+            expected_graphs[name] = file_path.read_text(encoding="utf-8")
+        self.assertEqual(graphs, expected_graphs)
 
     def test_register_allocate_spread(self):
         fn = Fn()
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/final.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/final.dot
new file mode 100644
index 0000000..ab6820a
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/final.dot
@@ -0,0 +1,33 @@
+graph {
+    graph [pack = true]
+    "2" [label = "<vl.outputs[0]: <VL_MAXVL>>: 0", style = "dotted", color = "black"]
+    "4" [label = "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "dotted", color = "black"]
+    "5" [label = "<ld.outputs[0]: <I64*32>>: 0", style = "dotted", color = "black"]
+    "6" [label = "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "dotted", color = "black"]
+    "7" [label = "<ld.out0.copy.outputs[0]: <I64*32>>: 0", style = "dotted", color = "black"]
+    "8" [label = "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "dotted", color = "black"]
+    "10" [label = "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "dotted", color = "black"]
+    "13" [label = "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "dotted", color = "black"]
+    "14" [label = "<add.inp0.copy.outputs[0]: <I64*32>>: 0", style = "dotted", color = "black"]
+    "15" [label = "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "dotted", color = "black"]
+    "17" [label = "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "dotted", color = "black"]
+    "20" [label = "<ca.outputs[0]: <CA>>: 0\n<add.outputs[1]: <CA>>: 0", style = "dotted", color = "black"]
+    "21" [label = "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "dotted", color = "black"]
+    "23" [label = "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "dotted", color = "black"]
+    "26" [label = "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "dotted", color = "black"]
+    "30" [label = "<arg.outputs[0]: <I64>>: 0\n<arg.out0.copy.outputs[0]: <I64>>: 0\n<ld.inp0.copy.outputs[0]: <I64>>: 0\n<st.inp1.copy.outputs[0]: <I64>>: 0", style = "dotted", color = "black"]
+    "32" [label = "<add.inp1.copy.outputs[0]: <I64*32>>: 0\n<li.outputs[0]: <I64*32>>: 0\n<li.out0.copy.outputs[0]: <I64*32>>: 0", style = "dotted", color = "black"]
+    "33" [label = "<add.outputs[0]: <I64*32>>: 0\n<add.out0.copy.outputs[0]: <I64*32>>: 0\n<st.inp0.copy.outputs[0]: <I64*32>>: 0", style = "dotted", color = "black"]
+    "5" -- "7" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "5" -- "14" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "5" -- "30" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "7" -- "14" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "7" -- "30" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "7" -- "32" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "14" -- "30" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "14" -- "32" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "14" -- "33" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "30" -- "32" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "30" -- "33" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "32" -- "33" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+}
\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/initial.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/initial.dot
new file mode 100644
index 0000000..052d010
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/initial.dot
@@ -0,0 +1,60 @@
+graph {
+    graph [pack = true]
+    "0" [label = "<arg.outputs[0]: <I64>>: 0", style = "solid", color = "black"]
+    "1" [label = "<arg.out0.copy.outputs[0]: <I64>>: 0", style = "solid", color = "black"]
+    "2" [label = "<vl.outputs[0]: <VL_MAXVL>>: 0", style = "solid", color = "black"]
+    "3" [label = "<ld.inp0.copy.outputs[0]: <I64>>: 0", style = "solid", color = "black"]
+    "4" [label = "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "solid", color = "black"]
+    "5" [label = "<ld.outputs[0]: <I64*32>>: 0", style = "solid", color = "black"]
+    "6" [label = "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "solid", color = "black"]
+    "7" [label = "<ld.out0.copy.outputs[0]: <I64*32>>: 0", style = "solid", color = "black"]
+    "8" [label = "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "solid", color = "black"]
+    "9" [label = "<li.outputs[0]: <I64*32>>: 0", style = "solid", color = "black"]
+    "10" [label = "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "solid", color = "black"]
+    "11" [label = "<li.out0.copy.outputs[0]: <I64*32>>: 0", style = "solid", color = "black"]
+    "13" [label = "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "solid", color = "black"]
+    "14" [label = "<add.inp0.copy.outputs[0]: <I64*32>>: 0", style = "solid", color = "black"]
+    "15" [label = "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "solid", color = "black"]
+    "16" [label = "<add.inp1.copy.outputs[0]: <I64*32>>: 0", style = "solid", color = "black"]
+    "17" [label = "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "solid", color = "black"]
+    "18" [label = "<add.outputs[0]: <I64*32>>: 0", style = "solid", color = "black"]
+    "20" [label = "<ca.outputs[0]: <CA>>: 0\n<add.outputs[1]: <CA>>: 0", style = "solid", color = "black"]
+    "21" [label = "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "solid", color = "black"]
+    "22" [label = "<add.out0.copy.outputs[0]: <I64*32>>: 0", style = "solid", color = "black"]
+    "23" [label = "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "solid", color = "black"]
+    "24" [label = "<st.inp0.copy.outputs[0]: <I64*32>>: 0", style = "solid", color = "black"]
+    "25" [label = "<st.inp1.copy.outputs[0]: <I64>>: 0", style = "solid", color = "black"]
+    "26" [label = "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: 0", style = "solid", color = "black"]
+    "0" -- "1" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "0" -- "3" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "0" -- "25" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "1" -- "3" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "1" -- "25" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "1" -- "5" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "1" -- "7" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "1" -- "9" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "1" -- "11" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "1" -- "14" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "1" -- "16" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "1" -- "18" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "1" -- "22" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "1" -- "24" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "3" -- "25" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "3" -- "5" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "5" -- "7" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "5" -- "14" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "7" -- "14" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "7" -- "9" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "7" -- "11" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "9" -- "11" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "9" -- "16" [label = "copy related", color = "blue", style = "dashed", decorate = true]
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_0_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_0_simplify.dot
new file mode 100644
index 0000000..6ffd3f0
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_0_simplify.dot
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_10_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_10_simplify.dot
new file mode 100644
index 0000000..f67f9f5
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_10_simplify.dot
@@ -0,0 +1,60 @@
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\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_11_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_11_simplify.dot
new file mode 100644
index 0000000..75236a2
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_11_simplify.dot
@@ -0,0 +1,60 @@
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_12_copy_merge.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_12_copy_merge.dot
new file mode 100644
index 0000000..5943780
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_12_copy_merge.dot
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+}
\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_12_copy_merge_result.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_12_copy_merge_result.dot
new file mode 100644
index 0000000..31bc3e6
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_12_copy_merge_result.dot
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\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_13_copy_merge.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_13_copy_merge.dot
new file mode 100644
index 0000000..c00ae3a
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_13_copy_merge.dot
@@ -0,0 +1,56 @@
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+}
\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_13_copy_merge_result.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_13_copy_merge_result.dot
new file mode 100644
index 0000000..bd6ea29
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_13_copy_merge_result.dot
@@ -0,0 +1,53 @@
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+}
\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_14_copy_merge.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_14_copy_merge.dot
new file mode 100644
index 0000000..39808f3
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_14_copy_merge.dot
@@ -0,0 +1,53 @@
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_14_copy_merge_result.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_14_copy_merge_result.dot
new file mode 100644
index 0000000..e6cc552
--- /dev/null
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_15_copy_merge.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_15_copy_merge.dot
new file mode 100644
index 0000000..af1a89c
--- /dev/null
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_15_copy_merge_result.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_15_copy_merge_result.dot
new file mode 100644
index 0000000..a6ca26d
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_15_copy_merge_result.dot
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\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_16_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_16_simplify.dot
new file mode 100644
index 0000000..a7f4219
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_16_simplify.dot
@@ -0,0 +1,45 @@
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_17_freeze.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_17_freeze.dot
new file mode 100644
index 0000000..dce2898
--- /dev/null
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_18_freeze.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_18_freeze.dot
new file mode 100644
index 0000000..272f3be
--- /dev/null
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_19_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_19_simplify.dot
new file mode 100644
index 0000000..a1c2dff
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_19_simplify.dot
@@ -0,0 +1,45 @@
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\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_1_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_1_simplify.dot
new file mode 100644
index 0000000..5cf2788
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_1_simplify.dot
@@ -0,0 +1,60 @@
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\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_20_copy_merge.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_20_copy_merge.dot
new file mode 100644
index 0000000..6ce62bd
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_20_copy_merge.dot
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\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_20_copy_merge_result.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_20_copy_merge_result.dot
new file mode 100644
index 0000000..d96ef3d
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_20_copy_merge_result.dot
@@ -0,0 +1,40 @@
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\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_21_copy_merge.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_21_copy_merge.dot
new file mode 100644
index 0000000..41f396e
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_21_copy_merge.dot
@@ -0,0 +1,40 @@
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\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_21_copy_merge_result.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_21_copy_merge_result.dot
new file mode 100644
index 0000000..d1dd187
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_21_copy_merge_result.dot
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+}
\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_22_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_22_simplify.dot
new file mode 100644
index 0000000..57de6b2
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_22_simplify.dot
@@ -0,0 +1,36 @@
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\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_23_copy_merge.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_23_copy_merge.dot
new file mode 100644
index 0000000..6e42fa4
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_23_copy_merge.dot
@@ -0,0 +1,36 @@
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\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_23_copy_merge_result.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_23_copy_merge_result.dot
new file mode 100644
index 0000000..37b4e78
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_23_copy_merge_result.dot
@@ -0,0 +1,33 @@
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\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_24_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_24_simplify.dot
new file mode 100644
index 0000000..fa4a77d
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_24_simplify.dot
@@ -0,0 +1,33 @@
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_2_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_2_simplify.dot
new file mode 100644
index 0000000..05a903d
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_2_simplify.dot
@@ -0,0 +1,60 @@
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_3_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_3_simplify.dot
new file mode 100644
index 0000000..966d076
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_4_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_4_simplify.dot
new file mode 100644
index 0000000..297d595
--- /dev/null
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_5_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_5_simplify.dot
new file mode 100644
index 0000000..ed43897
--- /dev/null
+++ b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_5_simplify.dot
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_6_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_6_simplify.dot
new file mode 100644
index 0000000..54989d2
--- /dev/null
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new file mode 100644
index 0000000..4c16bea
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_8_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_8_simplify.dot
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index 0000000..6056005
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diff --git a/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_9_simplify.dot b/src/bigint_presentation_code/_tests/test_register_allocator/test_register_allocate_graphs/expected/step_9_simplify.dot
new file mode 100644
index 0000000..15ea897
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+    "7" -- "14" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "7" -- "9" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "7" -- "11" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "9" -- "11" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "9" -- "16" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "11" -- "16" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "11" -- "14" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "14" -- "16" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "14" -- "18" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "16" -- "18" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+    "18" -- "22" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "18" -- "24" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "22" -- "24" [label = "copy related", color = "blue", style = "dashed", decorate = true]
+    "24" -- "25" [label = "interferes", color = "darkred", style = "bold", decorate = true]
+}
\ No newline at end of file
diff --git a/src/bigint_presentation_code/_tests/test_toom_cook.py b/src/bigint_presentation_code/_tests/test_toom_cook.py
index dc3bb8d..0b1f477 100644
--- a/src/bigint_presentation_code/_tests/test_toom_cook.py
+++ b/src/bigint_presentation_code/_tests/test_toom_cook.py
@@ -491,378 +491,378 @@ class TestToomCook(unittest.TestCase):
             fn, debug_out=sys.stdout, dump_graph=GraphDumper(self))
         self.assertEqual(
             repr(assigned_registers), "{"
-            "<store_dest.inp2.setvl.outputs[0]: <VL_MAXVL>>: "
-            "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<store_dest.inp1.copy.outputs[0]: <I64>>: "
+            "<mul_1_mul_rt_spread.out0.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
-            "<store_dest.inp0.copy.outputs[0]: <I64*6>>: "
-            "Loc(kind=LocKind.GPR, start=4, reg_len=6), "
-            "<store_dest.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
-            "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<dest_setvl.outputs[0]: <VL_MAXVL>>: "
-            "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
+            "<mul_1_pp_concat.inp0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
+            "<mul_1_pp_concat.inp1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
+            "<mul_1_pp_concat.inp2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
+            "<mul_1_pp_concat.inp3.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_1_pp_concat.inp4.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=7, reg_len=1), "
+            "<mul_1_cast_pp_zero.out0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=7, reg_len=1), "
+            "<mul_1_mul_rt_spread.out2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
+            "<mul_1_pp_concat.out0.copy.outputs[0]: <I64*5>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=5), "
+            "<mul_1_add.inp1.copy.outputs[0]: <I64*5>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=5), "
+            "<mul_1_mul.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=3), "
+            "<mul_1_mul.out0.copy.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=3), "
+            "<mul_1_mul_rt_spread.inp0.copy.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=3), "
+            "<mul_1_mul_rt_spread.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
+            "<mul_1_mul_rt_spread.outputs[1]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
+            "<mul_1_mul_rt_spread.outputs[2]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
+            "<mul_1_mul_rt_spread.out1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
+            "<mul_1_pp_concat.outputs[0]: <I64*5>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=5), "
+            "<mul_zero.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_0_mul.inp2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_0_mul.outputs[1]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_1_mul.inp2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_1_mul.outputs[1]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_1_mul.out1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_2_mul.inp2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_2_mul.outputs[1]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_2_mul.out1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_2_mul_rt_spread.out2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
+            "<mul_2_pp_concat.out0.copy.outputs[0]: <I64*4>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=4), "
+            "<mul_2_mul_rt_spread.out1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
+            "<mul_2_pp_concat.outputs[0]: <I64*4>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=4), "
+            "<mul_2_add.inp1.copy.outputs[0]: <I64*4>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=4), "
+            "<mul_2_mul.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=3), "
+            "<mul_2_mul.out0.copy.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=3), "
+            "<mul_2_mul_rt_spread.inp0.copy.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=3), "
+            "<mul_2_mul_rt_spread.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
+            "<mul_2_mul_rt_spread.outputs[1]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
+            "<mul_2_mul_rt_spread.outputs[2]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
+            "<mul_2_mul_rt_spread.out0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
+            "<mul_2_pp_concat.inp0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
+            "<mul_2_pp_concat.inp1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
+            "<mul_2_pp_concat.inp2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
+            "<mul_2_pp_concat.inp3.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_1_cast_pp_zero.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=7, reg_len=1), "
+            "<mul_1_cast_retval_zero.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
+            "<mul_0_mul_rt_spread.inp0.copy.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=3), "
+            "<mul_0_mul_rt_spread.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
+            "<mul_0_mul_rt_spread.outputs[1]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
+            "<mul_0_mul_rt_spread.outputs[2]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
+            "<mul_0_mul_rt_spread.out1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
+            "<mul_0_mul.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=3), "
+            "<mul_0_mul.out0.copy.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=3), "
+            "<mul_1_retval_concat.outputs[0]: <I64*5>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
+            "<mul_1_add.inp0.copy.outputs[0]: <I64*5>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
+            "<mul_0_mul.out1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
+            "<mul_1_retval_concat.out0.copy.outputs[0]: <I64*5>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
+            "<mul_0_mul_rt_spread.out2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
+            "<mul_1_cast_retval_zero.out0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
+            "<mul_1_retval_concat.inp0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
+            "<mul_1_retval_concat.inp1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
+            "<mul_1_retval_concat.inp2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
+            "<mul_1_retval_concat.inp3.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
+            "<mul_1_retval_concat.inp4.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
+            "<mul_1_sum_spread.inp0.copy.outputs[0]: <I64*5>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
+            "<mul_1_sum_spread.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
+            "<mul_1_sum_spread.outputs[1]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
+            "<mul_1_sum_spread.outputs[2]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
+            "<mul_1_sum_spread.outputs[3]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
+            "<mul_1_sum_spread.outputs[4]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
+            "<mul_1_sum_spread.out2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
+            "<mul_2_retval_concat.outputs[0]: <I64*4>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=4), "
+            "<mul_0_mul_rt_spread.out0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
             "<mul_concat.out0.copy.outputs[0]: <I64*6>>: "
-            "Loc(kind=LocKind.GPR, start=3, reg_len=6), "
-            "<mul_concat.out0.setvl.outputs[0]: <VL_MAXVL>>: "
-            "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<mul_concat.outputs[0]: <I64*6>>: "
-            "Loc(kind=LocKind.GPR, start=3, reg_len=6), "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=6), "
+            "<mul_1_sum_spread.out0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
+            "<mul_2_sum_spread.out3.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
+            "<mul_1_sum_spread.out1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
+            "<mul_2_retval_concat.inp0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
+            "<mul_2_retval_concat.inp1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
+            "<mul_2_retval_concat.inp2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
+            "<mul_2_retval_concat.inp3.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
+            "<mul_1_sum_spread.out4.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
+            "<mul_1_sum_spread.out3.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
+            "<mul_2_retval_concat.out0.copy.outputs[0]: <I64*4>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=4), "
+            "<mul_2_add.inp0.copy.outputs[0]: <I64*4>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=4), "
+            "<mul_1_add.outputs[0]: <I64*5>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
+            "<mul_1_add.out0.copy.outputs[0]: <I64*5>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
+            "<mul_2_sum_spread.out0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
             "<mul_concat.inp0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
             "<mul_concat.inp1.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
             "<mul_concat.inp2.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
             "<mul_concat.inp3.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
             "<mul_concat.inp4.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=7, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
             "<mul_concat.inp5.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
+            "<mul_2_add.outputs[0]: <I64*4>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=4), "
+            "<mul_2_add.out0.copy.outputs[0]: <I64*4>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=4), "
+            "<mul_2_sum_spread.inp0.copy.outputs[0]: <I64*4>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=4), "
+            "<mul_2_sum_spread.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
+            "<mul_2_sum_spread.outputs[1]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
+            "<mul_2_sum_spread.outputs[2]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
+            "<mul_2_sum_spread.outputs[3]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
+            "<mul_2_sum_spread.out1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
+            "<mul_concat.outputs[0]: <I64*6>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=6), "
+            "<mul_2_sum_spread.out2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
+            "<store_dest.inp0.copy.outputs[0]: <I64*6>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=6), "
+            "<mul_zero.out0.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=8, reg_len=1), "
-            "<mul_concat.inp6.setvl.outputs[0]: <VL_MAXVL>>: "
-            "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<mul_setvl.outputs[0]: <VL_MAXVL>>: "
-            "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<mul_2_sum_spread.out3.copy.outputs[0]: <I64>>: "
+            "<ptr_in.out0.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=9, reg_len=1), "
-            "<mul_2_sum_spread.out2.copy.outputs[0]: <I64>>: "
+            "<store_dest.inp1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=9, reg_len=1), "
+            "<load_lhs.inp0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=9, reg_len=1), "
+            "<load_rhs.inp0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=9, reg_len=1), "
+            "<ptr_in.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
+            "<mul_rhs_spread.out2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=12, reg_len=1), "
+            "<mul_2_mul.inp1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=12, reg_len=1), "
+            "<load_rhs.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=10, reg_len=3), "
+            "<load_rhs.out0.copy.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=10, reg_len=3), "
+            "<mul_rhs_spread.inp0.copy.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=10, reg_len=3), "
+            "<mul_rhs_spread.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=10, reg_len=1), "
-            "<mul_2_sum_spread.out1.copy.outputs[0]: <I64>>: "
+            "<mul_rhs_spread.outputs[1]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=11, reg_len=1), "
-            "<mul_2_sum_spread.out0.copy.outputs[0]: <I64>>: "
+            "<mul_rhs_spread.outputs[2]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=12, reg_len=1), "
-            "<mul_2_sum_spread.outputs[0]: <I64>>: "
+            "<mul_rhs_spread.out0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=10, reg_len=1), "
+            "<mul_0_mul.inp1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=10, reg_len=1), "
+            "<mul_rhs_spread.out1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=11, reg_len=1), "
+            "<mul_1_mul.inp1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=11, reg_len=1), "
+            "<load_lhs.out0.copy.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=20, reg_len=3), "
+            "<load_lhs.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=20, reg_len=3), "
+            "<mul_0_mul.inp0.copy.outputs[0]: <I64*3>>: "
+            "Loc(kind=LocKind.GPR, start=20, reg_len=3), "
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             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<mul_zero.out0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=22, reg_len=1), "
-            "<mul_zero.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
-            "<mul_rhs_spread.out2.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=23, reg_len=1), "
-            "<mul_rhs_spread.out1.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
-            "<mul_rhs_spread.out0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
-            "<mul_rhs_spread.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
-            "<mul_rhs_spread.outputs[1]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
-            "<mul_rhs_spread.outputs[2]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=7, reg_len=1), "
             "<mul_rhs_spread.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<mul_rhs_spread.inp0.copy.outputs[0]: <I64*3>>: "
-            "Loc(kind=LocKind.GPR, start=3, reg_len=3), "
             "<mul_rhs_spread.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
             "<mul_rhs_setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<load_rhs.out0.copy.outputs[0]: <I64*3>>: "
-            "Loc(kind=LocKind.GPR, start=3, reg_len=3), "
             "<load_rhs.out0.setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<load_rhs.outputs[0]: <I64*3>>: "
-            "Loc(kind=LocKind.GPR, start=3, reg_len=3), "
             "<load_rhs.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<load_rhs.inp0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
             "<rhs_setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<load_lhs.out0.copy.outputs[0]: <I64*3>>: "
-            "Loc(kind=LocKind.GPR, start=24, reg_len=3), "
             "<load_lhs.out0.setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<load_lhs.outputs[0]: <I64*3>>: "
-            "Loc(kind=LocKind.GPR, start=3, reg_len=3), "
             "<load_lhs.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<load_lhs.inp0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
             "<lhs_setvl.outputs[0]: <VL_MAXVL>>: "
-            "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
-            "<ptr_in.out0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=27, reg_len=1), "
-            "<ptr_in.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=3, reg_len=1)"
+            "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1)"
             "}")
 
     def test_simple_mul_192x192_asm(self):
diff --git a/src/bigint_presentation_code/compiler_ir.py b/src/bigint_presentation_code/compiler_ir.py
index 4f8fb79..2d19492 100644
--- a/src/bigint_presentation_code/compiler_ir.py
+++ b/src/bigint_presentation_code/compiler_ir.py
@@ -9,11 +9,12 @@ from typing import (AbstractSet, Any, Callable, Generic, Iterable, Iterator,
 from weakref import WeakValueDictionary as _WeakVDict
 
 from cached_property import cached_property
-from nmutil.plain_data import fields, plain_data
+from dataclasses import dataclass
+from nmutil import plain_data  # type: ignore
 
 from bigint_presentation_code.type_util import (Literal, Self, assert_never,
                                                 final)
-from bigint_presentation_code.util import (BitSet, FBitSet, FMap, InternedMeta,
+from bigint_presentation_code.util import (BitSet, FBitSet, FMap, Interned,
                                            OFSet, OSet)
 
 GPR_SIZE_IN_BYTES = 8
@@ -209,16 +210,11 @@ class OpStage(Enum):
 assert OpStage.Early < OpStage.Late, "early must be less than late"
 
 
-@plain_data(frozen=True, unsafe_hash=True, repr=False)
+@dataclass(frozen=True, unsafe_hash=True, repr=False)
 @final
-@total_ordering
-class ProgramPoint(metaclass=InternedMeta):
-    __slots__ = "op_index", "stage"
-
-    def __init__(self, op_index, stage):
-        # type: (int, OpStage) -> None
-        self.op_index = op_index
-        self.stage = stage
+class ProgramPoint(Interned):
+    op_index: int
+    stage: OpStage
 
     @property
     def int_value(self):
@@ -250,20 +246,34 @@ class ProgramPoint(metaclass=InternedMeta):
             return self.op_index < other.op_index
         return self.stage < other.stage
 
+    def __gt__(self, other):
+        # type: (ProgramPoint | Any) -> bool
+        if not isinstance(other, ProgramPoint):
+            return NotImplemented
+        return other.__lt__(self)
+
+    def __le__(self, other):
+        # type: (ProgramPoint | Any) -> bool
+        if not isinstance(other, ProgramPoint):
+            return NotImplemented
+        return not self.__gt__(other)
+
+    def __ge__(self, other):
+        # type: (ProgramPoint | Any) -> bool
+        if not isinstance(other, ProgramPoint):
+            return NotImplemented
+        return not self.__lt__(other)
+
     def __repr__(self):
         # type: () -> str
         return f"<ops[{self.op_index}]:{self.stage._name_}>"
 
 
-@plain_data(frozen=True, unsafe_hash=True, repr=False)
+@dataclass(frozen=True, unsafe_hash=True, repr=False)
 @final
-class ProgramRange(Sequence[ProgramPoint], metaclass=InternedMeta):
-    __slots__ = "start", "stop"
-
-    def __init__(self, start, stop):
-        # type: (ProgramPoint, ProgramPoint) -> None
-        self.start = start
-        self.stop = stop
+class ProgramRange(Sequence[ProgramPoint], Interned):
+    start: ProgramPoint
+    stop: ProgramPoint
 
     @cached_property
     def int_value_range(self):
@@ -311,24 +321,22 @@ class ProgramRange(Sequence[ProgramPoint], metaclass=InternedMeta):
         return f"<range:{start}..{stop}>"
 
 
-@plain_data(frozen=True, unsafe_hash=True, repr=False)
+@dataclass(frozen=True, unsafe_hash=True, repr=False)
 @final
-class SSAValSubReg(metaclass=InternedMeta):
-    __slots__ = "ssa_val", "reg_idx"
+class SSAValSubReg(Interned):
+    ssa_val: "SSAVal"
+    reg_idx: int
 
-    def __init__(self, ssa_val, reg_idx):
-        # type: (SSAVal, int) -> None
-        if reg_idx < 0 or reg_idx >= ssa_val.ty.reg_len:
+    def __post_init__(self):
+        if self.reg_idx < 0 or self.reg_idx >= self.ssa_val.ty.reg_len:
             raise ValueError("reg_idx out of range")
-        self.ssa_val = ssa_val
-        self.reg_idx = reg_idx
 
     def __repr__(self):
         # type: () -> str
         return f"{self.ssa_val}[{self.reg_idx}]"
 
 
-@plain_data(frozen=True, eq=False, repr=False)
+@plain_data.plain_data(frozen=True, eq=False, repr=False)
 @final
 class FnAnalysis:
     __slots__ = ("fn", "uses", "op_indexes", "live_ranges", "live_at",
@@ -542,10 +550,11 @@ class BaseTy(Enum):
         return "BaseTy." + self._name_
 
 
-@plain_data(frozen=True, unsafe_hash=True, repr=False)
+@dataclass(frozen=True, unsafe_hash=True, repr=False)
 @final
-class Ty(metaclass=InternedMeta):
-    __slots__ = "base_ty", "reg_len"
+class Ty(Interned):
+    base_ty: BaseTy
+    reg_len: int
 
     @staticmethod
     def validate(base_ty, reg_len):
@@ -559,13 +568,10 @@ class Ty(metaclass=InternedMeta):
             return "reg_len out of range"
         return None
 
-    def __init__(self, base_ty, reg_len):
-        # type: (BaseTy, int) -> None
-        msg = self.validate(base_ty=base_ty, reg_len=reg_len)
+    def __post_init__(self):
+        msg = self.validate(base_ty=self.base_ty, reg_len=self.reg_len)
         if msg is not None:
             raise ValueError(msg)
-        self.base_ty = base_ty
-        self.reg_len = reg_len
 
     def __repr__(self):
         # type: () -> str
@@ -682,17 +688,15 @@ class LocSubKind(Enum):
         return "LocSubKind." + self._name_
 
 
-@plain_data(frozen=True, unsafe_hash=True)
+@dataclass(frozen=True, unsafe_hash=True)
 @final
-class GenericTy(metaclass=InternedMeta):
-    __slots__ = "base_ty", "is_vec"
+class GenericTy(Interned):
+    base_ty: BaseTy
+    is_vec: bool
 
-    def __init__(self, base_ty, is_vec):
-        # type: (BaseTy, bool) -> None
-        self.base_ty = base_ty
-        if base_ty.only_scalar and is_vec:
-            raise ValueError(f"base_ty={base_ty} requires is_vec=False")
-        self.is_vec = is_vec
+    def __post_init__(self):
+        if self.base_ty.only_scalar and self.is_vec:
+            raise ValueError(f"base_ty={self.base_ty} requires is_vec=False")
 
     def instantiate(self, maxvl):
         # type: (int) -> Ty
@@ -710,10 +714,12 @@ class GenericTy(metaclass=InternedMeta):
         return ty.reg_len == 1
 
 
-@plain_data(frozen=True, unsafe_hash=True)
+@dataclass(frozen=True, unsafe_hash=True)
 @final
-class Loc(metaclass=InternedMeta):
-    __slots__ = "kind", "start", "reg_len"
+class Loc(Interned):
+    kind: LocKind
+    start: int
+    reg_len: int
 
     @staticmethod
     def validate(kind, start, reg_len):
@@ -735,14 +741,11 @@ class Loc(metaclass=InternedMeta):
             return None
         return Loc(kind=kind, start=start, reg_len=reg_len)
 
-    def __init__(self, kind, start, reg_len):
-        # type: (LocKind, int, int) -> None
-        msg = self.validate(kind=kind, start=start, reg_len=reg_len)
+    def __post_init__(self):
+        msg = self.validate(kind=self.kind, start=self.start,
+                            reg_len=self.reg_len)
         if msg is not None:
             raise ValueError(msg)
-        self.kind = kind
-        self.reg_len = reg_len
-        self.start = start
 
     def conflicts(self, other):
         # type: (Loc) -> bool
@@ -811,7 +814,7 @@ SPECIAL_GPRS = (
 
 
 @final
-class LocSet(OFSet[Loc], metaclass=InternedMeta):
+class LocSet(OFSet[Loc], Interned):
     def __init__(self, __locs=()):
         # type: (Iterable[Loc]) -> None
         super().__init__(__locs)
@@ -927,12 +930,16 @@ class LocSet(OFSet[Loc], metaclass=InternedMeta):
         return only_loc
 
 
-@plain_data(frozen=True, unsafe_hash=True)
+@dataclass(frozen=True, unsafe_hash=True)
 @final
-class GenericOperandDesc(metaclass=InternedMeta):
+class GenericOperandDesc(Interned):
     """generic Op operand descriptor"""
-    __slots__ = ("ty", "fixed_loc", "sub_kinds", "tied_input_index", "spread",
-                 "write_stage")
+    ty: GenericTy
+    sub_kinds: OFSet[LocSubKind]
+    fixed_loc: "Loc | None" = None
+    tied_input_index: "int | None" = None
+    spread: bool = False
+    write_stage: OpStage = OpStage.Early
 
     def __init__(
         self, ty,  # type: GenericTy
@@ -944,11 +951,11 @@ class GenericOperandDesc(metaclass=InternedMeta):
         write_stage=OpStage.Early,  # type: OpStage
     ):
         # type: (...) -> None
-        self.ty = ty
-        self.sub_kinds = OFSet(sub_kinds)
+        object.__setattr__(self, "ty", ty)
+        object.__setattr__(self, "sub_kinds", OFSet(sub_kinds))
         if len(self.sub_kinds) == 0:
             raise ValueError("sub_kinds can't be empty")
-        self.fixed_loc = fixed_loc
+        object.__setattr__(self, "fixed_loc", fixed_loc)
         if fixed_loc is not None:
             if tied_input_index is not None:
                 raise ValueError("operand can't be both tied and fixed")
@@ -970,8 +977,8 @@ class GenericOperandDesc(metaclass=InternedMeta):
                                  f"sub_kind={sub_kind} ty={ty}")
         if tied_input_index is not None and tied_input_index < 0:
             raise ValueError("invalid tied_input_index")
-        self.tied_input_index = tied_input_index
-        self.spread = spread
+        object.__setattr__(self, "tied_input_index", tied_input_index)
+        object.__setattr__(self, "spread", spread)
         if spread:
             if self.tied_input_index is not None:
                 raise ValueError("operand can't be both spread and tied")
@@ -979,7 +986,7 @@ class GenericOperandDesc(metaclass=InternedMeta):
                 raise ValueError("operand can't be both spread and fixed")
             if self.ty.is_vec:
                 raise ValueError("operand can't be both spread and vector")
-        self.write_stage = write_stage
+        object.__setattr__(self, "write_stage", write_stage)
 
     @cached_property
     def ty_before_spread(self):
@@ -1036,24 +1043,20 @@ class GenericOperandDesc(metaclass=InternedMeta):
                               spread_index=idx, write_stage=self.write_stage)
 
 
-@plain_data(frozen=True, unsafe_hash=True)
+@dataclass(frozen=True, unsafe_hash=True)
 @final
-class OperandDesc(metaclass=InternedMeta):
+class OperandDesc(Interned):
     """Op operand descriptor"""
-    __slots__ = ("loc_set_before_spread", "tied_input_index", "spread_index",
-                 "write_stage")
+    loc_set_before_spread: LocSet
+    tied_input_index: "int | None"
+    spread_index: "int | None"
+    write_stage: "OpStage"
 
-    def __init__(self, loc_set_before_spread, tied_input_index, spread_index,
-                 write_stage):
-        # type: (LocSet, int | None, int | None, OpStage) -> None
-        if len(loc_set_before_spread) == 0:
+    def __post_init__(self):
+        if len(self.loc_set_before_spread) == 0:
             raise ValueError("loc_set_before_spread must not be empty")
-        self.loc_set_before_spread = loc_set_before_spread
-        self.tied_input_index = tied_input_index
-        if self.tied_input_index is not None and spread_index is not None:
+        if self.tied_input_index is not None and self.spread_index is not None:
             raise ValueError("operand can't be both spread and tied")
-        self.spread_index = spread_index
-        self.write_stage = write_stage
 
     @cached_property
     def ty_before_spread(self):
@@ -1109,11 +1112,16 @@ OD_VL = GenericOperandDesc(
     sub_kinds=[LocSubKind.VL_MAXVL])
 
 
-@plain_data(frozen=True, unsafe_hash=True)
+@dataclass(frozen=True, unsafe_hash=True)
 @final
-class GenericOpProperties(metaclass=InternedMeta):
-    __slots__ = ("demo_asm", "inputs", "outputs", "immediates",
-                 "is_copy", "is_load_immediate", "has_side_effects")
+class GenericOpProperties(Interned):
+    demo_asm: str
+    inputs: "tuple[GenericOperandDesc, ...]"
+    outputs: "tuple[GenericOperandDesc, ...]"
+    immediates: "tuple[range, ...]"
+    is_copy: bool
+    is_load_immediate: bool
+    has_side_effects: bool
 
     def __init__(
         self, demo_asm,  # type: str
@@ -1125,8 +1133,8 @@ class GenericOpProperties(metaclass=InternedMeta):
         has_side_effects=False,  # type: bool
     ):
         # type: (...) -> None
-        self.demo_asm = demo_asm  # type: str
-        self.inputs = tuple(inputs)  # type: tuple[GenericOperandDesc, ...]
+        object.__setattr__(self, "demo_asm", demo_asm)
+        object.__setattr__(self, "inputs", tuple(inputs))
         for inp in self.inputs:
             if inp.tied_input_index is not None:
                 raise ValueError(
@@ -1134,7 +1142,7 @@ class GenericOpProperties(metaclass=InternedMeta):
             if inp.write_stage is not OpStage.Early:
                 raise ValueError(
                     f"write_stage is not allowed on inputs: {inp}")
-        self.outputs = tuple(outputs)  # type: tuple[GenericOperandDesc, ...]
+        object.__setattr__(self, "outputs", tuple(outputs))
         fixed_locs = []  # type: list[tuple[Loc, int]]
         for idx, out in enumerate(self.outputs):
             if out.tied_input_index is not None:
@@ -1155,15 +1163,15 @@ class GenericOpProperties(metaclass=InternedMeta):
                         f"outputs[{other_idx}]: {out.fixed_loc} conflicts "
                         f"with {other_fixed_loc}")
                 fixed_locs.append((out.fixed_loc, idx))
-        self.immediates = tuple(immediates)  # type: tuple[range, ...]
-        self.is_copy = is_copy  # type: bool
-        self.is_load_immediate = is_load_immediate  # type: bool
-        self.has_side_effects = has_side_effects  # type: bool
+        object.__setattr__(self, "immediates", tuple(immediates))
+        object.__setattr__(self, "is_copy", is_copy)
+        object.__setattr__(self, "is_load_immediate", is_load_immediate)
+        object.__setattr__(self, "has_side_effects", has_side_effects)
 
 
-@plain_data(frozen=True, unsafe_hash=True)
+@plain_data.plain_data(frozen=True, unsafe_hash=True)
 @final
-class OpProperties(metaclass=InternedMeta):
+class OpProperties:
     __slots__ = "kind", "inputs", "outputs", "maxvl", "copy_reg_len"
 
     def __init__(self, kind, maxvl):
@@ -1886,17 +1894,15 @@ class OpKind(Enum):
     _GEN_ASMS[FuncArgR3] = lambda: OpKind.__funcargr3_gen_asm
 
 
-@plain_data(frozen=True, unsafe_hash=True, repr=False)
-class SSAValOrUse(metaclass=InternedMeta):
-    __slots__ = "op", "operand_idx"
+@dataclass(frozen=True, unsafe_hash=True, repr=False)
+class SSAValOrUse(Interned):
+    op: "Op"
+    operand_idx: int
 
-    def __init__(self, op, operand_idx):
-        # type: (Op, int) -> None
-        super().__init__()
-        self.op = op
-        if operand_idx < 0 or operand_idx >= len(self.descriptor_array):
+    def __post_init__(self):
+        if self.operand_idx < 0 or \
+                self.operand_idx >= len(self.descriptor_array):
             raise ValueError("invalid operand_idx")
-        self.operand_idx = operand_idx
 
     @abstractmethod
     def __repr__(self):
@@ -1951,7 +1957,7 @@ class SSAValOrUse(metaclass=InternedMeta):
         return self.__class__(op=self.op, operand_idx=self.unspread_start_idx)
 
 
-@plain_data(frozen=True, unsafe_hash=True, repr=False)
+@dataclass(frozen=True, unsafe_hash=True, repr=False)
 @final
 class SSAVal(SSAValOrUse):
     __slots__ = ()
@@ -2002,7 +2008,7 @@ class SSAVal(SSAValOrUse):
         return tuple(SSAValSubReg(self, i) for i in range(self.ty.reg_len))
 
 
-@plain_data(frozen=True, unsafe_hash=True, repr=False)
+@dataclass(frozen=True, unsafe_hash=True, repr=False)
 @final
 class SSAUse(SSAValOrUse):
     __slots__ = ()
@@ -2170,7 +2176,7 @@ class OpImmediates(OpInputSeq[int, range]):
         super().__init__(items, op)
 
 
-@plain_data(frozen=True, eq=False, repr=False)
+@plain_data.plain_data(frozen=True, eq=False, repr=False)
 @final
 class Op:
     __slots__ = ("fn", "properties", "input_vals", "input_uses", "immediates",
@@ -2301,7 +2307,7 @@ class Op:
         self.kind.gen_asm(self, state)
 
 
-@plain_data(frozen=True, repr=False)
+@plain_data.plain_data(frozen=True, repr=False)
 class BaseSimState(metaclass=ABCMeta):
     __slots__ = "memory",
 
@@ -2378,7 +2384,7 @@ class BaseSimState(metaclass=ABCMeta):
     def __repr__(self):
         # type: () -> str
         field_vals = []  # type: list[str]
-        for name in fields(self):
+        for name in plain_data.fields(self):
             try:
                 value = getattr(self, name)
             except AttributeError:
@@ -2403,7 +2409,7 @@ class BaseSimState(metaclass=ABCMeta):
         ...
 
 
-@plain_data(frozen=True, repr=False)
+@plain_data.plain_data(frozen=True, repr=False)
 class PreRABaseSimState(BaseSimState):
     __slots__ = "ssa_vals",
 
@@ -2459,7 +2465,7 @@ class SimSkipOp(Exception):
     pass
 
 
-@plain_data(frozen=True, repr=False)
+@plain_data.plain_data(frozen=True, repr=False)
 @final
 class ConstPropagationState(PreRABaseSimState):
     __slots__ = "skipped_ops",
@@ -2482,7 +2488,7 @@ class ConstPropagationState(PreRABaseSimState):
         self.skipped_ops.add(op)
 
 
-@plain_data(frozen=True, repr=False)
+@plain_data.plain_data(frozen=True, repr=False)
 class PreRASimState(PreRABaseSimState):
     __slots__ = ()
 
@@ -2517,7 +2523,7 @@ class PreRASimState(PreRABaseSimState):
         return PreRASimState.__CURRENT_DEBUGGING_STATE[-1]
 
 
-@plain_data(frozen=True, repr=False)
+@plain_data.plain_data(frozen=True, repr=False)
 @final
 class PostRASimState(BaseSimState):
     __slots__ = "ssa_val_to_loc_map", "loc_values"
@@ -2569,7 +2575,7 @@ class PostRASimState(BaseSimState):
             self.loc_values[subloc] = value[i]
 
 
-@plain_data(frozen=True)
+@plain_data.plain_data(frozen=True)
 class GenAsmState:
     __slots__ = "allocated_locs", "output"
 
diff --git a/src/bigint_presentation_code/register_allocator.py b/src/bigint_presentation_code/register_allocator.py
index 0539f0a..8dfdd58 100644
--- a/src/bigint_presentation_code/register_allocator.py
+++ b/src/bigint_presentation_code/register_allocator.py
@@ -5,9 +5,10 @@ this uses an algorithm based on:
 [Retargetable Graph-Coloring Register Allocation for Irregular Architectures](https://user.it.uu.se/~svenolof/wpo/AllocSCOPES2003.20030626b.pdf)
 """
 
+from dataclasses import dataclass
 from functools import lru_cache, reduce
 from itertools import combinations, count
-from typing import Callable, Container, Iterable, Iterator, Mapping, TextIO, Tuple
+from typing import Any, Callable, Container, Iterable, Iterator, Mapping, TextIO, Tuple
 
 from cached_property import cached_property
 from nmutil.plain_data import plain_data, replace
@@ -16,7 +17,7 @@ from bigint_presentation_code.compiler_ir import (BaseTy, Fn, FnAnalysis, Loc,
                                                   LocSet, Op, ProgramRange,
                                                   SSAVal, SSAValSubReg, Ty)
 from bigint_presentation_code.type_util import final
-from bigint_presentation_code.util import FMap, InternedMeta, OFSet, OSet
+from bigint_presentation_code.util import FMap, Interned, OFSet, OSet
 
 
 class BadMergedSSAVal(ValueError):
@@ -26,9 +27,9 @@ class BadMergedSSAVal(ValueError):
 _CopyRelation = Tuple[SSAValSubReg, SSAValSubReg]
 
 
-@plain_data(frozen=True, repr=False)
+@dataclass(frozen=True, repr=False, eq=False)
 @final
-class MergedSSAVal(metaclass=InternedMeta):
+class MergedSSAVal(Interned):
     """a set of `SSAVal`s along with their offsets, all register allocated as
     a single unit.
 
@@ -56,22 +57,25 @@ class MergedSSAVal(metaclass=InternedMeta):
     * `v2` is allocated to `Loc(kind=LocKind.GPR, start=24, reg_len=2)`
     * `v3` is allocated to `Loc(kind=LocKind.GPR, start=21, reg_len=1)`
     """
-    __slots__ = ("fn_analysis", "ssa_val_offsets", "first_ssa_val", "loc_set",
-                 "first_loc")
+    fn_analysis: FnAnalysis
+    ssa_val_offsets: "FMap[SSAVal, int]"
+    first_ssa_val: SSAVal
+    loc_set: LocSet
+    first_loc: Loc
 
     def __init__(self, fn_analysis, ssa_val_offsets, loc_set=None):
         # type: (FnAnalysis, Mapping[SSAVal, int] | SSAVal, LocSet | None) -> None
-        self.fn_analysis = fn_analysis
+        object.__setattr__(self, "fn_analysis", fn_analysis)
         if isinstance(ssa_val_offsets, SSAVal):
             ssa_val_offsets = {ssa_val_offsets: 0}
-        self.ssa_val_offsets = FMap(ssa_val_offsets)  # type: FMap[SSAVal, int]
+        object.__setattr__(self, "ssa_val_offsets", FMap(ssa_val_offsets))
         first_ssa_val = None
         for ssa_val in self.ssa_vals:
             first_ssa_val = ssa_val
             break
         if first_ssa_val is None:
             raise BadMergedSSAVal("MergedSSAVal can't be empty")
-        self.first_ssa_val = first_ssa_val  # type: SSAVal
+        object.__setattr__(self, "first_ssa_val", first_ssa_val)
         # self.ty checks for mismatched base_ty
         reg_len = self.ty.reg_len
         if loc_set is not None and loc_set.ty != self.ty:
@@ -113,9 +117,9 @@ class MergedSSAVal(metaclass=InternedMeta):
             break
         if first_loc is None:
             raise BadMergedSSAVal("there are no valid Locs left")
-        self.first_loc = first_loc
+        object.__setattr__(self, "first_loc", first_loc)
         assert loc_set.ty == self.ty, "logic error somewhere"
-        self.loc_set = loc_set  # type: LocSet
+        object.__setattr__(self, "loc_set", loc_set)
         self.__mergable_check()
 
     def __mergable_check(self):
@@ -163,14 +167,17 @@ class MergedSSAVal(metaclass=InternedMeta):
                                               "of the same instruction")
                     vals[reg_offset] = reg
 
-    @cached_property
-    def __hash(self):
+    def __hash__(self):
         # type: () -> int
         return hash((self.fn_analysis, self.ssa_val_offsets, self.loc_set))
 
-    def __hash__(self):
-        # type: () -> int
-        return self.__hash
+    def __eq__(self, other):
+        # type: (MergedSSAVal | Any) -> bool
+        if isinstance(other, MergedSSAVal):
+            return self.fn_analysis == other.fn_analysis and \
+                self.ssa_val_offsets == other.ssa_val_offsets and \
+                self.loc_set == other.loc_set
+        return NotImplemented
 
     @property
     def only_loc(self):
diff --git a/src/bigint_presentation_code/toom_cook.py b/src/bigint_presentation_code/toom_cook.py
index 4ceb3d7..e220104 100644
--- a/src/bigint_presentation_code/toom_cook.py
+++ b/src/bigint_presentation_code/toom_cook.py
@@ -14,7 +14,6 @@ from bigint_presentation_code.compiler_ir import (GPR_SIZE_IN_BITS, BaseTy, Fn,
                                                   OpKind, SSAVal, Ty)
 from bigint_presentation_code.matrix import Matrix
 from bigint_presentation_code.type_util import Literal, final
-from bigint_presentation_code.util import InternedMeta
 
 
 @final
@@ -352,7 +351,7 @@ class EvalOpGenIrState:
 
 
 @plain_data(frozen=True, unsafe_hash=True)
-class EvalOp(metaclass=InternedMeta):
+class EvalOp:
     __slots__ = "lhs", "rhs", "poly"
 
     @property
diff --git a/src/bigint_presentation_code/util.py b/src/bigint_presentation_code/util.py
index 423714a..9d2b7b1 100644
--- a/src/bigint_presentation_code/util.py
+++ b/src/bigint_presentation_code/util.py
@@ -1,6 +1,7 @@
 from abc import ABCMeta, abstractmethod
-from typing import (AbstractSet, Any, Iterable, Iterator, Mapping, MutableSet,
-                    TypeVar, overload)
+from collections import defaultdict
+from typing import (AbstractSet, Any, Callable, Iterable, Iterator, Mapping,
+                    MutableSet, TypeVar, overload)
 
 from bigint_presentation_code.type_util import Self, final
 
@@ -17,45 +18,66 @@ __all__ = [
     "OSet",
     "top_set_bit_index",
     "trailing_zero_count",
-    "InternedMeta",
+    "Interned",
 ]
 
 
-class InternedMeta(ABCMeta):
-    def __init__(self, *args, **kwargs):
-        # type: (*Any, **Any) -> None
-        super().__init__(*args, **kwargs)
-        self.__INTERN_TABLE = {}  # type: dict[Any, Any]
-        self._InternedMeta__interned = False
-
-    def __intern(self, value):
-        # type: (_T) -> _T
-        if value._InternedMeta__interned:  # type: ignore
-            return value
-        value = self.__INTERN_TABLE.setdefault(value, value)
-        if value._InternedMeta__interned:  # type: ignore
-            return value
-        hash_v = hash(value)
-        value.__dict__["__hash__"] = lambda: hash_v
-        old_eq = value.__eq__
-
-        def __eq__(__o):
-            # type: (_T) -> bool
-            if value.__class__ is __o.__class__:
-                if (value._InternedMeta__interned and  # type: ignore
-                        __o._InternedMeta__interned):  # type: ignore
-                    return value is __o
-            return old_eq(__o)
-        value.__dict__["__eq__"] = __eq__
-        value.__dict__["_InternedMeta__interned"] = True
-        return value
-
-    def __call__(self, *args, **kwargs):
-        # type: (*Any, **Any) -> Any
-        return self.__intern(super().__call__(*args, **kwargs))
-
-
-class OFSet(AbstractSet[_T_co], metaclass=InternedMeta):
+class _InternedMeta(ABCMeta):
+    def __call__(self, *args: Any, **kwds: Any) -> Any:
+        return super().__call__(*args, **kwds)._Interned__intern()
+
+
+class Interned(metaclass=_InternedMeta):
+    def __init_intern(self):
+        # type: (Self) -> Self
+        cls = type(self)
+        old_hash = cls.__hash__
+        old_hash = getattr(old_hash, "_Interned__old_hash", old_hash)
+        old_eq = cls.__eq__
+        old_eq = getattr(old_eq, "_Interned__old_eq", old_eq)
+
+        def __hash__(self):
+            # type: (Self) -> int
+            return self._Interned__hash  # type: ignore
+        __hash__._Interned__old_hash = old_hash  # type: ignore
+        cls.__hash__ = __hash__
+
+        def __eq__(self,  # type: Self
+                   __other,  # type: Any
+                   *, __eq=old_eq,  # type: Callable[[Self, Any], bool]
+                   ):
+            # type: (...) -> bool
+            if self.__class__ is __other.__class__:
+                return self is __other
+            return __eq(self, __other)
+        __eq__._Interned__old_eq = old_eq  # type: ignore
+        cls.__eq__ = __eq__
+
+        table = defaultdict(list)  # type: dict[int, list[Self]]
+
+        def __intern(self,  # type: Self
+                     *, __hash=old_hash,  # type: Callable[[Self], int]
+                     __eq=old_eq,  # type: Callable[[Self, Any], bool]
+                     __table=table,  # type: dict[int, list[Self]]
+                     __NotImplemented=NotImplemented,  # type: Any
+                     ):
+            # type: (...) -> Self
+            h = __hash(self)
+            bucket = __table[h]
+            for i in bucket:
+                v = __eq(self, i)
+                if v is not __NotImplemented and v:
+                    return i
+            self.__dict__["_Interned__hash"] = h
+            bucket.append(self)
+            return self
+        cls._Interned__intern = __intern
+        return __intern(self)
+
+    _Interned__intern = __init_intern
+
+
+class OFSet(AbstractSet[_T_co], Interned):
     """ ordered frozen set """
     __slots__ = "__items", "__dict__", "__weakref__"
 
@@ -126,7 +148,7 @@ class OSet(MutableSet[_T]):
         return f"OSet({list(self)})"
 
 
-class FMap(Mapping[_T, _T_co], metaclass=InternedMeta):
+class FMap(Mapping[_T, _T_co], Interned):
     """ordered frozen hashable mapping"""
     __slots__ = "__items", "__hash", "__dict__", "__weakref__"
 
@@ -440,7 +462,7 @@ class BitSet(BaseBitSet, MutableSet[int]):
         return super().__isub__(it)
 
 
-class FBitSet(BaseBitSet, metaclass=InternedMeta):
+class FBitSet(BaseBitSet, Interned):
     """Frozen Bit Set"""
 
     @final