From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 25 Jun 2020 07:18:53 +0000 (+0200)
Subject: optimization, all items should have same attributes
X-Git-Tag: working-ls180~450^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4aec50a863b72b461352b84b15bdb9978c229db9;p=yosys.git

optimization, all items should have same attributes
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 89d734c40..6637c214d 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1112,6 +1112,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 			MapIter mibus;
 			FOREACH_NET_OF_NETBUS(netbus, mibus, net) {
 				import_attributes(wire->attributes, net, nl);
+				break;
 			}
 
 			RTLIL::Const initval = Const(State::Sx, GetSize(wire));