From: Maciej W. Rozycki <macro@imgtec.com>
Date: Wed, 7 Dec 2016 03:12:50 +0000 (+0000)
Subject: MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASK
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4b0781150f69b6ff251dac447c77e4d4f6598da8;p=binutils-gdb.git

MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASK

Complement commit e407c74b5b60 ("Support for MIPS R5900 (Sony Playstation
2)"), <https://sourceware.org/ml/binutils/2012-12/msg00240.html>, and
commit 2c62985659da ("MIPS: Add Octeon 3 support") and update the chip
mask accordingly.

	include/
	* opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
---

diff --git a/include/ChangeLog b/include/ChangeLog
index 7d37b15c239..00cebb6b9d7 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
+
 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 
     	* opcode/mips.h (ASE_DSPR3): Add a comment.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 08bc24f56d0..160fc9166f5 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1194,7 +1194,7 @@ static const unsigned int mips_isa_table[] = {
 #undef ISAF
 
 /* Masks used for Chip specific instructions.  */
-#define INSN_CHIP_MASK		  0xc3ff0f20
+#define INSN_CHIP_MASK		  0xc3ff4f60
 
 /* Cavium Networks Octeon instructions.  */
 #define INSN_OCTEON		  0x00000800