From: Robert Baruch <robert.c.baruch@gmail.com>
Date: Mon, 22 Feb 2021 04:00:31 +0000 (-0800)
Subject: int -> bool
X-Git-Tag: working-ls180~43
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4b31223e60f8854d50c1d1bbddca528fbf37d261;p=yosys.git

int -> bool
---

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index a5f170085..6170ea55e 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -735,7 +735,7 @@ struct RTLIL::SigChunk
 
 	RTLIL::SigChunk extract(int offset, int length) const;
 	inline int size() const { return width; }
-	inline int is_wire() const { return wire != NULL; }
+	inline bool is_wire() const { return wire != NULL; }
 
 	bool operator <(const RTLIL::SigChunk &other) const;
 	bool operator ==(const RTLIL::SigChunk &other) const;
@@ -761,7 +761,7 @@ struct RTLIL::SigBit
 	SigBit(const RTLIL::SigBit &sigbit) = default;
 	RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;
 
-	inline int is_wire() const { return wire != NULL; }
+	inline bool is_wire() const { return wire != NULL; }
 
 	bool operator <(const RTLIL::SigBit &other) const;
 	bool operator ==(const RTLIL::SigBit &other) const;