From: whitequark <cz@m-labs.hk>
Date: Mon, 3 Jun 2019 02:22:55 +0000 (+0000)
Subject: hdl.dsl: allow adding submodules with computed name, like with domains.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4b332fada5401c0cf1cd32385ed2ea0217735527;p=nmigen.git

hdl.dsl: allow adding submodules with computed name, like with domains.
---

diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py
index 03e7e23..30629c4 100644
--- a/nmigen/hdl/dsl.py
+++ b/nmigen/hdl/dsl.py
@@ -83,6 +83,9 @@ class _ModuleBuilderSubmodules:
     def __setattr__(self, name, submodule):
         self._builder._add_submodule(submodule, name)
 
+    def __setitem__(self, name, value):
+        return self.__setattr__(name, value)
+
 
 class _ModuleBuilderDomainSet:
     def __init__(self, builder):
diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py
index 2677582..0e703e0 100644
--- a/nmigen/test/test_hdl_dsl.py
+++ b/nmigen/test/test_hdl_dsl.py
@@ -505,6 +505,12 @@ class DSLTestCase(FHDLTestCase):
         m1.submodules.foo = m2
         self.assertEqual(m1._submodules, [(m2, "foo")])
 
+    def test_submodule_named_index(self):
+        m1 = Module()
+        m2 = Module()
+        m1.submodules["foo"] = m2
+        self.assertEqual(m1._submodules, [(m2, "foo")])
+
     def test_submodule_wrong(self):
         m = Module()
         with self.assertRaises(TypeError,