From: Luke Kenneth Casson Leighton Date: Tue, 30 Oct 2018 04:10:31 +0000 (+0000) Subject: add VL arg to macro X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4b3ab2d3f753868f1d4f05bc245b690ade4abf6d;p=riscv-tests.git add VL arg to macro --- diff --git a/isa/rv64ui/sv_addw_elwidth.S b/isa/rv64ui/sv_addw_elwidth.S index d5241a8..32ec811 100644 --- a/isa/rv64ui/sv_addw_elwidth.S +++ b/isa/rv64ui/sv_addw_elwidth.S @@ -8,7 +8,7 @@ RVTEST_RV64U # Define TVM used by program. // TODO: move SV_ELWIDTH_TEST to sv_test_macros.h // TODO: probably remove testing of x15 and x16 (or pass in as extra args?) -#define SV_ELWIDTH_TEST( wid1, wid2, wid3, isvec1, isvec2, isvec3, \ +#define SV_ELWIDTH_TEST( vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ expect1, expect2, expect3 ) \ \ SV_LDD_DATA( x12, testdata , 0); \ @@ -22,11 +22,11 @@ RVTEST_RV64U # Define TVM used by program. li x29, 0xa5a5a5a5a5a5a5a5; \ li x30, 0xa5a5a5a5a5a5a5a5; \ \ - SET_SV_MVL( 3); \ + SET_SV_MVL( vl ); \ SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1), \ SV_REG_CSR( 1, 12, wid2, 12, isvec2), \ SV_REG_CSR( 1, 28, wid3, 28, isvec3)); \ - SET_SV_VL( 3); \ + SET_SV_VL( vl ); \ \ addw x28, x15, x12; \ \ @@ -50,17 +50,17 @@ RVTEST_RV64U # Define TVM used by program. RVTEST_CODE_BEGIN # Start of test code. # TODO: add "addw" argument, add testdata argument - SV_ELWIDTH_TEST( 0, 0, 0, 1, 1, 1, + SV_ELWIDTH_TEST( 3, 0, 0, 0, 1, 1, 1, 0xffffffff8b6bab8b, 0xffffffff88684828, 0x0000000000000000 ) - SV_ELWIDTH_TEST( 0, 0, 3, 1, 1, 1, + SV_ELWIDTH_TEST( 3, 0, 0, 3, 1, 1, 1, 0x886848288b6bab8b, 0xa5a5a5a500000000, 0xa5a5a5a5a5a5a5a5 ) - SV_ELWIDTH_TEST( 1, 1, 0, 1, 1, 1, + SV_ELWIDTH_TEST( 3, 1, 1, 0, 1, 1, 1, 0xffffffffffffff8b, 0xffffffffffffffab, 0x000000000000006b ) - SV_ELWIDTH_TEST( 1, 1, 3, 1, 1, 1, + SV_ELWIDTH_TEST( 3, 1, 1, 3, 1, 1, 1, 0xffffffabffffff8b, 0xa5a5a5a50000006b, 0xa5a5a5a5a5a5a5a5 ) - SV_ELWIDTH_TEST( 1, 1, 2, 1, 1, 1, + SV_ELWIDTH_TEST( 3, 1, 1, 2, 1, 1, 1, 0xa5a5006bffabff8b, 0xa5a5a5a5a5a5a5a5, 0xa5a5a5a5a5a5a5a5 ) - SV_ELWIDTH_TEST( 1, 1, 1, 1, 1, 1, + SV_ELWIDTH_TEST( 3, 1, 1, 1, 1, 1, 1, 0xa5a5a5a5a56bab8b, 0xa5a5a5a5a5a5a5a5, 0xa5a5a5a5a5a5a5a5 ) RVTEST_PASS # Signal success.