From: lkcl <lkcl@web>
Date: Sat, 21 May 2022 14:59:12 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2145
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4b48fa72b32992e9f29928cb75777e9c166dcf97;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index b122c428a..5a054070f 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -71,8 +71,10 @@ equivalent to `maddld` because `maddld` performs sign-extension on RC.
 *Programmer's Note:
 As a Scalar Power ISA operation, like `lq` and `stq`, RS=RT+1.
 To achieve the same big-integer rolling-accumulation effect
-as SVP64, instructions may be issued `madded r20,r4,r8,r20
-madded r21,r5,r9,r21` etc. where the first `madded` will have
+as SVP64: assuming the scalar to multiply is in r0, 
+the vector to multiply by starts at r4 and the result vector
+in r20, instructions may be issued `madded r20,r4,r0,r20
+madded r21,r5,r0,r21` etc. where the first `madded` will have
 stored the upper half of the 128-bit multiply into r21, such
 that it may be picked up by the second `madded`. Repeat inline
 to construct a larger bigint scalar-vector multiply,