From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 3 Jun 2018 00:41:08 +0000 (+0100)
Subject: update
X-Git-Tag: convert-csv-opcode-to-binary~5318
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4b7b9d268954524dc13f0642970a404b5cc4236e;p=libreriscv.git

update
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 3f8749516..9d28b1ebc 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -110,13 +110,13 @@
 }
 
 
-\frame{\frametitle{How does Simple-V relate to RVV?}
+\frame{\frametitle{How does Simple-V relate to RVV? What's different?}
 
  \begin{itemize}
    \item RVV very heavy-duty (excellent for supercomputing)\vspace{10pt}
    \item Simple-V abstracts parallelism (based on best of RVV)\vspace{10pt}
    \item Graded levels: hardware, hybrid or traps (fit impl. need)\vspace{10pt}
-   \item Even Compressed instructions become vectorised\vspace{10pt}
+   \item Even Compressed become vectorised (RVV can't)\vspace{10pt}
   \end{itemize}
   What Simple-V is not:\vspace{10pt}
    \begin{itemize}