From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 22 Sep 2015 06:13:09 +0000 (+0200)
Subject: Fixed segfault on invalid verilog constant 1'b_
X-Git-Tag: yosys-0.6~146
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4b8200eb4943dcbdb2bede8695ca77cd7d6fde3a;p=yosys.git

Fixed segfault on invalid verilog constant 1'b_
---

diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index 9cc99750f..4a58357bf 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -122,7 +122,7 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
 	}
 
 	int len = GetSize(data);
-	RTLIL::State msb = data.back();
+	RTLIL::State msb = data.empty() ? RTLIL::S0 : data.back();
 
 	if (len_in_bits < 0) {
 		if (len < 32)