From: Samuel Pitoiset Date: Tue, 20 Nov 2018 15:41:23 +0000 (+0100) Subject: radv: only sync CP DMA for transfer operations or bottom pipe X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4b9bc4791b5778438f4829acd5a61d8b3574a257;p=mesa.git radv: only sync CP DMA for transfer operations or bottom pipe CP DMA can only be busy when the driver copies buffers. The only affected Vulkan commands are vkCmdCopyBuffer() and vkCmdUpdateBuffer() (because we fallback to a copy depending on a threshold). Clear operations are currently not concerned because the driver always syncs after the last DMA operation. Per the spec, these two operations have to be externally synchronized with VK_PIPELINE_STAGE_TRANSFER_BIT. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 9fcef5a62d3..f13768b4ada 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4496,7 +4496,9 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, /* Make sure CP DMA is idle because the driver might have performed a * DMA operation for copying or filling buffers/images. */ - si_cp_dma_wait_for_idle(cmd_buffer); + if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT | + VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)) + si_cp_dma_wait_for_idle(cmd_buffer); cmd_buffer->state.flush_bits |= dst_flush_bits; } @@ -4553,7 +4555,9 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer, /* Make sure CP DMA is idle because the driver might have performed a * DMA operation for copying or filling buffers/images. */ - si_cp_dma_wait_for_idle(cmd_buffer); + if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT | + VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)) + si_cp_dma_wait_for_idle(cmd_buffer); /* TODO: Emit EOS events for syncing PS/CS stages. */