From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 8 May 2023 12:07:24 +0000 (+0100)
Subject: whitespace
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4b9e87c66eae179c9ca2f758c9869537a1946305;p=libreriscv.git

whitespace
---

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index 957ead47f..14fb2d4b8 100644
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -192,13 +192,13 @@ maddedu r22,r6,r0,r3
 Pseudocode:
 
 ```
-if (RB)[0] != 0 then                 # workaround no unsigned-signed mul op
-    prod[0:127] <- -((RA) * -(RB))
-else
-    prod[0:127] <- (RA) * (RB)
-sum[0:127] <- prod + EXTS128((RC))
-RT <- sum[64:127]                    # Store low half in RT
-RS <- sum[0:63]                      # RS implicit register, equal to RC
+    if (RB)[0] != 0 then               # workaround no unsigned-signed mul op
+        prod[0:127] <- -((RA) * -(RB))
+    else
+        prod[0:127] <- (RA) * (RB)
+    sum[0:127] <- prod + EXTS128((RC))
+    RT <- sum[64:127]                  # Store low half in RT
+    RS <- sum[0:63]                    # RS implicit register, equal to RC
 ```
 
 Special registers altered:
@@ -256,16 +256,16 @@ maddedus r22,r6,r0,r3
 Pseudo-code:
 
 ```
-if ((RA) <u (RB)) & ((RB) != [0]*64) then  # Check RA<RB, for divide-by-0
-    dividend[0:127] <- (RA) || (RC)        # Combine RA/RC as 128-bit
-    divisor[0:127] <- [0]*64 || (RB)       # Extend RB to 128-bit
-    result <- dividend / divisor           # Unsigned Division
-    modulo <- dividend % divisor           # Unsigned Modulo
-    RT <- result[64:127]                   # Store result in RT
-    RS <- modulo[64:127]                   # Modulo in RC, implicit
-else                                       # In case of error
-    RT <- [1]*64                           # RT all 1's
-    RS <- [0]*64                           # RS all 0's
+    if ((RA) <u (RB)) & ((RB) != [0]*64) then  # Check RA<RB, for divide-by-0
+        dividend[0:127] <- (RA) || (RC)        # Combine RA/RC as 128-bit
+        divisor[0:127] <- [0]*64 || (RB)       # Extend RB to 128-bit
+        result <- dividend / divisor           # Unsigned Division
+        modulo <- dividend % divisor           # Unsigned Modulo
+        RT <- result[64:127]                   # Store result in RT
+        RS <- modulo[64:127]                   # Modulo in RC, implicit
+    else                                       # In case of error
+        RT <- [1]*64                           # RT all 1's
+        RS <- [0]*64                           # RS all 0's
 ```
 
 Special registers altered:
@@ -314,9 +314,9 @@ For Scalar usage, just as for `maddedu`, `RS=RC`
 Examples:
 
 ```
-# ((r0 << 64) + r2) / r1, store in r4
-# ((r0 << 64) + r2) % r1, store in r2
-divmod2du r4, r0, r1, r2
+    # ((r0 << 64) + r2) / r1, store in r4
+    # ((r0 << 64) + r2) % r1, store in r2
+    divmod2du r4, r0, r1, r2
 ```
 
 ----------
@@ -333,6 +333,7 @@ divmod2du r4, r0, r1, r2
 
 Pseudo-code:
 
+```
     n <- (RB)[58:63]                        # Use lower 6-bits for shift
     v <- ROTL64((RA), n)                    # Rotate RA 64-bit left by n bits
     mask <- MASK(64, 63-n)                  # 1s mask in MSBs
@@ -341,10 +342,7 @@ Pseudo-code:
     overflow = 0                            # Clear overflow flag
     if RS != [0]*64:                        # Check if RS is NOT zero
         overflow = 1                        # Set the overflow flag
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
+```
 
 The contents of register RA are shifted left the number
 of bits specified by (RB) 58:63. The same number of
@@ -364,6 +362,12 @@ effectively using RC as a 64-bit carry-in and carry-out. Arbitrary
 length Scalar-Vector shift may be performed without the additional
 masking instructions normally needed.*
 
+Special Registers Altered:
+
+```
+    CR0                    (if Rc=1)
+```
+
 ----------
 
 # Double-Shift Right Doubleword
@@ -376,6 +380,7 @@ masking instructions normally needed.*
 
 Pseudo-code:
 
+```
     n <- (RB)[58:63]                        # Take lower 6-bits for shift
     v <- ROTL64((RA), 64-n)                 # Rotate RA 64-bit left by 64-n bits
     mask <- MASK(n, 63)                     # 0's mask, set mask[n:63] to 1'
@@ -384,10 +389,7 @@ Pseudo-code:
     overflow = 0
     if RS != [0]*64:
         overflow = 1
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
+```
 
 The contents of register RA are shifted right the number
 of bits specified by (RB) 58:63. The same number of
@@ -407,6 +409,12 @@ effectively using RC as a 64-bit carry-in and carry-out. Arbitrary
 length Scalar-Vector shift may be performed without the additional
 masking instructions normally needed.*
 
+Special Registers Altered:
+
+```
+    CR0                    (if Rc=1)
+```
+
 ----------
 
 \newpage{}
@@ -416,43 +424,44 @@ masking instructions normally needed.*
 Add the following to Book I, 1.6.21.1, VA2-Form
 
 ```
-|0      |6     |11     |16     |21  |24|26  |31  |
-| PO    |  RT  |   RA  |   RB  | RC    | XO | Rc |
+    |0      |6     |11     |16     |21  |24|26  |31  |
+    | PO    |  RT  |   RA  |   RB  | RC    | XO | Rc |
 ```
 
-Add 'VA2-Form' to `RA` thru `XO` Field in Book I, 1.6.2
+Add 'VA2-Form' to `RA`, `RB`, `RC`, `Rc(31)` `RT` and
+`XO (26;30)` Fields in Book I, 1.6.2
 
 ```
-RA (11:15)
-    Field used to specify a GPR to be used as a
-    source or as a target.
-    Formats: ... VA2, ...
-
-RB (16:20)
-    Field used to specify a GPR to be used as a
-    source.
-    Formats: ... VA2, ...
-
-RC (21:25)
-    Field used to specify a GPR to be used as a
-    source.
-    Formats: ... VA2, ...
-
-Rc (31)
-    RECORD bit.
-    0    Do not alter the Condition Register.
-    1    Set Condition Register Field 0 or Field 1 as
-         described in Section 2.3.1, 'Condition Regis-
-         ter' on page 30.
-    Formats: ... VA2, ...
-
-RT (6:10)
-    Field used to specify a GPR to be used as a target.
-    Formats: ... VA2, ...
-
-XO (26:30)
-    Extended opcode field.
-    Formats: ... VA2, ...
+    RA (11:15)
+        Field used to specify a GPR to be used as a
+        source or as a target.
+        Formats: ... VA2, ...
+
+    RB (16:20)
+        Field used to specify a GPR to be used as a
+        source.
+        Formats: ... VA2, ...
+
+    RC (21:25)
+        Field used to specify a GPR to be used as a
+        source.
+        Formats: ... VA2, ...
+
+    Rc (31)
+        RECORD bit.
+        0    Do not alter the Condition Register.
+        1    Set Condition Register Field 0 or Field 1 as
+             described in Section 2.3.1, 'Condition Regis-
+             ter' on page 30.
+        Formats: ... VA2, ...
+
+    RT (6:10)
+        Field used to specify a GPR to be used as a target.
+        Formats: ... VA2, ...
+
+    XO (26:30)
+        Extended opcode field.
+        Formats: ... VA2, ...
 ```
 
 ----------
@@ -464,13 +473,13 @@ XO (26:30)
     Appendix G Power ISA sorted by Compliancy Subset
     Appendix H Power ISA sorted by mnemonic
 
-|Form| Book | Page | Version | mnemonic | Description |
-|----|------|------|---------|----------|-------------|
-|VA  | I    | #    | 3.2B    |maddedu   | Multiply-Add Extend Double Unsigned |
-|VA  | I    | #    | 3.2B    |maddedus  | Multiply-Add Extend Double Unsigned Signed |
-|VA  | I    | #    | 3.2B    |divmod2du | Divide/Modulo Quad-Double Unsigned |
-|VA2 | I    | #    | 3.2B    |dsld      | Double-Shift Left Doubleword |
-|VA2 | I    | #    | 3.2B    |dsrd      | Double-Shift Right Doubleword |
+|Form|Book|Page|Version| mnemonic |Description                              |
+|----|----|----|-------|----------|-----------------------------------------|
+|VA  | I  |#   | 3.2B  |maddedu   |Multiply-Add Extend Double Unsigned |
+|VA  | I  |#   | 3.2B  |maddedus  |Multiply-Add Extend Double Unsigned Signed |
+|VA  | I  |#   | 3.2B  |divmod2du |Divide/Modulo Quad-Double Unsigned |
+|VA2 | I  |#   | 3.2B  |dsld      |Double-Shift Left Doubleword |
+|VA2 | I  |#   | 3.2B  |dsrd      |Double-Shift Right Doubleword |
 
 ----------------