From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun, 4 Aug 2019 23:39:23 +0000 (+0200)
Subject: radv/gfx10: Enable DCC for storage images.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4bb17c08ae5d734894de0fcefe6a9645b443bf34;p=mesa.git

radv/gfx10: Enable DCC for storage images.

v2: Hide it behind a perftest flag.

Reviewed-by: Dave Airlie <airlied@redhat.com>
---

diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index ef5b331d188..a4878b06bdc 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -67,6 +67,7 @@ enum {
 	RADV_PERFTEST_CS_WAVE_32     = 0x100,
 	RADV_PERFTEST_PS_WAVE_32     = 0x200,
 	RADV_PERFTEST_GE_WAVE_32     = 0x400,
+	RADV_PERFTEST_STORAGE_DCC    = 0x800,
 };
 
 bool
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 5ef8942411c..4a2d836abe3 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -514,6 +514,7 @@ static const struct debug_control radv_perftest_options[] = {
 	{"cswave32", RADV_PERFTEST_CS_WAVE_32},
 	{"pswave32", RADV_PERFTEST_PS_WAVE_32},
 	{"gewave32", RADV_PERFTEST_GE_WAVE_32},
+	{"storagedcc", RADV_PERFTEST_STORAGE_DCC},
 	{NULL, 0}
 };
 
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 64b2a73bf45..b3a83ff306d 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -142,6 +142,13 @@ radv_surface_has_scanout(struct radv_device *device, const struct radv_image_cre
 	}
 }
 
+static bool
+radv_support_storage_dcc(const struct radv_physical_device *pdevice)
+{
+	return pdevice->rad_info.chip_class >= GFX10 &&
+	       (pdevice->instance->perftest_flags & RADV_PERFTEST_STORAGE_DCC);
+}
+
 static bool
 radv_use_dcc_for_image(struct radv_device *device,
 		       const struct radv_image *image,
@@ -161,8 +168,8 @@ radv_use_dcc_for_image(struct radv_device *device,
 	if (image->shareable)
 		return false;
 
-	/* TODO: Enable DCC for storage images. */
-	if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
+	if (((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT)  &&
+	     !radv_support_storage_dcc(device->physical_device))||
 	    (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
 		return false;
 
@@ -1444,13 +1451,17 @@ radv_image_view_make_descriptor(struct radv_image_view *iview,
 		else
 			base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
 	}
+
+	if (is_storage_image && radv_image_has_dcc(iview->image) &&
+	    !radv_support_storage_dcc(device->physical_device))
+		disable_compression = true;
 	si_set_mutable_tex_desc_fields(device, image,
 				       base_level_info,
 				       plane_id,
 				       iview->base_mip,
 				       iview->base_mip,
 				       blk_w, is_stencil, is_storage_image,
-				       is_storage_image || disable_compression,
+				       disable_compression,
 				       descriptor->plane_descriptors[descriptor_plane_id]);
 }
 
@@ -1650,7 +1661,8 @@ bool radv_layout_dcc_compressed(const struct radv_device *device,
 {
 	/* Don't compress compute transfer dst, as image stores are not supported. */
 	if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
-	    (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
+	    (queue_mask & (1u << RADV_QUEUE_COMPUTE)) &&
+	    !radv_support_storage_dcc(device->physical_device))
 		return false;
 
 	return radv_image_has_dcc(image) &&!in_render_loop;