From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sat, 1 Dec 2012 12:04:22 +0000 (+0100)
Subject: bus/wishbone/sram: accept memories < 32 bits
X-Git-Tag: 24jan2021_ls180~2099^2~727
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4bcb39699b3b454823a9677b043f977a1bed03ee;p=litex.git

bus/wishbone/sram: accept memories < 32 bits
---

diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
index d0c0c5b5..b1d23233 100644
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@@ -197,7 +197,7 @@ class Target(PureSimulable):
 class SRAM:
 	def __init__(self, mem_or_size, bus=Interface()):
 		if isinstance(mem_or_size, Memory):
-			assert(mem_or_size.width == 32)
+			assert(mem_or_size.width <= 32)
 			self.mem = mem_or_size
 		else:
 			self.mem = Memory(32, mem_or_size//4)