From: Matt Johnston Date: Thu, 27 Oct 2022 03:23:30 +0000 (+0800) Subject: Move alt_reset to syscon X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4bd45af739214d8659a4940485500ae508399ecd;p=microwatt.git Move alt_reset to syscon Instead of connecting core_alt_reset to litedram init_done, it moves to a syscon register bit. This simplifies top- files and future soc_reset handling. sdram main.c can unset the alt_reset bit after sdram init. Signed-off-by: Matt Johnston --- diff --git a/core_dram_tb.vhdl b/core_dram_tb.vhdl index a0251e3..4a3a0c3 100644 --- a/core_dram_tb.vhdl +++ b/core_dram_tb.vhdl @@ -32,7 +32,6 @@ architecture behave of core_dram_tb is signal wb_ext_io_out : wb_io_slave_out; signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_init : std_ulogic; - signal core_alt_reset : std_ulogic; -- SPI signal spi_sck : std_ulogic; @@ -84,8 +83,7 @@ begin spi_flash_cs_n => spi_cs_n, spi_flash_sdat_o => spi_sdat_o, spi_flash_sdat_oe => spi_sdat_oe, - spi_flash_sdat_i => spi_sdat_i, - alt_reset => core_alt_reset + spi_flash_sdat_i => spi_sdat_i ); flash: entity work.s25fl128s @@ -135,7 +133,6 @@ begin rst => rst, system_clk => system_clk, system_reset => soc_rst, - core_alt_reset => core_alt_reset, wb_in => wb_dram_in, wb_out => wb_dram_out, diff --git a/dram_tb.vhdl b/dram_tb.vhdl index ce22f30..c8e7b2c 100644 --- a/dram_tb.vhdl +++ b/dram_tb.vhdl @@ -58,7 +58,6 @@ begin rst => rst, system_clk => clk, system_reset => soc_rst, - core_alt_reset => open, pll_locked => open, wb_in => wb_in, diff --git a/fpga/top-acorn-cle-215.vhdl b/fpga/top-acorn-cle-215.vhdl index fd5fd5c..7f03506 100644 --- a/fpga/top-acorn-cle-215.vhdl +++ b/fpga/top-acorn-cle-215.vhdl @@ -84,9 +84,6 @@ architecture behaviour of toplevel is signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_init : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- SPI flash signal spi_sck : std_ulogic; signal spi_cs_n : std_ulogic; @@ -162,8 +159,7 @@ begin wb_ext_io_in => wb_ext_io_in, wb_ext_io_out => wb_ext_io_out, wb_ext_is_dram_csr => wb_ext_is_dram_csr, - wb_ext_is_dram_init => wb_ext_is_dram_init, - alt_reset => core_alt_reset + wb_ext_is_dram_init => wb_ext_is_dram_init ); -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2 @@ -231,7 +227,6 @@ begin led1 <= pll_rst; led2 <= not system_clk_locked; led3 <= '0'; - core_alt_reset <= '0'; -- Vivado barfs on those differential signals if left -- unconnected. So instanciate a diff. buffer and feed @@ -289,7 +284,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => soc_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/fpga/top-antmicro-artix-dc-scm.vhdl b/fpga/top-antmicro-artix-dc-scm.vhdl index b8fd75f..bd0dcd5 100644 --- a/fpga/top-antmicro-artix-dc-scm.vhdl +++ b/fpga/top-antmicro-artix-dc-scm.vhdl @@ -121,9 +121,6 @@ architecture behaviour of toplevel is -- for conversion from non-pipelined wishbone to pipelined signal wb_sddma_stb_sent : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- Status LED signal led0_b_pwm : std_ulogic; signal led0_r_pwm : std_ulogic; @@ -240,9 +237,7 @@ begin -- DMA wishbone wishbone_dma_in => wb_sddma_in, - wishbone_dma_out => wb_sddma_out, - - alt_reset => core_alt_reset + wishbone_dma_out => wb_sddma_out ); @@ -303,8 +298,6 @@ begin pll_locked_out => system_clk_locked ); - core_alt_reset <= '0'; - d11_led <= '0'; d12_led <= soc_rst; d13_led <= system_clk; @@ -376,7 +369,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => dram_sys_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index ecdd5d4..b6b8913 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -139,9 +139,6 @@ architecture behaviour of toplevel is -- for conversion from non-pipelined wishbone to pipelined signal wb_sddma_stb_sent : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- Status LED signal led0_b_pwm : std_ulogic; signal led0_r_pwm : std_ulogic; @@ -258,9 +255,7 @@ begin -- DMA wishbone wishbone_dma_in => wb_sddma_in, - wishbone_dma_out => wb_sddma_out, - - alt_reset => core_alt_reset + wishbone_dma_out => wb_sddma_out ); --uart_pmod_rts_n <= '0'; @@ -333,7 +328,6 @@ begin led0_b_pwm <= '1'; led0_r_pwm <= '1'; led0_g_pwm <= '0'; - core_alt_reset <= '0'; -- Vivado barfs on those differential signals if left -- unconnected. So instanciate a diff. buffer and feed @@ -402,7 +396,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => dram_sys_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/fpga/top-genesys2.vhdl b/fpga/top-genesys2.vhdl index ecdaa66..d876362 100644 --- a/fpga/top-genesys2.vhdl +++ b/fpga/top-genesys2.vhdl @@ -87,9 +87,6 @@ architecture behaviour of toplevel is signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_init : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- SPI flash signal spi_sck : std_ulogic; signal spi_cs_n : std_ulogic; @@ -165,8 +162,7 @@ begin wb_ext_io_in => wb_ext_io_in, wb_ext_io_out => wb_ext_io_out, wb_ext_is_dram_csr => wb_ext_is_dram_csr, - wb_ext_is_dram_init => wb_ext_is_dram_init, - alt_reset => core_alt_reset + wb_ext_is_dram_init => wb_ext_is_dram_init ); -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2 @@ -234,7 +230,6 @@ begin led1 <= pll_rst; led2 <= not system_clk_locked; led3 <= '0'; - core_alt_reset <= '0'; -- Vivado barfs on those differential signals if left -- unconnected. So instanciate a diff. buffer and feed @@ -292,7 +287,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => soc_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index beb4045..f18f80e 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -128,9 +128,6 @@ architecture behaviour of toplevel is -- for conversion from non-pipelined wishbone to pipelined signal wb_sddma_stb_sent : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- SPI flash signal spi_sck : std_ulogic; signal spi_cs_n : std_ulogic; @@ -220,9 +217,7 @@ begin -- DMA wishbone wishbone_dma_in => wb_sddma_in, - wishbone_dma_out => wb_sddma_out, - - alt_reset => core_alt_reset + wishbone_dma_out => wb_sddma_out ); -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2 @@ -282,7 +277,6 @@ begin led0 <= '1'; led1 <= not soc_rst; led2 <= '0'; - core_alt_reset <= '0'; -- Vivado barfs on those differential signals if left -- unconnected. So instanciate a diff. buffer and feed @@ -350,7 +344,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => dram_sys_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/fpga/top-orangecrab0.2.vhdl b/fpga/top-orangecrab0.2.vhdl index ada940c..f773323 100644 --- a/fpga/top-orangecrab0.2.vhdl +++ b/fpga/top-orangecrab0.2.vhdl @@ -110,9 +110,6 @@ architecture behaviour of toplevel is -- for conversion from non-pipelined wishbone to pipelined signal wb_sddma_stb_sent : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- Status LED signal led0_b_pwm : std_ulogic; signal led0_r_pwm : std_ulogic; @@ -231,9 +228,7 @@ begin -- DMA wishbone wishbone_dma_in => wb_sddma_in, - wishbone_dma_out => wb_sddma_out, - - alt_reset => core_alt_reset + wishbone_dma_out => wb_sddma_out ); -- SPI Flash @@ -284,7 +279,6 @@ begin led0_b_pwm <= '1'; led0_r_pwm <= '1'; led0_g_pwm <= '0'; - core_alt_reset <= '0'; end generate; @@ -341,7 +335,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => dram_sys_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/fpga/top-wukong-v2.vhdl b/fpga/top-wukong-v2.vhdl index d3f7bd8..2b6d4e1 100644 --- a/fpga/top-wukong-v2.vhdl +++ b/fpga/top-wukong-v2.vhdl @@ -128,9 +128,6 @@ architecture behaviour of toplevel is -- for conversion from non-pipelined wishbone to pipelined signal wb_sddma_stb_sent : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- SPI flash signal spi_sck : std_ulogic; signal spi_cs_n : std_ulogic; @@ -225,9 +222,7 @@ begin -- DMA wishbone wishbone_dma_in => wb_sddma_in, - wishbone_dma_out => wb_sddma_out, - - alt_reset => core_alt_reset + wishbone_dma_out => wb_sddma_out ); -- SPI Flash @@ -282,8 +277,6 @@ begin pll_locked_out => system_clk_locked ); - core_alt_reset <= '0'; - -- Vivado barfs on those differential signals if left -- unconnected. So instanciate a diff. buffer and feed -- it a constant '0'. @@ -351,7 +344,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => dram_sys_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/include/microwatt_soc.h b/include/microwatt_soc.h index ab55287..3e6830b 100644 --- a/include/microwatt_soc.h +++ b/include/microwatt_soc.h @@ -52,6 +52,7 @@ #define SYS_REG_CTRL_DRAM_AT_0 (1ull << 0) #define SYS_REG_CTRL_CORE_RESET (1ull << 1) #define SYS_REG_CTRL_SOC_RESET (1ull << 2) +#define SYS_REG_CTRL_ALT_RESET (1ull << 3) #define SYS_REG_DRAMINITINFO 0x30 #define SYS_REG_SPI_INFO 0x38 #define SYS_REG_SPI_INFO_FLASH_OFF_MASK 0xffffffff diff --git a/litedram/extras/litedram-wrapper-l2.vhdl b/litedram/extras/litedram-wrapper-l2.vhdl index 652e727..8069b8e 100644 --- a/litedram/extras/litedram-wrapper-l2.vhdl +++ b/litedram/extras/litedram-wrapper-l2.vhdl @@ -44,7 +44,6 @@ entity litedram_wrapper is rst : in std_ulogic; system_clk : out std_ulogic; system_reset : out std_ulogic; - core_alt_reset : out std_ulogic; pll_locked : out std_ulogic; -- Wishbone ports: @@ -420,9 +419,6 @@ begin assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS) report "geometry bits don't add up" severity FAILURE; - -- alternate core reset address set when DRAM is not initialized. - core_alt_reset <= not init_done; - -- Init code BRAM memory slave init_ram_0: entity work.dram_init_mem generic map( diff --git a/soc.vhdl b/soc.vhdl index 7daca5f..3282ca9 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -127,10 +127,7 @@ entity soc is -- GPIO signals gpio_out : out std_ulogic_vector(NGPIO - 1 downto 0); gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0); - gpio_in : in std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0'); - - -- DRAM controller signals - alt_reset : in std_ulogic := '0' + gpio_in : in std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0') ); end entity soc; @@ -166,6 +163,7 @@ architecture behaviour of soc is -- Syscon signals signal dram_at_0 : std_ulogic; signal do_core_reset : std_ulogic; + signal alt_reset : std_ulogic; signal wb_syscon_in : wb_io_master_out; signal wb_syscon_out : wb_io_slave_out; @@ -768,7 +766,8 @@ begin wishbone_out => wb_syscon_out, dram_at_0 => dram_at_0, core_reset => do_core_reset, - soc_reset => open -- XXX TODO + soc_reset => open, -- XXX TODO + alt_reset => alt_reset ); -- diff --git a/syscon.vhdl b/syscon.vhdl index 727f4e7..99fa835 100644 --- a/syscon.vhdl +++ b/syscon.vhdl @@ -34,7 +34,8 @@ entity syscon is -- System control ports dram_at_0 : out std_ulogic; core_reset : out std_ulogic; - soc_reset : out std_ulogic + soc_reset : out std_ulogic; + alt_reset : out std_ulogic ); end entity syscon; @@ -76,10 +77,11 @@ architecture behaviour of syscon is -- CLKINFO contains the CLK frequency is HZ in the bottom 40 bits -- CTRL register bits - constant SYS_REG_CTRL_BITS : positive := 3; + constant SYS_REG_CTRL_BITS : positive := 4; constant SYS_REG_CTRL_DRAM_AT_0 : integer := 0; constant SYS_REG_CTRL_CORE_RESET : integer := 1; constant SYS_REG_CTRL_SOC_RESET : integer := 2; + constant SYS_REG_CTRL_ALT_RESET : integer := 3; -- SPI Info register bits -- @@ -102,6 +104,7 @@ architecture behaviour of syscon is -- Ctrl register signal reg_ctrl : std_ulogic_vector(SYS_REG_CTRL_BITS-1 downto 0); signal reg_ctrl_out : std_ulogic_vector(63 downto 0); + signal ctrl_init_alt_reset : std_ulogic; -- Others signal reg_info : std_ulogic_vector(63 downto 0); @@ -128,11 +131,12 @@ architecture behaviour of syscon is -- Wishbone response latch signal wb_rsp : wb_io_slave_out; begin - -- Generated output signals dram_at_0 <= '1' when BRAM_SIZE = 0 else reg_ctrl(SYS_REG_CTRL_DRAM_AT_0); soc_reset <= reg_ctrl(SYS_REG_CTRL_SOC_RESET); core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET); + alt_reset <= reg_ctrl(SYS_REG_CTRL_ALT_RESET); + -- Info register is hard wired info_has_uart <= '1' when HAS_UART else '0'; @@ -211,12 +215,16 @@ begin end if; end process; + -- Initial state + ctrl_init_alt_reset <= '1' when HAS_DRAM else '0'; + -- Register writes regs_write: process(clk) begin if rising_edge(clk) then if (rst) then - reg_ctrl <= (others => '0'); + reg_ctrl <= (SYS_REG_CTRL_ALT_RESET => ctrl_init_alt_reset, + others => '0'); else if wishbone_in.cyc and wishbone_in.stb and wishbone_in.we then -- Change this if CTRL ever has more than 32 bits