From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Mar 2013 16:59:44 +0000 (+0100)
Subject: Changed fsm_expand to merge multiplexers more aggressively
X-Git-Tag: yosys-0.2.0~686
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4bd6f1ee8eb13f94fa7b6d3b87b8f19648ec4d6b;p=yosys.git

Changed fsm_expand to merge multiplexers more aggressively
---

diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index df3aec85a..0446c113d 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -42,6 +42,9 @@ struct FsmExpand
 
 	bool is_cell_merge_candidate(RTLIL::Cell *cell)
 	{
+		if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
+			return cell->connections.at("\\A").width < 2;
+
 		RTLIL::SigSpec new_signals;
 		if (cell->connections.count("\\A") > 0)
 			new_signals.append(assign_map(cell->connections["\\A"]));
@@ -137,7 +140,7 @@ struct FsmExpand
 		input_sig.sort_and_unify();
 		input_sig.remove_const();
 
-		assert(input_sig.width <= 4);
+		assert(input_sig.width <= 4 || cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux");
 		std::vector<RTLIL::Const> truth_tab;
 
 		for (int i = 0; i < (1 << input_sig.width); i++) {