From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 25 Aug 2016 09:44:25 +0000 (+0200)
Subject: Improved verilog parser errors
X-Git-Tag: yosys-0.7~104
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4be4969bae5d99af572ca99859dc4a550c24d4cf;p=yosys.git

Improved verilog parser errors
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 7b025db23..d0d6a5fe1 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -135,6 +135,9 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %left OP_POW
 %right UNARY_OPS
 
+%define parse.error verbose
+%define parse.lac full
+
 %expect 2
 %debug