From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 12:47:48 +0000 (+0200)
Subject: Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs
X-Git-Tag: yosys-0.4~391
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4be645860bf83de75cdd00fbe615f3fe05221d54;p=yosys.git

Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index db85f9e3d..9f9bd7e03 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1978,19 +1978,36 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
 
 void RTLIL::SigSpec::remove_const()
 {
-	cover("kernel.rtlil.sigspec.remove_const");
+	if (packed())
+	{
+		cover("kernel.rtlil.sigspec.remove_const.packed");
 
-	unpack();
+		std::vector<RTLIL::SigChunk> new_chunks;
+		new_chunks.reserve(SIZE(chunks_));
+
+		width_ = 0;
+		for (auto &chunk : chunks_)
+			if (chunk.wire != NULL) {
+				new_chunks.push_back(chunk);
+				width_ += chunk.width;
+			}
+
+		chunks_.swap(new_chunks);
+	}
+	else
+	{
+		cover("kernel.rtlil.sigspec.remove_const.unpacked");
 
-	std::vector<RTLIL::SigBit> new_bits;
-	new_bits.reserve(width_);
+		std::vector<RTLIL::SigBit> new_bits;
+		new_bits.reserve(width_);
 
-	for (auto &bit : bits_)
-		if (bit.wire != NULL)
-			new_bits.push_back(bit);
+		for (auto &bit : bits_)
+			if (bit.wire != NULL)
+				new_bits.push_back(bit);
 
-	bits_.swap(new_bits);
-	width_ = bits_.size();
+		bits_.swap(new_bits);
+		width_ = bits_.size();
+	}
 
 	check();
 }