From: lkcl <lkcl@web>
Date: Fri, 22 Jan 2021 21:11:09 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~381
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4beab55572942dd6d975e8892ad7e15d0e6e9c1a;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 7878b7523..1e6aba652 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -639,3 +639,8 @@ Fields:
 * spred={reg spec}
 
 similar to x86 "rex" prefix.
+
+For actual assembler:
+
+    sv.asmcode.mode.vec reg.v/8, src.s/16, pred={maskreg}, spred={maskreg}
+