From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Mar 2021 11:43:37 +0000 (+0000)
Subject: stw/std/std/stb must be SRC-RA and SRC-RS
X-Git-Tag: convert-csv-opcode-to-binary~42
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4c0740f67a565bccec720ae7685317baeb93d6fb;p=libreriscv.git

stw/std/std/stb must be SRC-RA and SRC-RS
---

diff --git a/openpower/isatables/LDSTRM-2P-2S.csv b/openpower/isatables/LDSTRM-2P-2S.csv
index dcb7c19bd..2a8edea4f 100644
--- a/openpower/isatables/LDSTRM-2P-2S.csv
+++ b/openpower/isatables/LDSTRM-2P-2S.csv
@@ -1,5 +1,5 @@
 insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out
-stw,2P,EXTRA3,d:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0
-stb,2P,EXTRA3,d:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0
-sth,2P,EXTRA3,d:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0
-std,2P,EXTRA3,d:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0
+stw,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0
+stb,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0
+sth,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0
+std,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0
diff --git a/openpower/sv_analysis.py b/openpower/sv_analysis.py
index f72fc6956..5e47025b9 100644
--- a/openpower/sv_analysis.py
+++ b/openpower/sv_analysis.py
@@ -388,8 +388,9 @@ def process_csvs():
                 res['2'] = 's:RA' # RA: Rsrc1_EXTRA2
 
             elif value == 'LDSTRM-2P-2S':
+                # stw, std, sth, stb
                 res['Etype'] = 'EXTRA3' # RM EXTRA2 type
-                res['0'] = 'd:RS' # RT: Rdest1_EXTRA2
+                res['0'] = 's:RS' # RT: Rdest1_EXTRA2
                 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2
 
             elif value == 'LDSTRM-2P-2S1D':