From: lkcl <lkcl@web>
Date: Sun, 7 May 2023 22:11:41 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4c1929308681f5f51e376c0b4625ebad2a8994ad;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index 32f39961a..957ead47f 100644
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -82,8 +82,7 @@ Instructions added
    but VA-Form EXT004 is under severe pressure.
 3. Both `maddhdu` and `divmod2du` instructions have been present in Intel x86
    for several decades.  Likewise, `dsld` and `dsrd`.
-4. None of these instruction is present in VSX: these are 128/64 whereas
-   VSX is 128/128.
+4. None of these instruction is present in VSX.
 5. `maddedu` and `divmod2du` are full inverses of each other, including
   when used for arbitrary-length big-integer arithmetic.
 6. These are all 3-in 2-out instructions. If Power ISA did not already
@@ -95,6 +94,8 @@ Instructions added
   and is unsuited for big-integer or other general arithmetic.
 8. Unresolved: dsld/dsrd are 3-in 3-out (in the Rc=1 variants) where the
    normal threshold set is 3-in 2-out.
+9. Hardware may macro-op fuse repeated inline uses, reducing register use through
+   operand-forwarding and/or using higher bit-width ALUs.
 
 **Changes**