From: Andrew Waterman <aswaterman@gmail.com>
Date: Tue, 13 Feb 2018 18:43:36 +0000 (-0800)
Subject: Implement cycleh/instreth CSRs for RV32 (#172)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4c1c92f59f7b021eb2fa3b373b60f0e8b7c08a17;p=riscv-isa-sim.git

Implement cycleh/instreth CSRs for RV32 (#172)
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 516a708..8cca490 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -565,6 +565,11 @@ reg_t processor_t::get_csr(int which)
     case CSR_MINSTRET:
     case CSR_MCYCLE:
       return state.minstret;
+    case CSR_INSTRETH:
+    case CSR_CYCLEH:
+      if (ctr_ok && xlen == 32)
+        return state.minstret >> 32;
+      break;
     case CSR_MINSTRETH:
     case CSR_MCYCLEH:
       if (xlen == 32)