From: Jan Hubicka Date: Fri, 27 Oct 2017 14:30:00 +0000 (+0200) Subject: x86-tune.def (X86_TUNE_PARTIAL_REG_DEPENDENCY, [...]): Disable for Haswell and newer... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4c249d97372f1d5f4da9f6f65e4b5be9dad8e3c7;p=gcc.git x86-tune.def (X86_TUNE_PARTIAL_REG_DEPENDENCY, [...]): Disable for Haswell and newer CPUs. * config/i386/x86-tune.def (X86_TUNE_PARTIAL_REG_DEPENDENCY, X86_TUNE_MOVX): Disable for Haswell and newer CPUs. From-SVN: r254152 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cdfc0025c63..bf87fafca14 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-10-27 Jan Hubicka + + * config/i386/x86-tune.def (X86_TUNE_PARTIAL_REG_DEPENDENCY, + X86_TUNE_MOVX): Disable for Haswell and newer CPUs. + 2017-10-27 Jakub Jelinek PR target/82703 diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 9d01761eff9..208d3c58ef4 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -48,7 +48,8 @@ DEF_TUNE (X86_TUNE_SCHEDULE, "schedule", over partial stores. For example preffer MOVZBL or MOVQ to load 8bit value over movb. */ DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency", - m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL + m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE + | m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_AMD_MULTIPLE | m_GENERIC) /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store @@ -84,8 +85,9 @@ DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall", /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid partial dependencies. */ DEF_TUNE (X86_TUNE_MOVX, "movx", - m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT - | m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GENERIC) + m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE + | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL + | m_GEODE | m_AMD_MULTIPLE | m_GENERIC) /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by full sized loads. */