From: lkcl <lkcl@web>
Date: Sat, 9 Jan 2021 23:14:31 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~501
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4c29fb7a63ec2025da2681d6c69eb43507301588;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 50d46be00..b6a8ecabb 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -104,7 +104,7 @@ Indexed LD is:
         if (RB.isvec) k++;
         if (RT.isvec) j++;
 
-Note in both cases that [[sv/svp64]] allows RA in "update" mode (`ldux`) to be effectively a completely different register from RA-as-a-source.  This because there is room in svp64 to extend RA-as-src as well as RA-as-dest, both independently as scalar or vector *and* independently extending their range.
+Note in both cases that [[sv/svp64]] allows RA-as-a-dest in "update" mode (`ldux`) to be effectively a *completely different* register from RA-as-a-source.  This because there is room in svp64 to extend RA-as-src as well as RA-as-dest, both independently as scalar or vector *and* independently extending their range.
 
 # Determining the LD/ST Modes