From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Apr 2020 11:23:27 +0000 (+0100)
Subject: add hypervisor system return
X-Git-Tag: convert-csv-opcode-to-binary~2946
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4c2a5de0d4baa50d8763bc08e800d37b2498b112;p=libreriscv.git

add hypervisor system return
---

diff --git a/openpower/isa/system.mdwn b/openpower/isa/system.mdwn
new file mode 100644
index 000000000..b1be77cc7
--- /dev/null
+++ b/openpower/isa/system.mdwn
@@ -0,0 +1,110 @@
+# System Call 
+
+SC-Form
+
+* sc LEV
+
+    SRR0 <-iea CIA + 4
+    SRR1[33:36] <- 0
+    SRR1[42:47] <- 0
+    SRR1[0:32]  <- MSR[0:32] 
+    SRR1[37:41] <- MSR[37:41]
+    SRR1[48:63] <- MSR[48:63]
+    MSR <- new_value 
+    NIA <- 0x0000_0000_0000_0C00
+
+Special Registers Altered:
+
+    SRR0 SRR1 MSR
+
+# System Call Vectored
+
+SC-Form
+
+* scv LEV
+
+    LR <- CIA + 4
+    SRR1[33:36] <- undefined
+    SRR1[42:47] <- undefined
+    SRR1[0:32]  <- MSR[0:32] 
+    SRR1[37:41] <- MSR[37:41]
+    SRR1[48:63] <- MSR[48:63]
+    MSR <- new_value 
+    NIA <- vectored
+
+Special Registers Altered:
+
+    LR CTR MSR
+
+# Return From System Call Vectored
+
+XL-Form
+
+* rfscv LEV
+
+    if (MSR[29:31] != 0b010) | (CTR[29:31] != 0b000) then
+        MSR[29:31] <- CTR[29:31]
+    MSR[48] <- CTR[49]
+    MSR[58] <- CTR[49]
+    MSR[59] <- CTR[49]
+    MSR[0:2] <- CTR[0:2]
+    MSR[4:28] <- CTR[4:28]
+    MSR[32] <- CTR[32]
+    MSR[37:41] <- CTR[37:41]
+    MSR[49:50] <- CTR[49:50]
+    MSR[52:57] <- CTR[52:57]
+    MSR[60:63] <- CTR[60:63]
+    NIA <-iea LR[0:61] || 0b00
+
+Special Registers Altered:
+
+    MSR
+
+# Return From Interrupt Doubleword
+
+XL-Form
+
+* rfid LEV
+
+    MSR[51] <- (MSR[3] & SRR1[51]) | ((¬MSR[3] & MSR[51]))
+    MSR[3] <- MSR[3] & SRR1[3])
+    if (MSR[29:31] != 0b010) | (SRR1[29:31] != 0b000) then
+        MSR[29:31] <- SRR1[29:31]
+    MSR[48] <- SRR1[48] | SRR1[49]
+    MSR[58] <- SRR1[88] | SRR1[49]
+    MSR[59] <- SRR1[59] | SRR1[49]
+    MSR[0:2] <- SRR1[0:2]
+    MSR[4:28] <- SRR1[4:28]
+    MSR[32] <- SRR1[32]
+    MSR[37:41] <- SRR1[37:41]
+    MSR[49:50] <- SRR1[49:50]
+    MSR[52:57] <- SRR1[52:57]
+    MSR[60:63] <- SRR1[60:63]
+    NIA <-iea SRR0[0:61] || 0b00
+
+Special Registers Altered:
+
+    MSR
+
+# Hypervisor Return From Interrupt Doubleword
+
+XL-Form
+
+* hrfid LEV
+
+    if (MSR[29:31] != 0b010) | (HSRR1[29:31] != 0b000) then
+        MSR[29:31] <- HSRR1[29:31]
+    MSR[48] <- HSRR1[48] | HSRR1[49]
+    MSR[58] <- HSRR1[88] | HSRR1[49]
+    MSR[59] <- HSRR1[59] | HSRR1[49]
+    MSR[0:28] <- HSRR1[0:28]
+    MSR[32] <- HSRR1[32]
+    MSR[37:41] <- HSRR1[37:41]
+    MSR[49:57] <- HSRR1[49:57]
+    MSR[60:63] <- HSRR1[60:63]
+    NIA <-iea HSRR0[0:61] || 0b00
+
+Special Registers Altered:
+
+    MSR
+