From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 4 Nov 2020 19:25:01 +0000 (+0000)
Subject: minor reformat of spec, whitespace
X-Git-Tag: partial-core-ls180-gdsii~30
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4c3fbb8343d1d22082e8d4722f31f08aafb02e38;p=soclayout.git

minor reformat of spec, whitespace
---

diff --git a/experiments10/doDesign.py b/experiments10/doDesign.py
index 62558f8..3dc4bc6 100644
--- a/experiments10/doDesign.py
+++ b/experiments10/doDesign.py
@@ -35,32 +35,34 @@ def scriptMain ( **kw ):
             print( ErrorMessage( 2, 'doDesign.scriptMain(): Unable to load cell "{}".'.format('adder') ))
             sys.exit( 1 )
         if editor: editor.setCell( cell ) 
-        #     Spec:  | Side        | Pos | Instance     | Pad net   |Core net | Direction |
-        ioPadsSpec = [ (IoPin.SOUTH, None, 'p_a0'       , 'a(0)'   , 'a(0)'   , 'io_in'   )
-                     , (IoPin.SOUTH, None, 'p_a1'       , 'a(1)'   , 'a(1)'   , 'io_in'   )
-                     , (IoPin.SOUTH, None, 'iopower_0'  , 'iovdd'  )
-                     , (IoPin.SOUTH, None, 'power_0'    , 'vdd'    )
-                     , (IoPin.SOUTH, None, 'p_a2'       , 'a(2)'   , 'a(2)'   , 'io_in'   )
-                     , (IoPin.SOUTH, None, 'p_b3'       , 'b(3)'   , 'b(3)'   , 'io_in'   )
-                     , (IoPin.EAST , None, 'p_tms_0'    , 'tms'    , 'tms'    , 'io_in'   )
-                     , (IoPin.EAST , None, 'p_tdo_0'    , 'tdo'    , 'tdo'    , 'io_out'  )
-                     , (IoPin.EAST , None, 'ground_0'   , 'vss'    )
-                     , (IoPin.EAST , None, 'p_clk'      , 'clk'    , 'clk'    , 'io_in'   )
-                     , (IoPin.EAST , None, 'p_tck'      , 'tck'    , 'tck'    , 'io_in'   )
-                     , (IoPin.EAST , None, 'p_tdi_0'    , 'tdi'    , 'tdi'    , 'io_in'   )
-                     , (IoPin.EAST , None, 'p_b2'       , 'b(2)'   , 'b(2)'   , 'io_in'   )
-                     , (IoPin.NORTH, None, 'ioground_0' , 'iovss'  )
-                     , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'   , 'io_in'   )
-                     , (IoPin.NORTH, None, 'ground_1'   , 'vss'    )
-                     , (IoPin.NORTH, None, 'p_b0'       , 'b(0)'   , 'b(0)'   , 'io_in'   )
-                     , (IoPin.NORTH, None, 'rst'        , 'rst'    , 'rst'    , 'io_in'   )
-                     , (IoPin.WEST , None, 'p_f3'       , 'f(3)'   , 'f(3)'   , 'io_out'  )
-                     , (IoPin.WEST , None, 'p_f2'       , 'f(2)'   , 'f(2)'   , 'io_out'  )
-                     , (IoPin.WEST , None, 'power_1'    , 'vdd'    )
-                     , (IoPin.WEST , None, 'p_f1'       , 'f(1)'   , 'f(1)'   , 'io_out'  )
-                     , (IoPin.WEST , None, 'p_f0'       , 'f(0)'   , 'f(0)'   , 'io_out'  )
-                     , (IoPin.WEST , None, 'p_a3'       , 'a(3)'   , 'a(3)'   , 'io_in'   )
-                     ]
+        #     Spec: 
+        # | Side        | Pos | Instance     | Pad net   |Core net | Direction |
+        ioPadsSpec = [
+           (IoPin.SOUTH, None, 'p_a0'       , 'a(0)'   , 'a(0)'   , 'io_in'   )
+         , (IoPin.SOUTH, None, 'p_a1'       , 'a(1)'   , 'a(1)'   , 'io_in'   )
+         , (IoPin.SOUTH, None, 'iopower_0'  , 'iovdd'  )
+         , (IoPin.SOUTH, None, 'power_0'    , 'vdd'    )
+         , (IoPin.SOUTH, None, 'p_a2'       , 'a(2)'   , 'a(2)'   , 'io_in'   )
+         , (IoPin.SOUTH, None, 'p_b3'       , 'b(3)'   , 'b(3)'   , 'io_in'   )
+         , (IoPin.EAST , None, 'p_tms_0'    , 'tms'    , 'tms'    , 'io_in'   )
+         , (IoPin.EAST , None, 'p_tdo_0'    , 'tdo'    , 'tdo'    , 'io_out'  )
+         , (IoPin.EAST , None, 'ground_0'   , 'vss'    )
+         , (IoPin.EAST , None, 'p_clk'      , 'clk'    , 'clk'    , 'io_in'   )
+         , (IoPin.EAST , None, 'p_tck'      , 'tck'    , 'tck'    , 'io_in'   )
+         , (IoPin.EAST , None, 'p_tdi_0'    , 'tdi'    , 'tdi'    , 'io_in'   )
+         , (IoPin.EAST , None, 'p_b2'       , 'b(2)'   , 'b(2)'   , 'io_in'   )
+         , (IoPin.NORTH, None, 'ioground_0' , 'iovss'  )
+         , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'   , 'io_in'   )
+         , (IoPin.NORTH, None, 'ground_1'   , 'vss'    )
+         , (IoPin.NORTH, None, 'p_b0'       , 'b(0)'   , 'b(0)'   , 'io_in'   )
+         , (IoPin.NORTH, None, 'rst'        , 'rst'    , 'rst'    , 'io_in'   )
+         , (IoPin.WEST , None, 'p_f3'       , 'f(3)'   , 'f(3)'   , 'io_out'  )
+         , (IoPin.WEST , None, 'p_f2'       , 'f(2)'   , 'f(2)'   , 'io_out'  )
+         , (IoPin.WEST , None, 'power_1'    , 'vdd'    )
+         , (IoPin.WEST , None, 'p_f1'       , 'f(1)'   , 'f(1)'   , 'io_out'  )
+         , (IoPin.WEST , None, 'p_f0'       , 'f(0)'   , 'f(0)'   , 'io_out'  )
+         , (IoPin.WEST , None, 'p_a3'       , 'a(3)'   , 'a(3)'   , 'io_in'   )
+        ]
         adderConf = ChipConf( cell, ioPads=ioPadsSpec )
         adderConf.cfg.etesian.bloat = 'nsxlib'
         adderConf.cfg.etesian.uniformDensity = True