From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Tue, 14 Apr 2020 13:44:17 +0000 (+0200)
Subject: abc9_ops: Add a check ensuring that connected port actually exists.
X-Git-Tag: working-ls180~652
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4c52691a58a469a525401bbc83c65f262b2a5504;p=yosys.git

abc9_ops: Add a check ensuring that connected port actually exists.
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 00af36615..8ae1b51ff 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -434,6 +434,9 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 		auto &t = timing.at(derived_type).required;
 		for (auto &conn : cell->connections_) {
 			auto port_wire = inst_module->wire(conn.first);
+			if (!port_wire)
+				log_error("Port %s in cell %s (type %s) of module %s does not actually exist",
+						log_id(conn.first), log_id(cell->name), log_id(cell->type), log_id(module->name));
 			if (!port_wire->port_input)
 				continue;