From: Segher Boessenkool Date: Tue, 4 Jun 2019 23:30:43 +0000 (+0200) Subject: rs6000: Remove Ftrad, Fvsx, Fs; add s and sd X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4c5d4de7b573ba7f64097afbb6d2d1608c522ddf;p=gcc.git rs6000: Remove Ftrad, Fvsx, Fs; add s and sd This removes the , , and mode attributes, and creates new and mode attributes instead. is either "s" or "d", depending on whether the mode is single-precision or double-precision floating point; and is either "s" or nothing. * config/rs6000/rs6000.md (SFDF, SFDF2): Adjust comments. (define_mode_attr sd): New. (define_mode_attr s): New. (define_mode_attr Ftrad): Delete. (define_mode_attr Fvsx): Delete. (define_mode_attr Fs): Delete. (rest of file): Use the new mode attributes. * config.rs6000/vsx.md: Use the new mode attributes. From-SVN: r271931 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 00ca70e8211..fd0b9bffc52 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2019-06-04 Segher Boessenkool + + * config/rs6000/rs6000.md (SFDF, SFDF2): Adjust comments. + (define_mode_attr sd): New. + (define_mode_attr s): New. + (define_mode_attr Ftrad): Delete. + (define_mode_attr Fvsx): Delete. + (define_mode_attr Fs): Delete. + (rest of file): Use the new mode attributes. + * config.rs6000/vsx.md: Use the new mode attributes. + 2019-06-04 Segher Boessenkool * config/rs6000/vsx.md: Replace all that are used with VSX_W diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index f596987fb74..c0a7f7698bb 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -486,13 +486,18 @@ ; Iterator for reciprocal estimate instructions (define_mode_iterator RECIPF [SF DF V4SF V2DF]) -; Iterator for just SF/DF +; SFmode or DFmode. (define_mode_iterator SFDF [SF DF]) -; Like SFDF, but a different name to match conditional move where the -; comparison operands may be a different mode than the input operands. +; And again, for when we need two FP modes in a pattern. (define_mode_iterator SFDF2 [SF DF]) +; A generic s/d attribute, for sp/dp for example. +(define_mode_attr sd [(SF "s") (DF "d")]) + +; "s" or nothing, for fmuls/fmul for example. +(define_mode_attr s [(SF "s") (DF "")]) + ; Iterator for 128-bit floating point that uses the IBM double-double format (define_mode_iterator IBM128 [(IF "FLOAT128_IBM_P (IFmode)") (TF "FLOAT128_IBM_P (TFmode)")]) @@ -513,12 +518,6 @@ ; Iterator for ISA 3.0 supported floating point types (define_mode_iterator FP_ISA3 [SF DF]) -; SF/DF suffix for traditional floating instructions -(define_mode_attr Ftrad [(SF "s") (DF "")]) - -; SF/DF suffix for VSX instructions -(define_mode_attr Fvsx [(SF "sp") (DF "dp")]) - ; SF/DF constraint for arithmetic on traditional floating point registers (define_mode_attr Ff [(SF "f") (DF "d") (DI "d")]) @@ -531,9 +530,6 @@ ; Which isa is needed for those float instructions? (define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")]) -; s/d suffix for things like sdiv/ddiv -(define_mode_attr Fs [(SF "s") (DF "d")]) - ; FRE/FRES support (define_mode_attr Ffre [(SF "fres") (DF "fre")]) (define_mode_attr FFRE [(SF "FRES") (DF "FRE")]) @@ -4638,8 +4634,8 @@ (match_operand:SFDF 2 "gpc_reg_operand" ",wa")))] "TARGET_HARD_FLOAT" "@ - fadd %0,%1,%2 - xsadd %x0,%x1,%x2" + fadd %0,%1,%2 + xsaddp %x0,%x1,%x2" [(set_attr "type" "fp") (set_attr "isa" "*,")]) @@ -4656,8 +4652,8 @@ (match_operand:SFDF 2 "gpc_reg_operand" ",wa")))] "TARGET_HARD_FLOAT" "@ - fsub %0,%1,%2 - xssub %x0,%x1,%x2" + fsub %0,%1,%2 + xssubp %x0,%x1,%x2" [(set_attr "type" "fp") (set_attr "isa" "*,")]) @@ -4674,8 +4670,8 @@ (match_operand:SFDF 2 "gpc_reg_operand" ",wa")))] "TARGET_HARD_FLOAT" "@ - fmul %0,%1,%2 - xsmul %x0,%x1,%x2" + fmul %0,%1,%2 + xsmulp %x0,%x1,%x2" [(set_attr "type" "dmul") (set_attr "isa" "*,")]) @@ -4700,9 +4696,9 @@ (match_operand:SFDF 2 "gpc_reg_operand" ",wa")))] "TARGET_HARD_FLOAT" "@ - fdiv %0,%1,%2 - xsdiv %x0,%x1,%x2" - [(set_attr "type" "div") + fdiv %0,%1,%2 + xsdivp %x0,%x1,%x2" + [(set_attr "type" "div") (set_attr "isa" "*,")]) (define_insn "*sqrt2_internal" @@ -4710,9 +4706,9 @@ (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",wa")))] "TARGET_HARD_FLOAT && TARGET_PPC_GPOPT" "@ - fsqrt %0,%1 - xssqrt %x0,%x1" - [(set_attr "type" "sqrt") + fsqrt %0,%1 + xssqrtp %x0,%x1" + [(set_attr "type" "sqrt") (set_attr "isa" "*,")]) (define_expand "sqrt2" @@ -4733,14 +4729,14 @@ }) ;; Floating point reciprocal approximation -(define_insn "fre" +(define_insn "fre" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",wa")] UNSPEC_FRES))] "TARGET_" "@ - fre %0,%1 - xsre %x0,%x1" + fre %0,%1 + xsrep %x0,%x1" [(set_attr "type" "fp") (set_attr "isa" "*,")]) @@ -4750,8 +4746,8 @@ UNSPEC_RSQRT))] "RS6000_RECIP_HAVE_RSQRTE_P (mode)" "@ - frsqrte %0,%1 - xsrsqrte %x0,%x1" + frsqrte %0,%1 + xsrsqrtep %x0,%x1" [(set_attr "type" "fp") (set_attr "isa" "*,")]) @@ -9390,8 +9386,8 @@ && (!avoiding_indexed_address_p (mode) || !gpc_reg_operand (operands[2], Pmode))" "@ - lfux %3,%0,%2 - lfu %3,%2(%0)" + lfux %3,%0,%2 + lfu %3,%2(%0)" [(set_attr "type" "fpload") (set_attr "update" "yes") (set_attr "indexed" "yes,no") @@ -9407,8 +9403,8 @@ && (!avoiding_indexed_address_p (mode) || !gpc_reg_operand (operands[2], Pmode))" "@ - stfux %3,%0,%2 - stfu %3,%2(%0)" + stfux %3,%0,%2 + stfu %3,%2(%0)" [(set_attr "type" "fpstore") (set_attr "update" "yes") (set_attr "indexed" "yes,no") @@ -13376,9 +13372,9 @@ (match_operand:SFDF 3 "gpc_reg_operand" ",0,wa")))] "TARGET_HARD_FLOAT" "@ - fmadd %0,%1,%2,%3 - xsmadda %x0,%x1,%x2 - xsmaddm %x0,%x1,%x3" + fmadd %0,%1,%2,%3 + xsmaddap %x0,%x1,%x2 + xsmaddmp %x0,%x1,%x3" [(set_attr "type" "fp") (set_attr "isa" "*,,")]) @@ -13400,9 +13396,9 @@ (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" ",0,wa"))))] "TARGET_HARD_FLOAT" "@ - fmsub %0,%1,%2,%3 - xsmsuba %x0,%x1,%x2 - xsmsubm %x0,%x1,%x3" + fmsub %0,%1,%2,%3 + xsmsubap %x0,%x1,%x2 + xsmsubmp %x0,%x1,%x3" [(set_attr "type" "fp") (set_attr "isa" "*,,")]) @@ -13448,9 +13444,9 @@ (match_operand:SFDF 3 "gpc_reg_operand" ",0,wa"))))] "TARGET_HARD_FLOAT" "@ - fnmadd %0,%1,%2,%3 - xsnmadda %x0,%x1,%x2 - xsnmaddm %x0,%x1,%x3" + fnmadd %0,%1,%2,%3 + xsnmaddap %x0,%x1,%x2 + xsnmaddmp %x0,%x1,%x3" [(set_attr "type" "fp") (set_attr "isa" "*,,")]) @@ -13475,9 +13471,9 @@ (match_operand:SFDF 3 "gpc_reg_operand" ",0,wa")))))] "TARGET_HARD_FLOAT" "@ - fnmsub %0,%1,%2,%3 - xsnmsuba %x0,%x1,%x2 - xsnmsubm %x0,%x1,%x3" + fnmsub %0,%1,%2,%3 + xsnmsubap %x0,%x1,%x2 + xsnmsubmp %x0,%x1,%x3" [(set_attr "type" "fp") (set_attr "isa" "*,,")]) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index d349091fb3a..0e04455bbb2 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4612,7 +4612,7 @@ ;; (The lt bit is set if operand 1 is negative. The eq bit is set ;; if any of the conditions tested by operand 2 are satisfied. ;; The gt and unordered bits are cleared to zero.) -(define_expand "xststdc" +(define_expand "xststdcp" [(set (match_dup 3) (compare:CCFP (unspec:SFDF @@ -4647,7 +4647,7 @@ }) ;; The VSX Scalar Test Negative Double- and Single-Precision -(define_expand "xststdcneg" +(define_expand "xststdcnegp" [(set (match_dup 2) (compare:CCFP (unspec:SFDF @@ -4676,7 +4676,7 @@ "xststdcqp %0,%1,%2" [(set_attr "type" "fpcompare")]) -(define_insn "*xststdc" +(define_insn "*xststdcp" [(set (match_operand:CCFP 0 "" "=y") (compare:CCFP (unspec:SFDF [(match_operand:SFDF 1 "vsx_register_operand" "wa") @@ -4684,7 +4684,7 @@ UNSPEC_VSX_STSTDC) (match_operand:SI 3 "zero_constant" "j")))] "TARGET_P9_VECTOR" - "xststdc %0,%x1,%2" + "xststdcp %0,%x1,%2" [(set_attr "type" "fpcompare")]) ;; VSX Vector Extract Exponent Double and Single Precision