From: whitequark Date: Sun, 8 Sep 2019 12:19:13 +0000 (+0000) Subject: hdl.mem,lib,examples: use Signal.range(). X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4c64beed59e3d99bd8b876fb683501f293c6ac78;p=nmigen.git hdl.mem,lib,examples: use Signal.range(). --- diff --git a/examples/basic/fsm.py b/examples/basic/fsm.py index 73e6f7d..86b00db 100644 --- a/examples/basic/fsm.py +++ b/examples/basic/fsm.py @@ -15,7 +15,7 @@ class UARTReceiver(Elaboratable): def elaborate(self, platform): m = Module() - ctr = Signal(max=self.divisor) + ctr = Signal.range(self.divisor) stb = Signal() with m.If(ctr == 0): m.d.sync += ctr.eq(self.divisor - 1) diff --git a/examples/basic/por.py b/examples/basic/por.py index 63eca23..b503e4d 100644 --- a/examples/basic/por.py +++ b/examples/basic/por.py @@ -7,7 +7,7 @@ cd_por = ClockDomain(reset_less=True) cd_sync = ClockDomain() m.domains += cd_por, cd_sync -delay = Signal(max=255, reset=255) +delay = Signal.range(256, reset=255) with m.If(delay != 0): m.d.por += delay.eq(delay - 1) m.d.comb += [ diff --git a/examples/basic/uart.py b/examples/basic/uart.py index 060d2f9..d7a9a9c 100644 --- a/examples/basic/uart.py +++ b/examples/basic/uart.py @@ -31,9 +31,9 @@ class UART(Elaboratable): def elaborate(self, platform): m = Module() - tx_phase = Signal(max=self.divisor) + tx_phase = Signal.range(self.divisor) tx_shreg = Signal(1 + self.data_bits + 1, reset=-1) - tx_count = Signal(max=len(tx_shreg) + 1) + tx_count = Signal.range(len(tx_shreg) + 1) m.d.comb += self.tx_o.eq(tx_shreg[0]) with m.If(tx_count == 0): @@ -54,9 +54,9 @@ class UART(Elaboratable): tx_phase.eq(self.divisor - 1), ] - rx_phase = Signal(max=self.divisor) + rx_phase = Signal.range(self.divisor) rx_shreg = Signal(1 + self.data_bits + 1, reset=-1) - rx_count = Signal(max=len(rx_shreg) + 1) + rx_count = Signal.range(len(rx_shreg) + 1) m.d.comb += self.rx_data.eq(rx_shreg[1:-1]) with m.If(rx_count == 0): diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py index 1ad7f42..c0d7c3d 100644 --- a/nmigen/hdl/mem.py +++ b/nmigen/hdl/mem.py @@ -83,7 +83,7 @@ class ReadPort(Elaboratable): self.domain = domain self.transparent = transparent - self.addr = Signal(max=memory.depth, + self.addr = Signal.range(memory.depth, name="{}_r_addr".format(memory.name), src_loc_at=2) self.data = Signal(memory.width, name="{}_r_data".format(memory.name), src_loc_at=2) @@ -148,7 +148,7 @@ class WritePort(Elaboratable): self.priority = priority self.granularity = granularity - self.addr = Signal(max=memory.depth, + self.addr = Signal.range(memory.depth, name="{}_w_addr".format(memory.name), src_loc_at=2) self.data = Signal(memory.width, name="{}_w_data".format(memory.name), src_loc_at=2) diff --git a/nmigen/lib/coding.py b/nmigen/lib/coding.py index eed02c9..300a718 100644 --- a/nmigen/lib/coding.py +++ b/nmigen/lib/coding.py @@ -25,7 +25,7 @@ class Encoder(Elaboratable): ---------- i : Signal(width), in One-hot input. - o : Signal(max=width), out + o : Signal.range(width), out Encoded binary. n : Signal, out Invalid: either none or multiple input bits are asserted. @@ -34,7 +34,7 @@ class Encoder(Elaboratable): self.width = width self.i = Signal(width) - self.o = Signal(max=max(2, width)) + self.o = Signal.range(width) self.n = Signal() def elaborate(self, platform): @@ -64,7 +64,7 @@ class PriorityEncoder(Elaboratable): ---------- i : Signal(width), in Input requests. - o : Signal(max=width), out + o : Signal.range(width), out Encoded binary. n : Signal, out Invalid: no input bits are asserted. @@ -73,7 +73,7 @@ class PriorityEncoder(Elaboratable): self.width = width self.i = Signal(width) - self.o = Signal(max=max(2, width)) + self.o = Signal.range(width) self.n = Signal() def elaborate(self, platform): @@ -98,7 +98,7 @@ class Decoder(Elaboratable): Attributes ---------- - i : Signal(max=width), in + i : Signal.range(width), in Input binary. o : Signal(width), out Decoded one-hot. @@ -108,7 +108,7 @@ class Decoder(Elaboratable): def __init__(self, width): self.width = width - self.i = Signal(max=max(2, width)) + self.i = Signal.range(width) self.n = Signal() self.o = Signal(width) diff --git a/nmigen/lib/fifo.py b/nmigen/lib/fifo.py index ded86cf..af2f072 100644 --- a/nmigen/lib/fifo.py +++ b/nmigen/lib/fifo.py @@ -136,7 +136,7 @@ class SyncFIFO(Elaboratable, FIFOInterface): def __init__(self, width, depth, fwft=True): super().__init__(width, depth, fwft) - self.level = Signal(max=depth + 1) + self.level = Signal.range(depth + 1) self.replace = Signal() def elaborate(self, platform): @@ -153,8 +153,8 @@ class SyncFIFO(Elaboratable, FIFOInterface): wrport = m.submodules.wrport = storage.write_port() rdport = m.submodules.rdport = storage.read_port( domain="comb" if self.fwft else "sync", transparent=self.fwft) - produce = Signal(max=self.depth) - consume = Signal(max=self.depth) + produce = Signal.range(self.depth) + consume = Signal.range(self.depth) m.d.comb += [ wrport.addr.eq(produce), @@ -234,7 +234,7 @@ class SyncFIFOBuffered(Elaboratable, FIFOInterface): def __init__(self, width, depth): super().__init__(width, depth, fwft=True) - self.level = Signal(max=depth + 1) + self.level = Signal.range(depth + 1) def elaborate(self, platform): m = Module() diff --git a/nmigen/test/test_lib_fifo.py b/nmigen/test/test_lib_fifo.py index 9d136c8..068de5f 100644 --- a/nmigen/test/test_lib_fifo.py +++ b/nmigen/test/test_lib_fifo.py @@ -52,7 +52,7 @@ class FIFOModel(Elaboratable, FIFOInterface): self.wdomain = wdomain self.replace = Signal() - self.level = Signal(max=self.depth + 1) + self.level = Signal.range(self.depth + 1) def elaborate(self, platform): m = Module() @@ -61,8 +61,8 @@ class FIFOModel(Elaboratable, FIFOInterface): wrport = m.submodules.wrport = storage.write_port(domain=self.wdomain) rdport = m.submodules.rdport = storage.read_port (domain="comb") - produce = Signal(max=self.depth) - consume = Signal(max=self.depth) + produce = Signal.range(self.depth) + consume = Signal.range(self.depth) m.d.comb += self.readable.eq(self.level > 0) m.d.comb += rdport.addr.eq((consume + 1) % self.depth)