From: lkcl <lkcl@web>
Date: Mon, 28 Mar 2022 23:55:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2958
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4c687e520287d3c8fdceb49eb2108f073f5fa2c7;p=libreriscv.git

---

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 4ba18ea8d..7ba682add 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -69,16 +69,16 @@ Instruction format:
 |0-5|6-10 |11|12-15|16-18|19-20|21-25  |26-30  |31|name      |
 |---|---- |--|-----|-----|-----|-----  |-----  |--|----      |
 |19 |RT   |  |mask |BB   |     |XO[0:4]|XO[5:9]|/ |          |
-|19 |RT   |0 |mask |BB   | 0 M |XO[0:4]|0 mode |Rc|crrweird  |
-|19 |RA   |1 |mask |BT   | 0 / |XO[0:4]|0 mode |/ |mtcrweird |
-|19 |BT //|0 |mask |BB   | 1 / |XO[0:4]|0 mode |/ |crweird   |
-|19 |BFT  |1 |mask |BB   | 1 M |XO[0:4]|0 mode |/ |crweirder |
+|19 |RT   |M |mask |BB   | 0 0 |XO[0:4]|0 mode |Rc|crrweird  |
+|19 |RA   |/ |mask |BT   | 0 1 |XO[0:4]|0 mode |/ |mtcrweird |
+|19 |BT //|M |mask |BB   | 1 0 |XO[0:4]|0 mode |/ |crweird   |
+|19 |BFT  |/ |mask |BB   | 1 1 |XO[0:4]|0 mode |/ |crweirder |
 
 **crrweird**
 
 mode is encoded in XO and is 4 bits
 
-bit 11=0, bit 19=0
+bit 19=0, bit 20=0
 
     crrweird: RT, BB, mask.mode
 
@@ -97,7 +97,7 @@ such can use Rc=1 and RC1 Data-dependent Mode capability
 
 **mtcrweird**
 
-bit 11=1, bit 19=0
+bit 19=0, bit 20=1
 
     mtcrweird: BT, RA, mask.mode
 
@@ -115,7 +115,7 @@ When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type oper
 
 **crweird**
 
-bit 11=0, bit 19=1
+bit 19=1, bit 20=0
 
     crweird: BT, BB, mask.mode
 
@@ -132,7 +132,7 @@ When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type oper
 
 **crweirder**
 
-bit 11=1, bit 19=1
+bit 19=1, bit 20=1
 
     crweirder: BFT, BB, mask.mode