From: Matt Poremba <Matthew.Poremba@amd.com>
Date: Wed, 14 Sep 2016 03:06:18 +0000 (-0400)
Subject: base: Output all AddrRange parameters to config.ini
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4c903d04128e2232e1121ea5344904bf86342094;p=gem5.git

base: Output all AddrRange parameters to config.ini

Currently only 'start' and 'end' of AddrRange are printed in config.ini.
This causes address ranges to be overlapping when loading a c++-only
config with interleaved addresses using CxxConfigManger. This patch adds
prints for the interleave and XOR bits to config.ini such that address
ranges are properly setup with cxx config.
---

diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 56465e067..ac777fad2 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -778,7 +778,9 @@ class AddrRange(ParamValue):
             raise TypeError, "Too many keywords: %s" % kwargs.keys()
 
     def __str__(self):
-        return '%s:%s' % (self.start, self.end)
+        return '%s:%s:%s:%s:%s:%s' \
+            % (self.start, self.end, self.intlvHighBit, self.xorHighBit,\
+               self.intlvBits, self.intlvMatch)
 
     def size(self):
         # Divide the size by the size of the interleaving slice
@@ -799,16 +801,28 @@ class AddrRange(ParamValue):
 
     @classmethod
     def cxx_ini_parse(cls, code, src, dest, ret):
-        code('uint64_t _start, _end;')
+        code('uint64_t _start, _end, _intlvHighBit = 0, _xorHighBit = 0;')
+        code('uint64_t _intlvBits = 0, _intlvMatch = 0;')
         code('char _sep;')
         code('std::istringstream _stream(${src});')
         code('_stream >> _start;')
         code('_stream.get(_sep);')
         code('_stream >> _end;')
+        code('if (!_stream.fail() && !_stream.eof()) {')
+        code('    _stream.get(_sep);')
+        code('    _stream >> _intlvHighBit;')
+        code('    _stream.get(_sep);')
+        code('    _stream >> _xorHighBit;')
+        code('    _stream.get(_sep);')
+        code('    _stream >> _intlvBits;')
+        code('    _stream.get(_sep);')
+        code('    _stream >> _intlvMatch;')
+        code('}')
         code('bool _ret = !_stream.fail() &&'
             '_stream.eof() && _sep == \':\';')
         code('if (_ret)')
-        code('   ${dest} = AddrRange(_start, _end);')
+        code('   ${dest} = AddrRange(_start, _end, _intlvHighBit, \
+                _xorHighBit, _intlvBits, _intlvMatch);')
         code('${ret} _ret;')
 
     def getValue(self):