From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 Jul 2020 11:54:56 +0000 (+0100)
Subject: note that traptype MUST increase in bitwidth corresponding to additions
X-Git-Tag: semi_working_ecp5~633
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4c9cc2c707416526869b07ffd8ac69cb543f33b2;p=soc.git

note that traptype MUST increase in bitwidth corresponding to additions
to TT
---

diff --git a/src/soc/consts.py b/src/soc/consts.py
index 1a78be88..ee5b4bae 100644
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -27,8 +27,10 @@ class MSR:
 
 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
 
-# note that these correspond to trap_input_record.traptype bits 0,1,2,3
+# note that these correspond to trap_input_record.traptype bits 0,1,2,3,4
 # (TODO: add more?)
+# IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
+# to expand traptype to cope with the increased range
 
 class PI:
     TM_BAD_THING = (63 - 42) # 1 for a TM Bad Thing type interrupt
@@ -39,10 +41,12 @@ class PI:
     ADR   = (63 - 47)    # 0 if SRR0 = address of instruction causing exception
 
 # see traptype (and trap main_stage.py)
+# IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
+# to expand traptype to cope with the increased range
 
 class TT:
     FP = 1<<0
     PRIV = 1<<1
     TRAP = 1<<2
     ADDR = 1<<3
-    ILLEG = 1<<4
+    ILLEG = 1<<4 # currently the max, therefore traptype must be 5 bits