From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 13 Nov 2020 18:04:41 +0000 (+0000)
Subject: reduce nc ls180 pins to match
X-Git-Tag: partial-core-ls180-gdsii~9
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ca14e60a57febd0960482b0c9005674af2d6608;p=soclayout.git

reduce nc ls180 pins to match
---

diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il
index cabbad1..d9fecf5 100644
--- a/experiments9/non_generated/full_core_ls180.il
+++ b/experiments9/non_generated/full_core_ls180.il
@@ -1,5 +1,5 @@
 # Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os)
-autoidx 3721
+autoidx 3709
 attribute \src "libresoc.v:5.1-277.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm"
@@ -72064,96 +72064,96 @@ module \jtag
   connect \_idblock_id_bypass \$9
   connect \_idblock_select_id \$7
 end
-attribute \src "ls180.v:4.1-10575.10"
+attribute \src "ls180.v:4.1-10563.10"
 attribute \cells_not_processed 1
 module \ls180
-  attribute \src "ls180.v:10059.1-10069.4"
-  wire width 7 $0$memwr$\mem$ls180.v:10061$1_ADDR[6:0]$2693
-  attribute \src "ls180.v:10059.1-10069.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10061$1_DATA[31:0]$2694
-  attribute \src "ls180.v:10059.1-10069.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10061$1_EN[31:0]$2695
-  attribute \src "ls180.v:10059.1-10069.4"
-  wire width 7 $0$memwr$\mem$ls180.v:10063$2_ADDR[6:0]$2696
-  attribute \src "ls180.v:10059.1-10069.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10063$2_DATA[31:0]$2697
-  attribute \src "ls180.v:10059.1-10069.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10063$2_EN[31:0]$2698
-  attribute \src "ls180.v:10059.1-10069.4"
-  wire width 7 $0$memwr$\mem$ls180.v:10065$3_ADDR[6:0]$2699
-  attribute \src "ls180.v:10059.1-10069.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10065$3_DATA[31:0]$2700
-  attribute \src "ls180.v:10059.1-10069.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10065$3_EN[31:0]$2701
-  attribute \src "ls180.v:10059.1-10069.4"
-  wire width 7 $0$memwr$\mem$ls180.v:10067$4_ADDR[6:0]$2702
-  attribute \src "ls180.v:10059.1-10069.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10067$4_DATA[31:0]$2703
-  attribute \src "ls180.v:10059.1-10069.4"
-  wire width 32 $0$memwr$\mem$ls180.v:10067$4_EN[31:0]$2704
-  attribute \src "ls180.v:10079.1-10083.4"
-  wire width 3 $0$memwr$\storage$ls180.v:10081$5_ADDR[2:0]$2707
-  attribute \src "ls180.v:10079.1-10083.4"
-  wire width 25 $0$memwr$\storage$ls180.v:10081$5_DATA[24:0]$2708
-  attribute \src "ls180.v:10079.1-10083.4"
-  wire width 25 $0$memwr$\storage$ls180.v:10081$5_EN[24:0]$2709
-  attribute \src "ls180.v:10093.1-10097.4"
-  wire width 3 $0$memwr$\storage_1$ls180.v:10095$6_ADDR[2:0]$2714
-  attribute \src "ls180.v:10093.1-10097.4"
-  wire width 25 $0$memwr$\storage_1$ls180.v:10095$6_DATA[24:0]$2715
-  attribute \src "ls180.v:10093.1-10097.4"
-  wire width 25 $0$memwr$\storage_1$ls180.v:10095$6_EN[24:0]$2716
-  attribute \src "ls180.v:10107.1-10111.4"
-  wire width 3 $0$memwr$\storage_2$ls180.v:10109$7_ADDR[2:0]$2721
-  attribute \src "ls180.v:10107.1-10111.4"
-  wire width 25 $0$memwr$\storage_2$ls180.v:10109$7_DATA[24:0]$2722
-  attribute \src "ls180.v:10107.1-10111.4"
-  wire width 25 $0$memwr$\storage_2$ls180.v:10109$7_EN[24:0]$2723
-  attribute \src "ls180.v:10121.1-10125.4"
-  wire width 3 $0$memwr$\storage_3$ls180.v:10123$8_ADDR[2:0]$2728
-  attribute \src "ls180.v:10121.1-10125.4"
-  wire width 25 $0$memwr$\storage_3$ls180.v:10123$8_DATA[24:0]$2729
-  attribute \src "ls180.v:10121.1-10125.4"
-  wire width 25 $0$memwr$\storage_3$ls180.v:10123$8_EN[24:0]$2730
-  attribute \src "ls180.v:10136.1-10140.4"
-  wire width 4 $0$memwr$\storage_4$ls180.v:10138$9_ADDR[3:0]$2735
-  attribute \src "ls180.v:10136.1-10140.4"
-  wire width 10 $0$memwr$\storage_4$ls180.v:10138$9_DATA[9:0]$2736
-  attribute \src "ls180.v:10136.1-10140.4"
-  wire width 10 $0$memwr$\storage_4$ls180.v:10138$9_EN[9:0]$2737
-  attribute \src "ls180.v:10153.1-10157.4"
-  wire width 4 $0$memwr$\storage_5$ls180.v:10155$10_ADDR[3:0]$2742
-  attribute \src "ls180.v:10153.1-10157.4"
-  wire width 10 $0$memwr$\storage_5$ls180.v:10155$10_DATA[9:0]$2743
-  attribute \src "ls180.v:10153.1-10157.4"
-  wire width 10 $0$memwr$\storage_5$ls180.v:10155$10_EN[9:0]$2744
-  attribute \src "ls180.v:10169.1-10173.4"
-  wire width 5 $0$memwr$\storage_6$ls180.v:10171$11_ADDR[4:0]$2749
-  attribute \src "ls180.v:10169.1-10173.4"
-  wire width 10 $0$memwr$\storage_6$ls180.v:10171$11_DATA[9:0]$2750
-  attribute \src "ls180.v:10169.1-10173.4"
-  wire width 10 $0$memwr$\storage_6$ls180.v:10171$11_EN[9:0]$2751
-  attribute \src "ls180.v:10183.1-10187.4"
-  wire width 5 $0$memwr$\storage_7$ls180.v:10185$12_ADDR[4:0]$2756
-  attribute \src "ls180.v:10183.1-10187.4"
-  wire width 10 $0$memwr$\storage_7$ls180.v:10185$12_DATA[9:0]$2757
-  attribute \src "ls180.v:10183.1-10187.4"
-  wire width 10 $0$memwr$\storage_7$ls180.v:10185$12_EN[9:0]$2758
+  attribute \src "ls180.v:10047.1-10057.4"
+  wire width 7 $0$memwr$\mem$ls180.v:10049$1_ADDR[6:0]$2681
+  attribute \src "ls180.v:10047.1-10057.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10049$1_DATA[31:0]$2682
+  attribute \src "ls180.v:10047.1-10057.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10049$1_EN[31:0]$2683
+  attribute \src "ls180.v:10047.1-10057.4"
+  wire width 7 $0$memwr$\mem$ls180.v:10051$2_ADDR[6:0]$2684
+  attribute \src "ls180.v:10047.1-10057.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10051$2_DATA[31:0]$2685
+  attribute \src "ls180.v:10047.1-10057.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10051$2_EN[31:0]$2686
+  attribute \src "ls180.v:10047.1-10057.4"
+  wire width 7 $0$memwr$\mem$ls180.v:10053$3_ADDR[6:0]$2687
+  attribute \src "ls180.v:10047.1-10057.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10053$3_DATA[31:0]$2688
+  attribute \src "ls180.v:10047.1-10057.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10053$3_EN[31:0]$2689
+  attribute \src "ls180.v:10047.1-10057.4"
+  wire width 7 $0$memwr$\mem$ls180.v:10055$4_ADDR[6:0]$2690
+  attribute \src "ls180.v:10047.1-10057.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10055$4_DATA[31:0]$2691
+  attribute \src "ls180.v:10047.1-10057.4"
+  wire width 32 $0$memwr$\mem$ls180.v:10055$4_EN[31:0]$2692
+  attribute \src "ls180.v:10067.1-10071.4"
+  wire width 3 $0$memwr$\storage$ls180.v:10069$5_ADDR[2:0]$2695
+  attribute \src "ls180.v:10067.1-10071.4"
+  wire width 25 $0$memwr$\storage$ls180.v:10069$5_DATA[24:0]$2696
+  attribute \src "ls180.v:10067.1-10071.4"
+  wire width 25 $0$memwr$\storage$ls180.v:10069$5_EN[24:0]$2697
+  attribute \src "ls180.v:10081.1-10085.4"
+  wire width 3 $0$memwr$\storage_1$ls180.v:10083$6_ADDR[2:0]$2702
+  attribute \src "ls180.v:10081.1-10085.4"
+  wire width 25 $0$memwr$\storage_1$ls180.v:10083$6_DATA[24:0]$2703
+  attribute \src "ls180.v:10081.1-10085.4"
+  wire width 25 $0$memwr$\storage_1$ls180.v:10083$6_EN[24:0]$2704
+  attribute \src "ls180.v:10095.1-10099.4"
+  wire width 3 $0$memwr$\storage_2$ls180.v:10097$7_ADDR[2:0]$2709
+  attribute \src "ls180.v:10095.1-10099.4"
+  wire width 25 $0$memwr$\storage_2$ls180.v:10097$7_DATA[24:0]$2710
+  attribute \src "ls180.v:10095.1-10099.4"
+  wire width 25 $0$memwr$\storage_2$ls180.v:10097$7_EN[24:0]$2711
+  attribute \src "ls180.v:10109.1-10113.4"
+  wire width 3 $0$memwr$\storage_3$ls180.v:10111$8_ADDR[2:0]$2716
+  attribute \src "ls180.v:10109.1-10113.4"
+  wire width 25 $0$memwr$\storage_3$ls180.v:10111$8_DATA[24:0]$2717
+  attribute \src "ls180.v:10109.1-10113.4"
+  wire width 25 $0$memwr$\storage_3$ls180.v:10111$8_EN[24:0]$2718
+  attribute \src "ls180.v:10124.1-10128.4"
+  wire width 4 $0$memwr$\storage_4$ls180.v:10126$9_ADDR[3:0]$2723
+  attribute \src "ls180.v:10124.1-10128.4"
+  wire width 10 $0$memwr$\storage_4$ls180.v:10126$9_DATA[9:0]$2724
+  attribute \src "ls180.v:10124.1-10128.4"
+  wire width 10 $0$memwr$\storage_4$ls180.v:10126$9_EN[9:0]$2725
+  attribute \src "ls180.v:10141.1-10145.4"
+  wire width 4 $0$memwr$\storage_5$ls180.v:10143$10_ADDR[3:0]$2730
+  attribute \src "ls180.v:10141.1-10145.4"
+  wire width 10 $0$memwr$\storage_5$ls180.v:10143$10_DATA[9:0]$2731
+  attribute \src "ls180.v:10141.1-10145.4"
+  wire width 10 $0$memwr$\storage_5$ls180.v:10143$10_EN[9:0]$2732
+  attribute \src "ls180.v:10157.1-10161.4"
+  wire width 5 $0$memwr$\storage_6$ls180.v:10159$11_ADDR[4:0]$2737
+  attribute \src "ls180.v:10157.1-10161.4"
+  wire width 10 $0$memwr$\storage_6$ls180.v:10159$11_DATA[9:0]$2738
+  attribute \src "ls180.v:10157.1-10161.4"
+  wire width 10 $0$memwr$\storage_6$ls180.v:10159$11_EN[9:0]$2739
+  attribute \src "ls180.v:10171.1-10175.4"
+  wire width 5 $0$memwr$\storage_7$ls180.v:10173$12_ADDR[4:0]$2744
+  attribute \src "ls180.v:10171.1-10175.4"
+  wire width 10 $0$memwr$\storage_7$ls180.v:10173$12_DATA[9:0]$2745
+  attribute \src "ls180.v:10171.1-10175.4"
+  wire width 10 $0$memwr$\storage_7$ls180.v:10173$12_EN[9:0]$2746
   attribute \src "ls180.v:3226.1-3319.4"
   wire width 3 $0\builder_bankmachine0_next_state[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\builder_bankmachine0_state[2:0]
   attribute \src "ls180.v:3383.1-3476.4"
   wire width 3 $0\builder_bankmachine1_next_state[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\builder_bankmachine1_state[2:0]
   attribute \src "ls180.v:3540.1-3633.4"
   wire width 3 $0\builder_bankmachine2_next_state[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\builder_bankmachine2_state[2:0]
   attribute \src "ls180.v:3697.1-3790.4"
   wire width 3 $0\builder_bankmachine3_next_state[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\builder_bankmachine3_state[2:0]
   attribute \src "ls180.v:6520.1-6536.4"
   wire $0\builder_comb_rhs_array_muxed0[0:0]
@@ -72233,69 +72233,69 @@ module \ls180
   wire $0\builder_comb_t_array_muxed5[0:0]
   attribute \src "ls180.v:2790.1-2836.4"
   wire $0\builder_converter0_next_state[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_converter0_state[0:0]
   attribute \src "ls180.v:2850.1-2896.4"
   wire $0\builder_converter1_next_state[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_converter1_state[0:0]
   attribute \src "ls180.v:2910.1-2956.4"
   wire $0\builder_converter2_next_state[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_converter2_state[0:0]
   attribute \src "ls180.v:4043.1-4089.4"
   wire $0\builder_converter_next_state[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_converter_state[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 20 $0\builder_count[19:0]
   attribute \src "ls180.v:5760.1-5771.4"
   wire $0\builder_error[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\builder_grant[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 14 $0\builder_libresocsim_adr[13:0]
   attribute \src "ls180.v:5649.1-5685.4"
   wire width 14 $0\builder_libresocsim_adr_next_value1[13:0]
   attribute \src "ls180.v:5649.1-5685.4"
   wire $0\builder_libresocsim_adr_next_value_ce1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\builder_libresocsim_dat_w[7:0]
   attribute \src "ls180.v:5649.1-5685.4"
   wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0]
   attribute \src "ls180.v:5649.1-5685.4"
   wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_libresocsim_we[0:0]
   attribute \src "ls180.v:5649.1-5685.4"
   wire $0\builder_libresocsim_we_next_value2[0:0]
@@ -72317,135 +72317,135 @@ module \ls180
   wire $0\builder_locked3[0:0]
   attribute \src "ls180.v:3915.1-3987.4"
   wire width 3 $0\builder_multiplexer_next_state[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\builder_multiplexer_state[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl0_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl0_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl10_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl10_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl11_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl11_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl12_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl12_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl13_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl13_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl14_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl14_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl15_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl15_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl16_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl16_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl1_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl1_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl2_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl2_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl3_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl3_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl4_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl4_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl5_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl5_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl6_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl6_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl7_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl7_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl8_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl8_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl9_regs0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_multiregimpl9_regs1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_new_master_rdata_valid0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_new_master_rdata_valid1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_new_master_rdata_valid2[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_new_master_rdata_valid3[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_new_master_wdata_ready[0:0]
   attribute \src "ls180.v:5649.1-5685.4"
   wire width 2 $0\builder_next_state[1:0]
   attribute \src "ls180.v:3132.1-3162.4"
   wire width 2 $0\builder_refresher_next_state[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\builder_refresher_state[1:0]
   attribute \src "ls180.v:5459.1-5498.4"
   wire width 2 $0\builder_sdblock2memdma_next_state[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\builder_sdblock2memdma_state[1:0]
   attribute \src "ls180.v:5026.1-5105.4"
   wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_sdcore_crcupstreaminserter_state[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire width 3 $0\builder_sdcore_fsm_next_state[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\builder_sdcore_fsm_state[2:0]
   attribute \src "ls180.v:5518.1-5555.4"
   wire $0\builder_sdmem2blockdma_fsm_next_state[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_sdmem2blockdma_fsm_state[0:0]
   attribute \src "ls180.v:5556.1-5592.4"
   wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0]
   attribute \src "ls180.v:4701.1-4773.4"
   wire width 3 $0\builder_sdphy_fsm_next_state[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\builder_sdphy_fsm_state[2:0]
   attribute \src "ls180.v:4546.1-4639.4"
   wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0]
   attribute \src "ls180.v:4436.1-4512.4"
   wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0]
   attribute \src "ls180.v:4673.1-4700.4"
   wire $0\builder_sdphy_sdphycrcr_next_state[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_sdphy_sdphycrcr_state[0:0]
   attribute \src "ls180.v:4807.1-4908.4"
   wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\builder_sdphy_sdphydatar_state[2:0]
   attribute \src "ls180.v:4402.1-4435.4"
   wire $0\builder_sdphy_sdphyinit_next_state[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\builder_sdphy_sdphyinit_state[0:0]
   attribute \src "ls180.v:5760.1-5771.4"
   wire $0\builder_shared_ack[0:0]
@@ -72453,17 +72453,17 @@ module \ls180
   wire width 32 $0\builder_shared_dat_r[31:0]
   attribute \src "ls180.v:5710.1-5717.4"
   wire width 5 $0\builder_slave_sel[4:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 5 $0\builder_slave_sel_r[4:0]
   attribute \src "ls180.v:4233.1-4281.4"
   wire width 2 $0\builder_spimaster0_next_state[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\builder_spimaster0_state[1:0]
   attribute \src "ls180.v:4292.1-4340.4"
   wire width 2 $0\builder_spimaster1_next_state[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\builder_spimaster1_state[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\builder_state[1:0]
   attribute \src "ls180.v:7201.1-7229.4"
   wire $0\builder_sync_f_array_muxed0[0:0]
@@ -72483,39 +72483,39 @@ module \ls180
   wire $0\builder_sync_rhs_array_muxed5[0:0]
   attribute \src "ls180.v:7184.1-7200.4"
   wire $0\builder_sync_rhs_array_muxed6[0:0]
-  attribute \src "ls180.v:154.11-154.24"
+  attribute \src "ls180.v:133.11-133.24"
   wire width 3 $0\eint_1[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_cmd_consumed[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_converter_counter[0:0]
   attribute \src "ls180.v:4043.1-4089.4"
   wire $0\main_converter_counter_converter_next_value[0:0]
   attribute \src "ls180.v:4043.1-4089.4"
   wire $0\main_converter_counter_converter_next_value_ce[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_converter_dat_r[31:0]
   attribute \src "ls180.v:4043.1-4089.4"
   wire $0\main_converter_skip[0:0]
   attribute \src "ls180.v:7359.1-7429.4"
   wire width 16 $0\main_dfi_p0_rddata[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_dfi_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
-  wire width 36 $0\main_dummy[35:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
+  wire width 24 $0\main_dummy[23:0]
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_gpio_oe_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_gpio_oe_storage[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_gpio_out_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_gpio_out_storage[15:0]
   attribute \src "ls180.v:7316.1-7334.4"
   wire width 16 $0\main_gpio_status[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_i2c_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_i2c_storage[2:0]
   attribute \src "ls180.v:7355.1-7357.4"
   wire $0\main_int_rst[0:0]
@@ -72539,45 +72539,45 @@ module \ls180
   wire $0\main_interface1_bus_stb[0:0]
   attribute \src "ls180.v:5518.1-5555.4"
   wire $0\main_interface1_bus_we[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_libresocsim_bus_errors[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_converter0_counter[0:0]
   attribute \src "ls180.v:2790.1-2836.4"
   wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0]
   attribute \src "ls180.v:2790.1-2836.4"
   wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 64 $0\main_libresocsim_converter0_dat_r[63:0]
   attribute \src "ls180.v:2790.1-2836.4"
   wire $0\main_libresocsim_converter0_skip[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_converter1_counter[0:0]
   attribute \src "ls180.v:2850.1-2896.4"
   wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0]
   attribute \src "ls180.v:2850.1-2896.4"
   wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 64 $0\main_libresocsim_converter1_dat_r[63:0]
   attribute \src "ls180.v:2850.1-2896.4"
   wire $0\main_libresocsim_converter1_skip[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_converter2_counter[0:0]
   attribute \src "ls180.v:2910.1-2956.4"
   wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0]
   attribute \src "ls180.v:2910.1-2956.4"
   wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 64 $0\main_libresocsim_converter2_dat_r[63:0]
   attribute \src "ls180.v:2910.1-2956.4"
   wire $0\main_libresocsim_converter2_skip[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_en_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_en_storage[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_eventmanager_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_eventmanager_storage[0:0]
   attribute \src "ls180.v:2790.1-2836.4"
   wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0]
@@ -72627,17 +72627,17 @@ module \ls180
   wire $0\main_libresocsim_interface2_converted_interface_stb[0:0]
   attribute \src "ls180.v:2910.1-2956.4"
   wire $0\main_libresocsim_interface2_converted_interface_we[0:0]
-  attribute \src "ls180.v:155.12-155.74"
+  attribute \src "ls180.v:159.12-159.74"
   wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
-  attribute \src "ls180.v:130.5-130.69"
+  attribute \src "ls180.v:135.5-135.69"
   wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
-  attribute \src "ls180.v:134.5-134.72"
+  attribute \src "ls180.v:144.5-144.72"
   wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
-  attribute \src "ls180.v:143.12-143.78"
+  attribute \src "ls180.v:148.12-148.78"
   wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
-  attribute \src "ls180.v:141.5-141.74"
+  attribute \src "ls180.v:142.5-142.74"
   wire $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
-  attribute \src "ls180.v:161.5-161.74"
+  attribute \src "ls180.v:132.5-132.74"
   wire $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
   attribute \src "ls180.v:2850.1-2896.4"
   wire $0\main_libresocsim_libresoc_dbus_ack[0:0]
@@ -72653,41 +72653,41 @@ module \ls180
   wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0]
   attribute \src "ls180.v:118.5-118.49"
   wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_load_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_libresocsim_load_storage[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_ram_bus_ack[0:0]
   attribute \src "ls180.v:217.5-217.40"
   wire $0\main_libresocsim_ram_bus_err[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_reload_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_libresocsim_reload_storage[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_reset_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_reset_storage[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_scratch_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_libresocsim_scratch_storage[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_update_value_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_update_value_storage[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_libresocsim_value[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_libresocsim_value_status[31:0]
   attribute \src "ls180.v:2959.1-2965.4"
   wire width 4 $0\main_libresocsim_we[3:0]
   attribute \src "ls180.v:2971.1-2976.4"
   wire $0\main_libresocsim_zero_clear[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_zero_old_trigger[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_libresocsim_zero_pending[0:0]
   attribute \src "ls180.v:4043.1-4089.4"
   wire width 30 $0\main_litedram_wb_adr[29:0]
@@ -72701,53 +72701,53 @@ module \ls180
   wire $0\main_litedram_wb_stb[0:0]
   attribute \src "ls180.v:4043.1-4089.4"
   wire $0\main_litedram_wb_we[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_pwm0_counter[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_pwm0_enable_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_pwm0_enable_storage[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_pwm0_period_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_pwm0_period_storage[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_pwm0_width_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_pwm0_width_storage[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_pwm1_counter[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_pwm1_enable_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_pwm1_enable_storage[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_pwm1_period_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_pwm1_period_storage[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_pwm1_width_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_pwm1_width_storage[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_rddata_en[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\main_sdblock2mem_converter_demux[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdblock2mem_converter_source_first[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdblock2mem_converter_source_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdblock2mem_converter_strobe_all[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 5 $0\main_sdblock2mem_fifo_consume[4:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 6 $0\main_sdblock2mem_fifo_level[5:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 5 $0\main_sdblock2mem_fifo_produce[4:0]
   attribute \src "ls180.v:1582.5-1582.41"
   wire $0\main_sdblock2mem_fifo_replace[0:0]
@@ -72759,23 +72759,23 @@ module \ls180
   wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0]
   attribute \src "ls180.v:5459.1-5498.4"
   wire $0\main_sdblock2mem_sink_sink_valid1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0]
   attribute \src "ls180.v:5459.1-5498.4"
   wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
@@ -72785,41 +72785,41 @@ module \ls180
   wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
   attribute \src "ls180.v:5459.1-5498.4"
   wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdcore_block_count_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_sdcore_block_count_storage[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdcore_block_length_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 10 $0\main_sdcore_block_length_storage[9:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdcore_cmd_argument_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_sdcore_cmd_argument_storage[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdcore_cmd_command_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_sdcore_cmd_command_storage[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdcore_cmd_count[2:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdcore_cmd_done[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdcore_cmd_error[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 128 $0\main_sdcore_cmd_response_status[127:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
@@ -72827,53 +72827,53 @@ module \ls180
   wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
   attribute \src "ls180.v:1391.5-1391.34"
   wire $0\main_sdcore_cmd_send_w[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdcore_cmd_timeout[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0]
   attribute \src "ls180.v:5114.1-5121.4"
   wire $0\main_sdcore_crc16_checker_crc0_clr[0:0]
   attribute \src "ls180.v:5170.1-5177.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
   attribute \src "ls180.v:5124.1-5131.4"
   wire $0\main_sdcore_crc16_checker_crc1_clr[0:0]
   attribute \src "ls180.v:5180.1-5187.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
   attribute \src "ls180.v:5134.1-5141.4"
   wire $0\main_sdcore_crc16_checker_crc2_clr[0:0]
   attribute \src "ls180.v:5190.1-5197.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
   attribute \src "ls180.v:5144.1-5151.4"
   wire $0\main_sdcore_crc16_checker_crc3_clr[0:0]
   attribute \src "ls180.v:5200.1-5207.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_crc16_checker_sink_first[0:0]
@@ -72889,11 +72889,11 @@ module \ls180
   wire $0\main_sdcore_crc16_checker_source_first[0:0]
   attribute \src "ls180.v:5153.1-5158.4"
   wire $0\main_sdcore_crc16_checker_source_valid[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_sdcore_crc16_checker_val[7:0]
   attribute \src "ls180.v:5106.1-5111.4"
   wire $0\main_sdcore_crc16_checker_valid[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0]
   attribute \src "ls180.v:5026.1-5105.4"
   wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
@@ -72901,39 +72901,39 @@ module \ls180
   wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
   attribute \src "ls180.v:4988.1-4995.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
   attribute \src "ls180.v:4998.1-5005.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
   attribute \src "ls180.v:5008.1-5015.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
   attribute \src "ls180.v:5018.1-5025.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0]
   attribute \src "ls180.v:5026.1-5105.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
   attribute \src "ls180.v:5026.1-5105.4"
   wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0]
   attribute \src "ls180.v:5026.1-5105.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
   attribute \src "ls180.v:5026.1-5105.4"
   wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0]
   attribute \src "ls180.v:5026.1-5105.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
   attribute \src "ls180.v:5026.1-5105.4"
   wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0]
   attribute \src "ls180.v:5026.1-5105.4"
   wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
@@ -72953,41 +72953,41 @@ module \ls180
   wire $0\main_sdcore_crc16_inserter_source_valid[0:0]
   attribute \src "ls180.v:4966.1-4973.4"
   wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_sdcore_data_count[31:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdcore_data_done[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdcore_data_error[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdcore_data_timeout[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\main_sdmem2block_converter_mux[1:0]
   attribute \src "ls180.v:5604.1-5620.4"
   wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdmem2block_dma_base_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 64 $0\main_sdmem2block_dma_base_storage[63:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_sdmem2block_dma_data[31:0]
   attribute \src "ls180.v:5518.1-5555.4"
   wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
@@ -72995,19 +72995,19 @@ module \ls180
   wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
   attribute \src "ls180.v:5556.1-5592.4"
   wire $0\main_sdmem2block_dma_done_status[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdmem2block_dma_enable_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdmem2block_dma_enable_storage[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdmem2block_dma_length_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_sdmem2block_dma_length_storage[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdmem2block_dma_loop_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdmem2block_dma_loop_storage[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_sdmem2block_dma_offset[31:0]
   attribute \src "ls180.v:5556.1-5592.4"
   wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
@@ -73029,65 +73029,65 @@ module \ls180
   wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0]
   attribute \src "ls180.v:5518.1-5555.4"
   wire $0\main_sdmem2block_dma_source_valid[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 5 $0\main_sdmem2block_fifo_consume[4:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 6 $0\main_sdmem2block_fifo_level[5:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 5 $0\main_sdmem2block_fifo_produce[4:0]
   attribute \src "ls180.v:1718.5-1718.41"
   wire $0\main_sdmem2block_fifo_replace[0:0]
   attribute \src "ls180.v:5634.1-5641.4"
   wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_clocker_clk0[0:0]
   attribute \src "ls180.v:4372.1-4400.4"
   wire $0\main_sdphy_clocker_clk1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_clocker_clk_d[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 9 $0\main_sdphy_clocker_clks[8:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_clocker_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 9 $0\main_sdphy_clocker_storage[8:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0]
   attribute \src "ls180.v:1183.5-1183.53"
   wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0]
   attribute \src "ls180.v:1184.5-1184.52"
   wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
   attribute \src "ls180.v:1164.5-1164.46"
   wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_cmdr_cmdr_reset[0:0]
   attribute \src "ls180.v:4546.1-4639.4"
   wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
   attribute \src "ls180.v:4546.1-4639.4"
   wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_cmdr_cmdr_run[0:0]
   attribute \src "ls180.v:4546.1-4639.4"
   wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_sdphy_cmdr_count[7:0]
   attribute \src "ls180.v:4546.1-4639.4"
   wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
@@ -73135,13 +73135,13 @@ module \ls180
   wire $0\main_sdphy_cmdr_source_ready[0:0]
   attribute \src "ls180.v:4546.1-4639.4"
   wire $0\main_sdphy_cmdr_source_valid[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_sdphy_cmdr_timeout[31:0]
   attribute \src "ls180.v:4546.1-4639.4"
   wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
   attribute \src "ls180.v:4546.1-4639.4"
   wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_sdphy_cmdw_count[7:0]
   attribute \src "ls180.v:4436.1-4512.4"
   wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
@@ -73167,45 +73167,45 @@ module \ls180
   wire $0\main_sdphy_cmdw_sink_ready[0:0]
   attribute \src "ls180.v:5208.1-5398.4"
   wire $0\main_sdphy_cmdw_sink_valid[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 10 $0\main_sdphy_datar_count[9:0]
   attribute \src "ls180.v:4807.1-4908.4"
   wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
   attribute \src "ls180.v:4807.1-4908.4"
   wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_datar_datar_buf_source_first[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_datar_datar_buf_source_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_datar_datar_buf_source_valid[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_datar_datar_converter_demux[0:0]
   attribute \src "ls180.v:1339.5-1339.55"
   wire $0\main_sdphy_datar_datar_converter_sink_first[0:0]
   attribute \src "ls180.v:1340.5-1340.54"
   wire $0\main_sdphy_datar_datar_converter_sink_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_datar_datar_converter_source_first[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_datar_datar_converter_source_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0]
   attribute \src "ls180.v:1320.5-1320.48"
   wire $0\main_sdphy_datar_datar_pads_in_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_datar_datar_reset[0:0]
   attribute \src "ls180.v:4807.1-4908.4"
   wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
   attribute \src "ls180.v:4807.1-4908.4"
   wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_datar_datar_run[0:0]
   attribute \src "ls180.v:4807.1-4908.4"
   wire $0\main_sdphy_datar_datar_source_source_ready0[0:0]
@@ -73255,51 +73255,51 @@ module \ls180
   wire $0\main_sdphy_datar_source_valid[0:0]
   attribute \src "ls180.v:4807.1-4908.4"
   wire $0\main_sdphy_datar_stop[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_sdphy_datar_timeout[31:0]
   attribute \src "ls180.v:4807.1-4908.4"
   wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
   attribute \src "ls180.v:4807.1-4908.4"
   wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_sdphy_dataw_count[7:0]
   attribute \src "ls180.v:4701.1-4773.4"
   wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
   attribute \src "ls180.v:4701.1-4773.4"
   wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0]
   attribute \src "ls180.v:1261.5-1261.54"
   wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0]
   attribute \src "ls180.v:1262.5-1262.53"
   wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
   attribute \src "ls180.v:1242.5-1242.47"
   wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_dataw_crcr_reset[0:0]
   attribute \src "ls180.v:4673.1-4700.4"
   wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
   attribute \src "ls180.v:4673.1-4700.4"
   wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdphy_dataw_crcr_run[0:0]
   attribute \src "ls180.v:4673.1-4700.4"
   wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0]
@@ -73351,7 +73351,7 @@ module \ls180
   wire $0\main_sdphy_dataw_stop[0:0]
   attribute \src "ls180.v:4673.1-4700.4"
   wire $0\main_sdphy_dataw_valid[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_sdphy_init_count[7:0]
   attribute \src "ls180.v:4402.1-4435.4"
   wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
@@ -73373,21 +73373,21 @@ module \ls180
   wire $0\main_sdphy_sdpads_cmd_i[0:0]
   attribute \src "ls180.v:7359.1-7429.4"
   wire width 4 $0\main_sdphy_sdpads_data_i[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_address_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 13 $0\main_sdram_address_storage[12:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_baddress_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\main_sdram_baddress_storage[1:0]
   attribute \src "ls180.v:3188.1-3195.4"
   wire $0\main_sdram_bankmachine0_auto_precharge[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
   attribute \src "ls180.v:449.5-449.64"
   wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
@@ -73397,15 +73397,15 @@ module \ls180
   wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
   attribute \src "ls180.v:3210.1-3217.4"
   wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
   attribute \src "ls180.v:3177.1-3184.4"
   wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0]
@@ -73431,7 +73431,7 @@ module \ls180
   wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0]
   attribute \src "ls180.v:3226.1-3319.4"
   wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 13 $0\main_sdram_bankmachine0_row[12:0]
   attribute \src "ls180.v:3226.1-3319.4"
   wire $0\main_sdram_bankmachine0_row_close[0:0]
@@ -73439,23 +73439,23 @@ module \ls180
   wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
   attribute \src "ls180.v:3226.1-3319.4"
   wire $0\main_sdram_bankmachine0_row_open[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine0_row_opened[0:0]
   attribute \src "ls180.v:491.32-491.76"
   wire $0\main_sdram_bankmachine0_trascon_ready[0:0]
   attribute \src "ls180.v:489.32-489.75"
   wire $0\main_sdram_bankmachine0_trccon_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0]
   attribute \src "ls180.v:3345.1-3352.4"
   wire $0\main_sdram_bankmachine1_auto_precharge[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
   attribute \src "ls180.v:531.5-531.64"
   wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
@@ -73465,15 +73465,15 @@ module \ls180
   wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
   attribute \src "ls180.v:3367.1-3374.4"
   wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
   attribute \src "ls180.v:3334.1-3341.4"
   wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0]
@@ -73499,7 +73499,7 @@ module \ls180
   wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0]
   attribute \src "ls180.v:3383.1-3476.4"
   wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 13 $0\main_sdram_bankmachine1_row[12:0]
   attribute \src "ls180.v:3383.1-3476.4"
   wire $0\main_sdram_bankmachine1_row_close[0:0]
@@ -73507,23 +73507,23 @@ module \ls180
   wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
   attribute \src "ls180.v:3383.1-3476.4"
   wire $0\main_sdram_bankmachine1_row_open[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine1_row_opened[0:0]
   attribute \src "ls180.v:573.32-573.76"
   wire $0\main_sdram_bankmachine1_trascon_ready[0:0]
   attribute \src "ls180.v:571.32-571.75"
   wire $0\main_sdram_bankmachine1_trccon_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0]
   attribute \src "ls180.v:3502.1-3509.4"
   wire $0\main_sdram_bankmachine2_auto_precharge[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
   attribute \src "ls180.v:613.5-613.64"
   wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
@@ -73533,15 +73533,15 @@ module \ls180
   wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
   attribute \src "ls180.v:3524.1-3531.4"
   wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
   attribute \src "ls180.v:3491.1-3498.4"
   wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0]
@@ -73567,7 +73567,7 @@ module \ls180
   wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0]
   attribute \src "ls180.v:3540.1-3633.4"
   wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 13 $0\main_sdram_bankmachine2_row[12:0]
   attribute \src "ls180.v:3540.1-3633.4"
   wire $0\main_sdram_bankmachine2_row_close[0:0]
@@ -73575,23 +73575,23 @@ module \ls180
   wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
   attribute \src "ls180.v:3540.1-3633.4"
   wire $0\main_sdram_bankmachine2_row_open[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine2_row_opened[0:0]
   attribute \src "ls180.v:655.32-655.76"
   wire $0\main_sdram_bankmachine2_trascon_ready[0:0]
   attribute \src "ls180.v:653.32-653.75"
   wire $0\main_sdram_bankmachine2_trccon_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0]
   attribute \src "ls180.v:3659.1-3666.4"
   wire $0\main_sdram_bankmachine3_auto_precharge[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
   attribute \src "ls180.v:695.5-695.64"
   wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
@@ -73601,15 +73601,15 @@ module \ls180
   wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
   attribute \src "ls180.v:3681.1-3688.4"
   wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
   attribute \src "ls180.v:3648.1-3655.4"
   wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0]
@@ -73635,7 +73635,7 @@ module \ls180
   wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0]
   attribute \src "ls180.v:3697.1-3790.4"
   wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 13 $0\main_sdram_bankmachine3_row[12:0]
   attribute \src "ls180.v:3697.1-3790.4"
   wire $0\main_sdram_bankmachine3_row_close[0:0]
@@ -73643,15 +73643,15 @@ module \ls180
   wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
   attribute \src "ls180.v:3697.1-3790.4"
   wire $0\main_sdram_bankmachine3_row_open[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine3_row_opened[0:0]
   attribute \src "ls180.v:737.32-737.76"
   wire $0\main_sdram_bankmachine3_trascon_ready[0:0]
   attribute \src "ls180.v:735.32-735.75"
   wire $0\main_sdram_bankmachine3_trccon_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0]
   attribute \src "ls180.v:3824.1-3829.4"
   wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0]
@@ -73661,7 +73661,7 @@ module \ls180
   wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0]
   attribute \src "ls180.v:745.5-745.43"
   wire $0\main_sdram_choose_cmd_cmd_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\main_sdram_choose_cmd_grant[1:0]
   attribute \src "ls180.v:3810.1-3816.4"
   wire width 4 $0\main_sdram_choose_cmd_valids[3:0]
@@ -73681,7 +73681,7 @@ module \ls180
   wire $0\main_sdram_choose_req_cmd_payload_we[0:0]
   attribute \src "ls180.v:3915.1-3987.4"
   wire $0\main_sdram_choose_req_cmd_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\main_sdram_choose_req_grant[1:0]
   attribute \src "ls180.v:3843.1-3849.4"
   wire width 4 $0\main_sdram_choose_req_valids[3:0]
@@ -73693,19 +73693,19 @@ module \ls180
   wire $0\main_sdram_choose_req_want_writes[0:0]
   attribute \src "ls180.v:3132.1-3162.4"
   wire $0\main_sdram_cmd_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 13 $0\main_sdram_cmd_payload_a[12:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\main_sdram_cmd_payload_ba[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_cmd_payload_cas[0:0]
   attribute \src "ls180.v:393.5-393.42"
   wire $0\main_sdram_cmd_payload_is_read[0:0]
   attribute \src "ls180.v:394.5-394.43"
   wire $0\main_sdram_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_cmd_payload_we[0:0]
   attribute \src "ls180.v:3915.1-3987.4"
   wire $0\main_sdram_cmd_ready[0:0]
@@ -73713,27 +73713,27 @@ module \ls180
   wire $0\main_sdram_cmd_valid[0:0]
   attribute \src "ls180.v:329.5-329.38"
   wire $0\main_sdram_command_issue_w[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_command_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 6 $0\main_sdram_command_storage[5:0]
   attribute \src "ls180.v:378.5-378.35"
   wire $0\main_sdram_dfi_p0_act_n[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 13 $0\main_sdram_dfi_p0_address[12:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\main_sdram_dfi_p0_bank[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_dfi_p0_cas_n[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_dfi_p0_cs_n[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_dfi_p0_ras_n[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_dfi_p0_rddata_en[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_dfi_p0_we_n[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_dfi_p0_wrdata_en[0:0]
   attribute \src "ls180.v:3915.1-3987.4"
   wire $0\main_sdram_en0[0:0]
@@ -73789,17 +73789,17 @@ module \ls180
   wire width 13 $0\main_sdram_nop_a[12:0]
   attribute \src "ls180.v:777.11-777.35"
   wire width 2 $0\main_sdram_nop_ba[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_postponer_count[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_postponer_req_o[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_sequencer_count[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_sdram_sequencer_counter[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_sequencer_done1[0:0]
   attribute \src "ls180.v:3132.1-3162.4"
   wire $0\main_sdram_sequencer_start0[0:0]
@@ -73807,7 +73807,7 @@ module \ls180
   wire width 16 $0\main_sdram_slave_p0_rddata[15:0]
   attribute \src "ls180.v:3015.1-3069.4"
   wire $0\main_sdram_slave_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdram_status[15:0]
   attribute \src "ls180.v:779.5-779.31"
   wire $0\main_sdram_steerer0[0:0]
@@ -73815,55 +73815,55 @@ module \ls180
   wire $0\main_sdram_steerer1[0:0]
   attribute \src "ls180.v:3915.1-3987.4"
   wire width 2 $0\main_sdram_steerer_sel[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_sdram_storage[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_tccdcon_count[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_tccdcon_ready[0:0]
   attribute \src "ls180.v:784.32-784.63"
   wire $0\main_sdram_tfawcon_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 5 $0\main_sdram_time0[4:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_sdram_time1[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 10 $0\main_sdram_timer_count1[9:0]
   attribute \src "ls180.v:782.32-782.63"
   wire $0\main_sdram_trrdcon_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_sdram_twtrcon_count[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_twtrcon_ready[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_sdram_wrdata_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_sdram_wrdata_storage[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_spimaster11_storage[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_spimaster12_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_spimaster16_storage[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_spimaster17_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_spimaster1_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_spimaster1_storage[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_spimaster21_storage[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_spimaster22_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_spimaster23_storage[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_spimaster24_re[0:0]
   attribute \src "ls180.v:4233.1-4281.4"
   wire $0\main_spimaster25_clk_enable[0:0]
   attribute \src "ls180.v:4233.1-4281.4"
   wire $0\main_spimaster26_cs_enable[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_spimaster27_count[2:0]
   attribute \src "ls180.v:4233.1-4281.4"
   wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0]
@@ -73875,31 +73875,31 @@ module \ls180
   wire $0\main_spimaster29_miso_latch[0:0]
   attribute \src "ls180.v:4233.1-4281.4"
   wire $0\main_spimaster2_done[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_spimaster30_clk_divider[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_spimaster33_mosi_data[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_spimaster34_mosi_sel[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_spimaster35_miso_data[7:0]
   attribute \src "ls180.v:4233.1-4281.4"
   wire $0\main_spimaster3_irq[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_spimaster5_miso[7:0]
   attribute \src "ls180.v:1000.12-1000.47"
   wire width 16 $0\main_spimaster8_clk_divider[15:0]
   attribute \src "ls180.v:6285.1-6290.4"
   wire $0\main_spimaster9_start[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_spisdcard_clk_divider1[15:0]
   attribute \src "ls180.v:4292.1-4340.4"
   wire $0\main_spisdcard_clk_enable[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_spisdcard_control_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 16 $0\main_spisdcard_control_storage[15:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_spisdcard_count[2:0]
   attribute \src "ls180.v:4292.1-4340.4"
   wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0]
@@ -73907,109 +73907,109 @@ module \ls180
   wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0]
   attribute \src "ls180.v:4292.1-4340.4"
   wire $0\main_spisdcard_cs_enable[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_spisdcard_cs_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_spisdcard_cs_storage[0:0]
   attribute \src "ls180.v:4292.1-4340.4"
   wire $0\main_spisdcard_done0[0:0]
   attribute \src "ls180.v:4292.1-4340.4"
   wire $0\main_spisdcard_irq[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_spisdcard_loopback_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_spisdcard_loopback_storage[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_spisdcard_miso[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_spisdcard_miso_data[7:0]
   attribute \src "ls180.v:4292.1-4340.4"
   wire $0\main_spisdcard_miso_latch[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_spisdcard_mosi_data[7:0]
   attribute \src "ls180.v:4292.1-4340.4"
   wire $0\main_spisdcard_mosi_latch[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_spisdcard_mosi_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 3 $0\main_spisdcard_mosi_sel[2:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_spisdcard_mosi_storage[7:0]
   attribute \src "ls180.v:6331.1-6336.4"
   wire $0\main_spisdcard_start1[0:0]
   attribute \src "ls180.v:4151.1-4155.4"
   wire width 2 $0\main_uart_eventmanager_pending_w[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_eventmanager_re[0:0]
   attribute \src "ls180.v:4140.1-4144.4"
   wire width 2 $0\main_uart_eventmanager_status_w[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\main_uart_eventmanager_storage[1:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_phy_re[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_uart_phy_rx_bitcount[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_phy_rx_busy[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_phy_rx_r[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_uart_phy_rx_reg[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_phy_sink_ready[0:0]
   attribute \src "ls180.v:855.5-855.38"
   wire $0\main_uart_phy_source_first[0:0]
   attribute \src "ls180.v:856.5-856.37"
   wire $0\main_uart_phy_source_last[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_uart_phy_source_payload_data[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_phy_source_valid[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 32 $0\main_uart_phy_storage[31:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_uart_phy_tx_bitcount[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_phy_tx_busy[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 8 $0\main_uart_phy_tx_reg[7:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_phy_uart_clk_rxen[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_phy_uart_clk_txen[0:0]
   attribute \src "ls180.v:982.5-982.27"
   wire $0\main_uart_reset[0:0]
   attribute \src "ls180.v:4145.1-4150.4"
   wire $0\main_uart_rx_clear[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_uart_rx_fifo_consume[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 5 $0\main_uart_rx_fifo_level0[4:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_uart_rx_fifo_produce[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_rx_fifo_readable[0:0]
   attribute \src "ls180.v:964.5-964.37"
   wire $0\main_uart_rx_fifo_replace[0:0]
   attribute \src "ls180.v:4203.1-4210.4"
   wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_rx_old_trigger[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_rx_pending[0:0]
   attribute \src "ls180.v:4134.1-4139.4"
   wire $0\main_uart_tx_clear[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_uart_tx_fifo_consume[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 5 $0\main_uart_tx_fifo_level0[4:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 4 $0\main_uart_tx_fifo_produce[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_tx_fifo_readable[0:0]
   attribute \src "ls180.v:927.5-927.37"
   wire $0\main_uart_tx_fifo_replace[0:0]
@@ -74019,39 +74019,39 @@ module \ls180
   wire $0\main_uart_tx_fifo_sink_last[0:0]
   attribute \src "ls180.v:4173.1-4180.4"
   wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_tx_old_trigger[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_uart_tx_pending[0:0]
   attribute \src "ls180.v:4043.1-4089.4"
   wire $0\main_wb_sdram_ack[0:0]
   attribute \src "ls180.v:823.5-823.29"
   wire $0\main_wb_sdram_err[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\main_wdata_consumed[0:0]
-  attribute \src "ls180.v:10059.1-10069.4"
+  attribute \src "ls180.v:10047.1-10057.4"
   wire width 7 $0\memadr[6:0]
-  attribute \src "ls180.v:10079.1-10083.4"
+  attribute \src "ls180.v:10067.1-10071.4"
   wire width 25 $0\memdat[24:0]
-  attribute \src "ls180.v:10093.1-10097.4"
+  attribute \src "ls180.v:10081.1-10085.4"
   wire width 25 $0\memdat_1[24:0]
-  attribute \src "ls180.v:10107.1-10111.4"
+  attribute \src "ls180.v:10095.1-10099.4"
   wire width 25 $0\memdat_2[24:0]
-  attribute \src "ls180.v:10121.1-10125.4"
+  attribute \src "ls180.v:10109.1-10113.4"
   wire width 25 $0\memdat_3[24:0]
-  attribute \src "ls180.v:10136.1-10140.4"
+  attribute \src "ls180.v:10124.1-10128.4"
   wire width 10 $0\memdat_4[9:0]
-  attribute \src "ls180.v:10142.1-10145.4"
+  attribute \src "ls180.v:10130.1-10133.4"
   wire width 10 $0\memdat_5[9:0]
-  attribute \src "ls180.v:10153.1-10157.4"
+  attribute \src "ls180.v:10141.1-10145.4"
   wire width 10 $0\memdat_6[9:0]
-  attribute \src "ls180.v:10159.1-10162.4"
+  attribute \src "ls180.v:10147.1-10150.4"
   wire width 10 $0\memdat_7[9:0]
-  attribute \src "ls180.v:10169.1-10173.4"
+  attribute \src "ls180.v:10157.1-10161.4"
   wire width 10 $0\memdat_8[9:0]
-  attribute \src "ls180.v:10183.1-10187.4"
+  attribute \src "ls180.v:10171.1-10175.4"
   wire width 10 $0\memdat_9[9:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire width 2 $0\pwm[1:0]
   attribute \src "ls180.v:7359.1-7429.4"
   wire $0\sdcard_clk[0:0]
@@ -74085,19 +74085,19 @@ module \ls180
   wire $0\sdram_ras_n[0:0]
   attribute \src "ls180.v:7359.1-7429.4"
   wire $0\sdram_we_n[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\spimaster_clk[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\spimaster_cs_n[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\spimaster_mosi[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\spisdcard_clk[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\spisdcard_cs_n[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\spisdcard_mosi[0:0]
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   wire $0\uart_tx[0:0]
   attribute \src "ls180.v:1749.11-1749.49"
   wire width 3 $1\builder_bankmachine0_next_state[2:0]
@@ -74450,7 +74450,7 @@ module \ls180
   attribute \src "ls180.v:268.5-268.36"
   wire $1\main_dfi_p0_rddata_valid[0:0]
   attribute \src "ls180.v:1067.12-1067.30"
-  wire width 36 $1\main_dummy[35:0]
+  wire width 24 $1\main_dummy[23:0]
   attribute \src "ls180.v:984.5-984.27"
   wire $1\main_gpio_oe_re[0:0]
   attribute \src "ls180.v:983.12-983.40"
@@ -75793,96 +75793,96 @@ module \ls180
   wire width 32 $add$ls180.v:5569$1010_Y
   attribute \src "ls180.v:5571.77-5571.111"
   wire width 32 $add$ls180.v:5571$1011_Y
-  attribute \src "ls180.v:7503.36-7503.70"
-  wire width 32 $add$ls180.v:7503$2415_Y
-  attribute \src "ls180.v:7588.37-7588.72"
-  wire width 4 $add$ls180.v:7588$2436_Y
-  attribute \src "ls180.v:7605.60-7605.119"
-  wire width 3 $add$ls180.v:7605$2440_Y
-  attribute \src "ls180.v:7608.60-7608.119"
-  wire width 3 $add$ls180.v:7608$2441_Y
-  attribute \src "ls180.v:7612.59-7612.116"
-  wire width 4 $add$ls180.v:7612$2446_Y
-  attribute \src "ls180.v:7651.60-7651.119"
-  wire width 3 $add$ls180.v:7651$2456_Y
-  attribute \src "ls180.v:7654.60-7654.119"
-  wire width 3 $add$ls180.v:7654$2457_Y
-  attribute \src "ls180.v:7658.59-7658.116"
-  wire width 4 $add$ls180.v:7658$2462_Y
-  attribute \src "ls180.v:7697.60-7697.119"
-  wire width 3 $add$ls180.v:7697$2472_Y
-  attribute \src "ls180.v:7700.60-7700.119"
-  wire width 3 $add$ls180.v:7700$2473_Y
-  attribute \src "ls180.v:7704.59-7704.116"
-  wire width 4 $add$ls180.v:7704$2478_Y
-  attribute \src "ls180.v:7743.60-7743.119"
-  wire width 3 $add$ls180.v:7743$2488_Y
-  attribute \src "ls180.v:7746.60-7746.119"
-  wire width 3 $add$ls180.v:7746$2489_Y
-  attribute \src "ls180.v:7750.59-7750.116"
-  wire width 4 $add$ls180.v:7750$2494_Y
-  attribute \src "ls180.v:7980.34-7980.66"
-  wire width 4 $add$ls180.v:7980$2548_Y
-  attribute \src "ls180.v:7996.73-7996.131"
-  wire width 33 $add$ls180.v:7996$2551_Y
-  attribute \src "ls180.v:8009.34-8009.66"
-  wire width 4 $add$ls180.v:8009$2555_Y
-  attribute \src "ls180.v:8028.73-8028.131"
-  wire width 33 $add$ls180.v:8028$2558_Y
-  attribute \src "ls180.v:8054.33-8054.65"
-  wire width 4 $add$ls180.v:8054$2566_Y
-  attribute \src "ls180.v:8057.33-8057.65"
-  wire width 4 $add$ls180.v:8057$2567_Y
-  attribute \src "ls180.v:8061.33-8061.64"
-  wire width 5 $add$ls180.v:8061$2572_Y
-  attribute \src "ls180.v:8076.33-8076.65"
-  wire width 4 $add$ls180.v:8076$2577_Y
-  attribute \src "ls180.v:8079.33-8079.65"
-  wire width 4 $add$ls180.v:8079$2578_Y
-  attribute \src "ls180.v:8083.33-8083.64"
-  wire width 5 $add$ls180.v:8083$2583_Y
-  attribute \src "ls180.v:8104.35-8104.70"
-  wire width 16 $add$ls180.v:8104$2585_Y
-  attribute \src "ls180.v:8139.34-8139.68"
-  wire width 16 $add$ls180.v:8139$2590_Y
-  attribute \src "ls180.v:8175.25-8175.49"
-  wire width 32 $add$ls180.v:8175$2595_Y
-  attribute \src "ls180.v:8189.25-8189.49"
-  wire width 32 $add$ls180.v:8189$2599_Y
-  attribute \src "ls180.v:8203.31-8203.61"
-  wire width 9 $add$ls180.v:8203$2604_Y
-  attribute \src "ls180.v:8226.45-8226.88"
-  wire width 3 $add$ls180.v:8226$2608_Y
-  attribute \src "ls180.v:8272.71-8272.114"
-  wire width 4 $add$ls180.v:8272$2614_Y
-  attribute \src "ls180.v:8307.46-8307.90"
-  wire width 3 $add$ls180.v:8307$2620_Y
-  attribute \src "ls180.v:8353.72-8353.116"
-  wire width 4 $add$ls180.v:8353$2626_Y
-  attribute \src "ls180.v:8386.47-8386.92"
-  wire $add$ls180.v:8386$2632_Y
-  attribute \src "ls180.v:8414.73-8414.118"
-  wire width 2 $add$ls180.v:8414$2638_Y
-  attribute \src "ls180.v:8526.39-8526.75"
-  wire width 4 $add$ls180.v:8526$2651_Y
-  attribute \src "ls180.v:8587.37-8587.73"
-  wire width 5 $add$ls180.v:8587$2655_Y
-  attribute \src "ls180.v:8590.37-8590.73"
-  wire width 5 $add$ls180.v:8590$2656_Y
-  attribute \src "ls180.v:8594.36-8594.70"
-  wire width 6 $add$ls180.v:8594$2661_Y
-  attribute \src "ls180.v:8609.41-8609.80"
-  wire width 2 $add$ls180.v:8609$2665_Y
-  attribute \src "ls180.v:8643.67-8643.106"
-  wire width 3 $add$ls180.v:8643$2671_Y
-  attribute \src "ls180.v:8669.39-8669.76"
-  wire width 2 $add$ls180.v:8669$2673_Y
-  attribute \src "ls180.v:8673.37-8673.73"
-  wire width 5 $add$ls180.v:8673$2677_Y
-  attribute \src "ls180.v:8676.37-8676.73"
-  wire width 5 $add$ls180.v:8676$2678_Y
-  attribute \src "ls180.v:8680.36-8680.70"
-  wire width 6 $add$ls180.v:8680$2683_Y
+  attribute \src "ls180.v:7491.36-7491.70"
+  wire width 32 $add$ls180.v:7491$2403_Y
+  attribute \src "ls180.v:7576.37-7576.72"
+  wire width 4 $add$ls180.v:7576$2424_Y
+  attribute \src "ls180.v:7593.60-7593.119"
+  wire width 3 $add$ls180.v:7593$2428_Y
+  attribute \src "ls180.v:7596.60-7596.119"
+  wire width 3 $add$ls180.v:7596$2429_Y
+  attribute \src "ls180.v:7600.59-7600.116"
+  wire width 4 $add$ls180.v:7600$2434_Y
+  attribute \src "ls180.v:7639.60-7639.119"
+  wire width 3 $add$ls180.v:7639$2444_Y
+  attribute \src "ls180.v:7642.60-7642.119"
+  wire width 3 $add$ls180.v:7642$2445_Y
+  attribute \src "ls180.v:7646.59-7646.116"
+  wire width 4 $add$ls180.v:7646$2450_Y
+  attribute \src "ls180.v:7685.60-7685.119"
+  wire width 3 $add$ls180.v:7685$2460_Y
+  attribute \src "ls180.v:7688.60-7688.119"
+  wire width 3 $add$ls180.v:7688$2461_Y
+  attribute \src "ls180.v:7692.59-7692.116"
+  wire width 4 $add$ls180.v:7692$2466_Y
+  attribute \src "ls180.v:7731.60-7731.119"
+  wire width 3 $add$ls180.v:7731$2476_Y
+  attribute \src "ls180.v:7734.60-7734.119"
+  wire width 3 $add$ls180.v:7734$2477_Y
+  attribute \src "ls180.v:7738.59-7738.116"
+  wire width 4 $add$ls180.v:7738$2482_Y
+  attribute \src "ls180.v:7968.34-7968.66"
+  wire width 4 $add$ls180.v:7968$2536_Y
+  attribute \src "ls180.v:7984.73-7984.131"
+  wire width 33 $add$ls180.v:7984$2539_Y
+  attribute \src "ls180.v:7997.34-7997.66"
+  wire width 4 $add$ls180.v:7997$2543_Y
+  attribute \src "ls180.v:8016.73-8016.131"
+  wire width 33 $add$ls180.v:8016$2546_Y
+  attribute \src "ls180.v:8042.33-8042.65"
+  wire width 4 $add$ls180.v:8042$2554_Y
+  attribute \src "ls180.v:8045.33-8045.65"
+  wire width 4 $add$ls180.v:8045$2555_Y
+  attribute \src "ls180.v:8049.33-8049.64"
+  wire width 5 $add$ls180.v:8049$2560_Y
+  attribute \src "ls180.v:8064.33-8064.65"
+  wire width 4 $add$ls180.v:8064$2565_Y
+  attribute \src "ls180.v:8067.33-8067.65"
+  wire width 4 $add$ls180.v:8067$2566_Y
+  attribute \src "ls180.v:8071.33-8071.64"
+  wire width 5 $add$ls180.v:8071$2571_Y
+  attribute \src "ls180.v:8092.35-8092.70"
+  wire width 16 $add$ls180.v:8092$2573_Y
+  attribute \src "ls180.v:8127.34-8127.68"
+  wire width 16 $add$ls180.v:8127$2578_Y
+  attribute \src "ls180.v:8163.25-8163.49"
+  wire width 32 $add$ls180.v:8163$2583_Y
+  attribute \src "ls180.v:8177.25-8177.49"
+  wire width 32 $add$ls180.v:8177$2587_Y
+  attribute \src "ls180.v:8191.31-8191.61"
+  wire width 9 $add$ls180.v:8191$2592_Y
+  attribute \src "ls180.v:8214.45-8214.88"
+  wire width 3 $add$ls180.v:8214$2596_Y
+  attribute \src "ls180.v:8260.71-8260.114"
+  wire width 4 $add$ls180.v:8260$2602_Y
+  attribute \src "ls180.v:8295.46-8295.90"
+  wire width 3 $add$ls180.v:8295$2608_Y
+  attribute \src "ls180.v:8341.72-8341.116"
+  wire width 4 $add$ls180.v:8341$2614_Y
+  attribute \src "ls180.v:8374.47-8374.92"
+  wire $add$ls180.v:8374$2620_Y
+  attribute \src "ls180.v:8402.73-8402.118"
+  wire width 2 $add$ls180.v:8402$2626_Y
+  attribute \src "ls180.v:8514.39-8514.75"
+  wire width 4 $add$ls180.v:8514$2639_Y
+  attribute \src "ls180.v:8575.37-8575.73"
+  wire width 5 $add$ls180.v:8575$2643_Y
+  attribute \src "ls180.v:8578.37-8578.73"
+  wire width 5 $add$ls180.v:8578$2644_Y
+  attribute \src "ls180.v:8582.36-8582.70"
+  wire width 6 $add$ls180.v:8582$2649_Y
+  attribute \src "ls180.v:8597.41-8597.80"
+  wire width 2 $add$ls180.v:8597$2653_Y
+  attribute \src "ls180.v:8631.67-8631.106"
+  wire width 3 $add$ls180.v:8631$2659_Y
+  attribute \src "ls180.v:8657.39-8657.76"
+  wire width 2 $add$ls180.v:8657$2661_Y
+  attribute \src "ls180.v:8661.37-8661.73"
+  wire width 5 $add$ls180.v:8661$2665_Y
+  attribute \src "ls180.v:8664.37-8664.73"
+  wire width 5 $add$ls180.v:8664$2666_Y
+  attribute \src "ls180.v:8668.36-8668.70"
+  wire width 6 $add$ls180.v:8668$2671_Y
   attribute \src "ls180.v:2813.9-2813.80"
   wire $and$ls180.v:2813$17_Y
   attribute \src "ls180.v:2831.9-2831.80"
@@ -77897,156 +77897,156 @@ module \ls180
   wire $and$ls180.v:7197$2366_Y
   attribute \src "ls180.v:7416.17-7416.67"
   wire $and$ls180.v:7416$2373_Y
-  attribute \src "ls180.v:7507.8-7507.67"
-  wire $and$ls180.v:7507$2416_Y
-  attribute \src "ls180.v:7507.7-7507.102"
-  wire $and$ls180.v:7507$2418_Y
-  attribute \src "ls180.v:7526.7-7526.75"
-  wire $and$ls180.v:7526$2422_Y
-  attribute \src "ls180.v:7534.7-7534.56"
-  wire $and$ls180.v:7534$2424_Y
-  attribute \src "ls180.v:7562.7-7562.75"
-  wire $and$ls180.v:7562$2431_Y
-  attribute \src "ls180.v:7604.8-7604.131"
-  wire $and$ls180.v:7604$2437_Y
-  attribute \src "ls180.v:7604.7-7604.190"
-  wire $and$ls180.v:7604$2439_Y
-  attribute \src "ls180.v:7610.8-7610.131"
-  wire $and$ls180.v:7610$2442_Y
-  attribute \src "ls180.v:7610.7-7610.190"
-  wire $and$ls180.v:7610$2444_Y
-  attribute \src "ls180.v:7650.8-7650.131"
-  wire $and$ls180.v:7650$2453_Y
-  attribute \src "ls180.v:7650.7-7650.190"
-  wire $and$ls180.v:7650$2455_Y
-  attribute \src "ls180.v:7656.8-7656.131"
-  wire $and$ls180.v:7656$2458_Y
-  attribute \src "ls180.v:7656.7-7656.190"
-  wire $and$ls180.v:7656$2460_Y
-  attribute \src "ls180.v:7696.8-7696.131"
-  wire $and$ls180.v:7696$2469_Y
-  attribute \src "ls180.v:7696.7-7696.190"
-  wire $and$ls180.v:7696$2471_Y
-  attribute \src "ls180.v:7702.8-7702.131"
-  wire $and$ls180.v:7702$2474_Y
-  attribute \src "ls180.v:7702.7-7702.190"
-  wire $and$ls180.v:7702$2476_Y
-  attribute \src "ls180.v:7742.8-7742.131"
-  wire $and$ls180.v:7742$2485_Y
-  attribute \src "ls180.v:7742.7-7742.190"
-  wire $and$ls180.v:7742$2487_Y
-  attribute \src "ls180.v:7748.8-7748.131"
-  wire $and$ls180.v:7748$2490_Y
-  attribute \src "ls180.v:7748.7-7748.190"
-  wire $and$ls180.v:7748$2492_Y
-  attribute \src "ls180.v:7945.48-7945.124"
-  wire $and$ls180.v:7945$2517_Y
-  attribute \src "ls180.v:7945.130-7945.206"
-  wire $and$ls180.v:7945$2520_Y
-  attribute \src "ls180.v:7945.212-7945.288"
-  wire $and$ls180.v:7945$2523_Y
-  attribute \src "ls180.v:7945.294-7945.370"
-  wire $and$ls180.v:7945$2526_Y
-  attribute \src "ls180.v:7946.49-7946.125"
-  wire $and$ls180.v:7946$2529_Y
-  attribute \src "ls180.v:7946.131-7946.207"
-  wire $and$ls180.v:7946$2532_Y
-  attribute \src "ls180.v:7946.213-7946.289"
-  wire $and$ls180.v:7946$2535_Y
-  attribute \src "ls180.v:7946.295-7946.371"
-  wire $and$ls180.v:7946$2538_Y
-  attribute \src "ls180.v:7965.8-7965.49"
-  wire $and$ls180.v:7965$2541_Y
-  attribute \src "ls180.v:7968.8-7968.53"
-  wire $and$ls180.v:7968$2542_Y
-  attribute \src "ls180.v:7973.8-7973.59"
-  wire $and$ls180.v:7973$2544_Y
-  attribute \src "ls180.v:7973.7-7973.90"
-  wire $and$ls180.v:7973$2546_Y
-  attribute \src "ls180.v:7979.8-7979.59"
-  wire $and$ls180.v:7979$2547_Y
-  attribute \src "ls180.v:8003.8-8003.48"
-  wire $and$ls180.v:8003$2554_Y
-  attribute \src "ls180.v:8036.7-8036.57"
-  wire $and$ls180.v:8036$2560_Y
-  attribute \src "ls180.v:8043.7-8043.57"
-  wire $and$ls180.v:8043$2562_Y
-  attribute \src "ls180.v:8053.8-8053.75"
-  wire $and$ls180.v:8053$2563_Y
-  attribute \src "ls180.v:8053.7-8053.107"
-  wire $and$ls180.v:8053$2565_Y
-  attribute \src "ls180.v:8059.8-8059.75"
-  wire $and$ls180.v:8059$2568_Y
-  attribute \src "ls180.v:8059.7-8059.107"
-  wire $and$ls180.v:8059$2570_Y
-  attribute \src "ls180.v:8075.8-8075.75"
-  wire $and$ls180.v:8075$2574_Y
-  attribute \src "ls180.v:8075.7-8075.107"
-  wire $and$ls180.v:8075$2576_Y
-  attribute \src "ls180.v:8081.8-8081.75"
-  wire $and$ls180.v:8081$2579_Y
-  attribute \src "ls180.v:8081.7-8081.107"
-  wire $and$ls180.v:8081$2581_Y
-  attribute \src "ls180.v:8229.7-8229.96"
-  wire $and$ls180.v:8229$2609_Y
-  attribute \src "ls180.v:8230.8-8230.93"
-  wire $and$ls180.v:8230$2610_Y
-  attribute \src "ls180.v:8238.8-8238.93"
-  wire $and$ls180.v:8238$2611_Y
-  attribute \src "ls180.v:8310.7-8310.98"
-  wire $and$ls180.v:8310$2621_Y
-  attribute \src "ls180.v:8311.8-8311.95"
-  wire $and$ls180.v:8311$2622_Y
-  attribute \src "ls180.v:8319.8-8319.95"
-  wire $and$ls180.v:8319$2623_Y
-  attribute \src "ls180.v:8389.7-8389.100"
-  wire $and$ls180.v:8389$2633_Y
-  attribute \src "ls180.v:8390.8-8390.97"
-  wire $and$ls180.v:8390$2634_Y
-  attribute \src "ls180.v:8398.8-8398.97"
-  wire $and$ls180.v:8398$2635_Y
+  attribute \src "ls180.v:7495.8-7495.67"
+  wire $and$ls180.v:7495$2404_Y
+  attribute \src "ls180.v:7495.7-7495.102"
+  wire $and$ls180.v:7495$2406_Y
+  attribute \src "ls180.v:7514.7-7514.75"
+  wire $and$ls180.v:7514$2410_Y
+  attribute \src "ls180.v:7522.7-7522.56"
+  wire $and$ls180.v:7522$2412_Y
+  attribute \src "ls180.v:7550.7-7550.75"
+  wire $and$ls180.v:7550$2419_Y
+  attribute \src "ls180.v:7592.8-7592.131"
+  wire $and$ls180.v:7592$2425_Y
+  attribute \src "ls180.v:7592.7-7592.190"
+  wire $and$ls180.v:7592$2427_Y
+  attribute \src "ls180.v:7598.8-7598.131"
+  wire $and$ls180.v:7598$2430_Y
+  attribute \src "ls180.v:7598.7-7598.190"
+  wire $and$ls180.v:7598$2432_Y
+  attribute \src "ls180.v:7638.8-7638.131"
+  wire $and$ls180.v:7638$2441_Y
+  attribute \src "ls180.v:7638.7-7638.190"
+  wire $and$ls180.v:7638$2443_Y
+  attribute \src "ls180.v:7644.8-7644.131"
+  wire $and$ls180.v:7644$2446_Y
+  attribute \src "ls180.v:7644.7-7644.190"
+  wire $and$ls180.v:7644$2448_Y
+  attribute \src "ls180.v:7684.8-7684.131"
+  wire $and$ls180.v:7684$2457_Y
+  attribute \src "ls180.v:7684.7-7684.190"
+  wire $and$ls180.v:7684$2459_Y
+  attribute \src "ls180.v:7690.8-7690.131"
+  wire $and$ls180.v:7690$2462_Y
+  attribute \src "ls180.v:7690.7-7690.190"
+  wire $and$ls180.v:7690$2464_Y
+  attribute \src "ls180.v:7730.8-7730.131"
+  wire $and$ls180.v:7730$2473_Y
+  attribute \src "ls180.v:7730.7-7730.190"
+  wire $and$ls180.v:7730$2475_Y
+  attribute \src "ls180.v:7736.8-7736.131"
+  wire $and$ls180.v:7736$2478_Y
+  attribute \src "ls180.v:7736.7-7736.190"
+  wire $and$ls180.v:7736$2480_Y
+  attribute \src "ls180.v:7933.48-7933.124"
+  wire $and$ls180.v:7933$2505_Y
+  attribute \src "ls180.v:7933.130-7933.206"
+  wire $and$ls180.v:7933$2508_Y
+  attribute \src "ls180.v:7933.212-7933.288"
+  wire $and$ls180.v:7933$2511_Y
+  attribute \src "ls180.v:7933.294-7933.370"
+  wire $and$ls180.v:7933$2514_Y
+  attribute \src "ls180.v:7934.49-7934.125"
+  wire $and$ls180.v:7934$2517_Y
+  attribute \src "ls180.v:7934.131-7934.207"
+  wire $and$ls180.v:7934$2520_Y
+  attribute \src "ls180.v:7934.213-7934.289"
+  wire $and$ls180.v:7934$2523_Y
+  attribute \src "ls180.v:7934.295-7934.371"
+  wire $and$ls180.v:7934$2526_Y
+  attribute \src "ls180.v:7953.8-7953.49"
+  wire $and$ls180.v:7953$2529_Y
+  attribute \src "ls180.v:7956.8-7956.53"
+  wire $and$ls180.v:7956$2530_Y
+  attribute \src "ls180.v:7961.8-7961.59"
+  wire $and$ls180.v:7961$2532_Y
+  attribute \src "ls180.v:7961.7-7961.90"
+  wire $and$ls180.v:7961$2534_Y
+  attribute \src "ls180.v:7967.8-7967.59"
+  wire $and$ls180.v:7967$2535_Y
+  attribute \src "ls180.v:7991.8-7991.48"
+  wire $and$ls180.v:7991$2542_Y
+  attribute \src "ls180.v:8024.7-8024.57"
+  wire $and$ls180.v:8024$2548_Y
+  attribute \src "ls180.v:8031.7-8031.57"
+  wire $and$ls180.v:8031$2550_Y
+  attribute \src "ls180.v:8041.8-8041.75"
+  wire $and$ls180.v:8041$2551_Y
+  attribute \src "ls180.v:8041.7-8041.107"
+  wire $and$ls180.v:8041$2553_Y
+  attribute \src "ls180.v:8047.8-8047.75"
+  wire $and$ls180.v:8047$2556_Y
+  attribute \src "ls180.v:8047.7-8047.107"
+  wire $and$ls180.v:8047$2558_Y
+  attribute \src "ls180.v:8063.8-8063.75"
+  wire $and$ls180.v:8063$2562_Y
+  attribute \src "ls180.v:8063.7-8063.107"
+  wire $and$ls180.v:8063$2564_Y
+  attribute \src "ls180.v:8069.8-8069.75"
+  wire $and$ls180.v:8069$2567_Y
+  attribute \src "ls180.v:8069.7-8069.107"
+  wire $and$ls180.v:8069$2569_Y
+  attribute \src "ls180.v:8217.7-8217.96"
+  wire $and$ls180.v:8217$2597_Y
+  attribute \src "ls180.v:8218.8-8218.93"
+  wire $and$ls180.v:8218$2598_Y
+  attribute \src "ls180.v:8226.8-8226.93"
+  wire $and$ls180.v:8226$2599_Y
+  attribute \src "ls180.v:8298.7-8298.98"
+  wire $and$ls180.v:8298$2609_Y
+  attribute \src "ls180.v:8299.8-8299.95"
+  wire $and$ls180.v:8299$2610_Y
+  attribute \src "ls180.v:8307.8-8307.95"
+  wire $and$ls180.v:8307$2611_Y
+  attribute \src "ls180.v:8377.7-8377.100"
+  wire $and$ls180.v:8377$2621_Y
+  attribute \src "ls180.v:8378.8-8378.97"
+  wire $and$ls180.v:8378$2622_Y
+  attribute \src "ls180.v:8386.8-8386.97"
+  wire $and$ls180.v:8386$2623_Y
+  attribute \src "ls180.v:8477.7-8477.82"
+  wire $and$ls180.v:8477$2629_Y
+  attribute \src "ls180.v:8480.7-8480.82"
+  wire $and$ls180.v:8480$2630_Y
+  attribute \src "ls180.v:8483.7-8483.82"
+  wire $and$ls180.v:8483$2631_Y
+  attribute \src "ls180.v:8486.7-8486.82"
+  wire $and$ls180.v:8486$2632_Y
   attribute \src "ls180.v:8489.7-8489.82"
-  wire $and$ls180.v:8489$2641_Y
-  attribute \src "ls180.v:8492.7-8492.82"
-  wire $and$ls180.v:8492$2642_Y
-  attribute \src "ls180.v:8495.7-8495.82"
-  wire $and$ls180.v:8495$2643_Y
-  attribute \src "ls180.v:8498.7-8498.82"
-  wire $and$ls180.v:8498$2644_Y
-  attribute \src "ls180.v:8501.7-8501.82"
-  wire $and$ls180.v:8501$2645_Y
-  attribute \src "ls180.v:8506.7-8506.82"
-  wire $and$ls180.v:8506$2646_Y
-  attribute \src "ls180.v:8511.7-8511.82"
-  wire $and$ls180.v:8511$2647_Y
-  attribute \src "ls180.v:8516.7-8516.82"
-  wire $and$ls180.v:8516$2648_Y
-  attribute \src "ls180.v:8521.7-8521.82"
-  wire $and$ls180.v:8521$2649_Y
-  attribute \src "ls180.v:8586.8-8586.83"
-  wire $and$ls180.v:8586$2652_Y
-  attribute \src "ls180.v:8586.7-8586.119"
-  wire $and$ls180.v:8586$2654_Y
-  attribute \src "ls180.v:8592.8-8592.83"
-  wire $and$ls180.v:8592$2657_Y
-  attribute \src "ls180.v:8592.7-8592.119"
-  wire $and$ls180.v:8592$2659_Y
-  attribute \src "ls180.v:8612.7-8612.88"
-  wire $and$ls180.v:8612$2666_Y
-  attribute \src "ls180.v:8613.8-8613.85"
-  wire $and$ls180.v:8613$2667_Y
-  attribute \src "ls180.v:8621.8-8621.85"
-  wire $and$ls180.v:8621$2668_Y
-  attribute \src "ls180.v:8665.7-8665.88"
-  wire $and$ls180.v:8665$2672_Y
-  attribute \src "ls180.v:8672.8-8672.83"
-  wire $and$ls180.v:8672$2674_Y
-  attribute \src "ls180.v:8672.7-8672.119"
-  wire $and$ls180.v:8672$2676_Y
-  attribute \src "ls180.v:8678.8-8678.83"
-  wire $and$ls180.v:8678$2679_Y
-  attribute \src "ls180.v:8678.7-8678.119"
-  wire $and$ls180.v:8678$2681_Y
+  wire $and$ls180.v:8489$2633_Y
+  attribute \src "ls180.v:8494.7-8494.82"
+  wire $and$ls180.v:8494$2634_Y
+  attribute \src "ls180.v:8499.7-8499.82"
+  wire $and$ls180.v:8499$2635_Y
+  attribute \src "ls180.v:8504.7-8504.82"
+  wire $and$ls180.v:8504$2636_Y
+  attribute \src "ls180.v:8509.7-8509.82"
+  wire $and$ls180.v:8509$2637_Y
+  attribute \src "ls180.v:8574.8-8574.83"
+  wire $and$ls180.v:8574$2640_Y
+  attribute \src "ls180.v:8574.7-8574.119"
+  wire $and$ls180.v:8574$2642_Y
+  attribute \src "ls180.v:8580.8-8580.83"
+  wire $and$ls180.v:8580$2645_Y
+  attribute \src "ls180.v:8580.7-8580.119"
+  wire $and$ls180.v:8580$2647_Y
+  attribute \src "ls180.v:8600.7-8600.88"
+  wire $and$ls180.v:8600$2654_Y
+  attribute \src "ls180.v:8601.8-8601.85"
+  wire $and$ls180.v:8601$2655_Y
+  attribute \src "ls180.v:8609.8-8609.85"
+  wire $and$ls180.v:8609$2656_Y
+  attribute \src "ls180.v:8653.7-8653.88"
+  wire $and$ls180.v:8653$2660_Y
+  attribute \src "ls180.v:8660.8-8660.83"
+  wire $and$ls180.v:8660$2662_Y
+  attribute \src "ls180.v:8660.7-8660.119"
+  wire $and$ls180.v:8660$2664_Y
+  attribute \src "ls180.v:8666.8-8666.83"
+  wire $and$ls180.v:8666$2667_Y
+  attribute \src "ls180.v:8666.7-8666.119"
+  wire $and$ls180.v:8666$2669_Y
   attribute \src "ls180.v:2814.42-2814.101"
   wire $eq$ls180.v:2814$18_Y
   attribute \src "ls180.v:2821.11-2821.54"
@@ -79043,180 +79043,180 @@ module \ls180
   wire $eq$ls180.v:6918$2313_Y
   attribute \src "ls180.v:6918.294-6918.327"
   wire $eq$ls180.v:6918$2316_Y
-  attribute \src "ls180.v:7511.8-7511.38"
-  wire $eq$ls180.v:7511$2419_Y
-  attribute \src "ls180.v:7542.8-7542.42"
-  wire $eq$ls180.v:7542$2427_Y
-  attribute \src "ls180.v:7562.38-7562.74"
-  wire $eq$ls180.v:7562$2430_Y
-  attribute \src "ls180.v:7569.7-7569.43"
-  wire $eq$ls180.v:7569$2432_Y
-  attribute \src "ls180.v:7576.7-7576.43"
-  wire $eq$ls180.v:7576$2433_Y
-  attribute \src "ls180.v:7584.7-7584.43"
-  wire $eq$ls180.v:7584$2434_Y
-  attribute \src "ls180.v:7636.9-7636.54"
-  wire $eq$ls180.v:7636$2452_Y
-  attribute \src "ls180.v:7682.9-7682.54"
-  wire $eq$ls180.v:7682$2468_Y
-  attribute \src "ls180.v:7728.9-7728.54"
-  wire $eq$ls180.v:7728$2484_Y
-  attribute \src "ls180.v:7774.9-7774.54"
-  wire $eq$ls180.v:7774$2500_Y
-  attribute \src "ls180.v:7924.9-7924.41"
-  wire $eq$ls180.v:7924$2512_Y
-  attribute \src "ls180.v:7939.9-7939.41"
-  wire $eq$ls180.v:7939$2515_Y
-  attribute \src "ls180.v:7945.49-7945.82"
-  wire $eq$ls180.v:7945$2516_Y
-  attribute \src "ls180.v:7945.131-7945.164"
-  wire $eq$ls180.v:7945$2519_Y
-  attribute \src "ls180.v:7945.213-7945.246"
-  wire $eq$ls180.v:7945$2522_Y
-  attribute \src "ls180.v:7945.295-7945.328"
-  wire $eq$ls180.v:7945$2525_Y
-  attribute \src "ls180.v:7946.50-7946.83"
-  wire $eq$ls180.v:7946$2528_Y
-  attribute \src "ls180.v:7946.132-7946.165"
-  wire $eq$ls180.v:7946$2531_Y
-  attribute \src "ls180.v:7946.214-7946.247"
-  wire $eq$ls180.v:7946$2534_Y
-  attribute \src "ls180.v:7946.296-7946.329"
-  wire $eq$ls180.v:7946$2537_Y
-  attribute \src "ls180.v:7981.9-7981.42"
-  wire $eq$ls180.v:7981$2549_Y
-  attribute \src "ls180.v:7984.10-7984.43"
-  wire $eq$ls180.v:7984$2550_Y
-  attribute \src "ls180.v:8010.9-8010.42"
-  wire $eq$ls180.v:8010$2556_Y
-  attribute \src "ls180.v:8015.10-8015.43"
-  wire $eq$ls180.v:8015$2557_Y
-  attribute \src "ls180.v:8222.9-8222.53"
-  wire $eq$ls180.v:8222$2606_Y
-  attribute \src "ls180.v:8303.9-8303.54"
-  wire $eq$ls180.v:8303$2618_Y
-  attribute \src "ls180.v:8382.9-8382.55"
-  wire $eq$ls180.v:8382$2630_Y
-  attribute \src "ls180.v:8605.9-8605.49"
-  wire $eq$ls180.v:8605$2663_Y
-  attribute \src "ls180.v:8181.8-8181.54"
-  wire $ge$ls180.v:8181$2598_Y
-  attribute \src "ls180.v:8195.8-8195.54"
-  wire $ge$ls180.v:8195$2602_Y
+  attribute \src "ls180.v:7499.8-7499.38"
+  wire $eq$ls180.v:7499$2407_Y
+  attribute \src "ls180.v:7530.8-7530.42"
+  wire $eq$ls180.v:7530$2415_Y
+  attribute \src "ls180.v:7550.38-7550.74"
+  wire $eq$ls180.v:7550$2418_Y
+  attribute \src "ls180.v:7557.7-7557.43"
+  wire $eq$ls180.v:7557$2420_Y
+  attribute \src "ls180.v:7564.7-7564.43"
+  wire $eq$ls180.v:7564$2421_Y
+  attribute \src "ls180.v:7572.7-7572.43"
+  wire $eq$ls180.v:7572$2422_Y
+  attribute \src "ls180.v:7624.9-7624.54"
+  wire $eq$ls180.v:7624$2440_Y
+  attribute \src "ls180.v:7670.9-7670.54"
+  wire $eq$ls180.v:7670$2456_Y
+  attribute \src "ls180.v:7716.9-7716.54"
+  wire $eq$ls180.v:7716$2472_Y
+  attribute \src "ls180.v:7762.9-7762.54"
+  wire $eq$ls180.v:7762$2488_Y
+  attribute \src "ls180.v:7912.9-7912.41"
+  wire $eq$ls180.v:7912$2500_Y
+  attribute \src "ls180.v:7927.9-7927.41"
+  wire $eq$ls180.v:7927$2503_Y
+  attribute \src "ls180.v:7933.49-7933.82"
+  wire $eq$ls180.v:7933$2504_Y
+  attribute \src "ls180.v:7933.131-7933.164"
+  wire $eq$ls180.v:7933$2507_Y
+  attribute \src "ls180.v:7933.213-7933.246"
+  wire $eq$ls180.v:7933$2510_Y
+  attribute \src "ls180.v:7933.295-7933.328"
+  wire $eq$ls180.v:7933$2513_Y
+  attribute \src "ls180.v:7934.50-7934.83"
+  wire $eq$ls180.v:7934$2516_Y
+  attribute \src "ls180.v:7934.132-7934.165"
+  wire $eq$ls180.v:7934$2519_Y
+  attribute \src "ls180.v:7934.214-7934.247"
+  wire $eq$ls180.v:7934$2522_Y
+  attribute \src "ls180.v:7934.296-7934.329"
+  wire $eq$ls180.v:7934$2525_Y
+  attribute \src "ls180.v:7969.9-7969.42"
+  wire $eq$ls180.v:7969$2537_Y
+  attribute \src "ls180.v:7972.10-7972.43"
+  wire $eq$ls180.v:7972$2538_Y
+  attribute \src "ls180.v:7998.9-7998.42"
+  wire $eq$ls180.v:7998$2544_Y
+  attribute \src "ls180.v:8003.10-8003.43"
+  wire $eq$ls180.v:8003$2545_Y
+  attribute \src "ls180.v:8210.9-8210.53"
+  wire $eq$ls180.v:8210$2594_Y
+  attribute \src "ls180.v:8291.9-8291.54"
+  wire $eq$ls180.v:8291$2606_Y
+  attribute \src "ls180.v:8370.9-8370.55"
+  wire $eq$ls180.v:8370$2618_Y
+  attribute \src "ls180.v:8593.9-8593.49"
+  wire $eq$ls180.v:8593$2651_Y
+  attribute \src "ls180.v:8169.8-8169.54"
+  wire $ge$ls180.v:8169$2586_Y
+  attribute \src "ls180.v:8183.8-8183.54"
+  wire $ge$ls180.v:8183$2590_Y
   attribute \src "ls180.v:5155.47-5155.83"
   wire $gt$ls180.v:5155$914_Y
   attribute \src "ls180.v:5161.7-5161.43"
   wire $lt$ls180.v:5161$917_Y
-  attribute \src "ls180.v:8176.8-8176.43"
-  wire $lt$ls180.v:8176$2596_Y
-  attribute \src "ls180.v:8190.8-8190.43"
-  wire $lt$ls180.v:8190$2600_Y
-  attribute \src "ls180.v:10071.33-10071.36"
-  wire width 32 $memrd$\mem$ls180.v:10071$2705_DATA
-  attribute \src "ls180.v:10082.12-10082.19"
-  wire width 25 $memrd$\storage$ls180.v:10082$2710_DATA
-  attribute \src "ls180.v:10089.68-10089.75"
-  wire width 25 $memrd$\storage$ls180.v:10089$2712_DATA
-  attribute \src "ls180.v:10096.14-10096.23"
-  wire width 25 $memrd$\storage_1$ls180.v:10096$2717_DATA
-  attribute \src "ls180.v:10103.68-10103.77"
-  wire width 25 $memrd$\storage_1$ls180.v:10103$2719_DATA
-  attribute \src "ls180.v:10110.14-10110.23"
-  wire width 25 $memrd$\storage_2$ls180.v:10110$2724_DATA
-  attribute \src "ls180.v:10117.68-10117.77"
-  wire width 25 $memrd$\storage_2$ls180.v:10117$2726_DATA
-  attribute \src "ls180.v:10124.14-10124.23"
-  wire width 25 $memrd$\storage_3$ls180.v:10124$2731_DATA
-  attribute \src "ls180.v:10131.68-10131.77"
-  wire width 25 $memrd$\storage_3$ls180.v:10131$2733_DATA
-  attribute \src "ls180.v:10139.14-10139.23"
-  wire width 10 $memrd$\storage_4$ls180.v:10139$2738_DATA
-  attribute \src "ls180.v:10144.15-10144.24"
-  wire width 10 $memrd$\storage_4$ls180.v:10144$2740_DATA
-  attribute \src "ls180.v:10156.14-10156.23"
-  wire width 10 $memrd$\storage_5$ls180.v:10156$2745_DATA
-  attribute \src "ls180.v:10161.15-10161.24"
-  wire width 10 $memrd$\storage_5$ls180.v:10161$2747_DATA
-  attribute \src "ls180.v:10172.14-10172.23"
-  wire width 10 $memrd$\storage_6$ls180.v:10172$2752_DATA
-  attribute \src "ls180.v:10179.45-10179.54"
-  wire width 10 $memrd$\storage_6$ls180.v:10179$2754_DATA
-  attribute \src "ls180.v:10186.14-10186.23"
-  wire width 10 $memrd$\storage_7$ls180.v:10186$2759_DATA
-  attribute \src "ls180.v:10193.45-10193.54"
-  wire width 10 $memrd$\storage_7$ls180.v:10193$2761_DATA
+  attribute \src "ls180.v:8164.8-8164.43"
+  wire $lt$ls180.v:8164$2584_Y
+  attribute \src "ls180.v:8178.8-8178.43"
+  wire $lt$ls180.v:8178$2588_Y
+  attribute \src "ls180.v:10059.33-10059.36"
+  wire width 32 $memrd$\mem$ls180.v:10059$2693_DATA
+  attribute \src "ls180.v:10070.12-10070.19"
+  wire width 25 $memrd$\storage$ls180.v:10070$2698_DATA
+  attribute \src "ls180.v:10077.68-10077.75"
+  wire width 25 $memrd$\storage$ls180.v:10077$2700_DATA
+  attribute \src "ls180.v:10084.14-10084.23"
+  wire width 25 $memrd$\storage_1$ls180.v:10084$2705_DATA
+  attribute \src "ls180.v:10091.68-10091.77"
+  wire width 25 $memrd$\storage_1$ls180.v:10091$2707_DATA
+  attribute \src "ls180.v:10098.14-10098.23"
+  wire width 25 $memrd$\storage_2$ls180.v:10098$2712_DATA
+  attribute \src "ls180.v:10105.68-10105.77"
+  wire width 25 $memrd$\storage_2$ls180.v:10105$2714_DATA
+  attribute \src "ls180.v:10112.14-10112.23"
+  wire width 25 $memrd$\storage_3$ls180.v:10112$2719_DATA
+  attribute \src "ls180.v:10119.68-10119.77"
+  wire width 25 $memrd$\storage_3$ls180.v:10119$2721_DATA
+  attribute \src "ls180.v:10127.14-10127.23"
+  wire width 10 $memrd$\storage_4$ls180.v:10127$2726_DATA
+  attribute \src "ls180.v:10132.15-10132.24"
+  wire width 10 $memrd$\storage_4$ls180.v:10132$2728_DATA
+  attribute \src "ls180.v:10144.14-10144.23"
+  wire width 10 $memrd$\storage_5$ls180.v:10144$2733_DATA
+  attribute \src "ls180.v:10149.15-10149.24"
+  wire width 10 $memrd$\storage_5$ls180.v:10149$2735_DATA
+  attribute \src "ls180.v:10160.14-10160.23"
+  wire width 10 $memrd$\storage_6$ls180.v:10160$2740_DATA
+  attribute \src "ls180.v:10167.45-10167.54"
+  wire width 10 $memrd$\storage_6$ls180.v:10167$2742_DATA
+  attribute \src "ls180.v:10174.14-10174.23"
+  wire width 10 $memrd$\storage_7$ls180.v:10174$2747_DATA
+  attribute \src "ls180.v:10181.45-10181.54"
+  wire width 10 $memrd$\storage_7$ls180.v:10181$2749_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 7 $memwr$\mem$ls180.v:10061$1_ADDR
+  wire width 7 $memwr$\mem$ls180.v:10049$1_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10061$1_DATA
+  wire width 32 $memwr$\mem$ls180.v:10049$1_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10061$1_EN
+  wire width 32 $memwr$\mem$ls180.v:10049$1_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 7 $memwr$\mem$ls180.v:10063$2_ADDR
+  wire width 7 $memwr$\mem$ls180.v:10051$2_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10063$2_DATA
+  wire width 32 $memwr$\mem$ls180.v:10051$2_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10063$2_EN
+  wire width 32 $memwr$\mem$ls180.v:10051$2_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 7 $memwr$\mem$ls180.v:10065$3_ADDR
+  wire width 7 $memwr$\mem$ls180.v:10053$3_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10065$3_DATA
+  wire width 32 $memwr$\mem$ls180.v:10053$3_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10065$3_EN
+  wire width 32 $memwr$\mem$ls180.v:10053$3_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 7 $memwr$\mem$ls180.v:10067$4_ADDR
+  wire width 7 $memwr$\mem$ls180.v:10055$4_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10067$4_DATA
+  wire width 32 $memwr$\mem$ls180.v:10055$4_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 32 $memwr$\mem$ls180.v:10067$4_EN
+  wire width 32 $memwr$\mem$ls180.v:10055$4_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 3 $memwr$\storage$ls180.v:10081$5_ADDR
+  wire width 3 $memwr$\storage$ls180.v:10069$5_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage$ls180.v:10081$5_DATA
+  wire width 25 $memwr$\storage$ls180.v:10069$5_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage$ls180.v:10081$5_EN
+  wire width 25 $memwr$\storage$ls180.v:10069$5_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 3 $memwr$\storage_1$ls180.v:10095$6_ADDR
+  wire width 3 $memwr$\storage_1$ls180.v:10083$6_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_1$ls180.v:10095$6_DATA
+  wire width 25 $memwr$\storage_1$ls180.v:10083$6_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_1$ls180.v:10095$6_EN
+  wire width 25 $memwr$\storage_1$ls180.v:10083$6_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 3 $memwr$\storage_2$ls180.v:10109$7_ADDR
+  wire width 3 $memwr$\storage_2$ls180.v:10097$7_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_2$ls180.v:10109$7_DATA
+  wire width 25 $memwr$\storage_2$ls180.v:10097$7_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_2$ls180.v:10109$7_EN
+  wire width 25 $memwr$\storage_2$ls180.v:10097$7_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 3 $memwr$\storage_3$ls180.v:10123$8_ADDR
+  wire width 3 $memwr$\storage_3$ls180.v:10111$8_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_3$ls180.v:10123$8_DATA
+  wire width 25 $memwr$\storage_3$ls180.v:10111$8_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_3$ls180.v:10123$8_EN
+  wire width 25 $memwr$\storage_3$ls180.v:10111$8_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\storage_4$ls180.v:10138$9_ADDR
+  wire width 4 $memwr$\storage_4$ls180.v:10126$9_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_4$ls180.v:10138$9_DATA
+  wire width 10 $memwr$\storage_4$ls180.v:10126$9_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_4$ls180.v:10138$9_EN
+  wire width 10 $memwr$\storage_4$ls180.v:10126$9_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\storage_5$ls180.v:10155$10_ADDR
+  wire width 4 $memwr$\storage_5$ls180.v:10143$10_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_5$ls180.v:10155$10_DATA
+  wire width 10 $memwr$\storage_5$ls180.v:10143$10_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_5$ls180.v:10155$10_EN
+  wire width 10 $memwr$\storage_5$ls180.v:10143$10_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 5 $memwr$\storage_6$ls180.v:10171$11_ADDR
+  wire width 5 $memwr$\storage_6$ls180.v:10159$11_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_6$ls180.v:10171$11_DATA
+  wire width 10 $memwr$\storage_6$ls180.v:10159$11_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_6$ls180.v:10171$11_EN
+  wire width 10 $memwr$\storage_6$ls180.v:10159$11_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 5 $memwr$\storage_7$ls180.v:10185$12_ADDR
+  wire width 5 $memwr$\storage_7$ls180.v:10173$12_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_7$ls180.v:10185$12_DATA
+  wire width 10 $memwr$\storage_7$ls180.v:10173$12_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_7$ls180.v:10185$12_EN
+  wire width 10 $memwr$\storage_7$ls180.v:10173$12_EN
   attribute \src "ls180.v:2969.41-2969.71"
   wire $ne$ls180.v:2969$60_Y
   attribute \src "ls180.v:3130.70-3130.104"
@@ -79267,14 +79267,14 @@ module \ls180
   wire $ne$ls180.v:5648$1024_Y
   attribute \src "ls180.v:5679.79-5679.119"
   wire $ne$ls180.v:5679$1027_Y
-  attribute \src "ls180.v:7501.7-7501.52"
-  wire $ne$ls180.v:7501$2414_Y
-  attribute \src "ls180.v:7551.9-7551.43"
-  wire $ne$ls180.v:7551$2428_Y
-  attribute \src "ls180.v:7587.8-7587.44"
-  wire $ne$ls180.v:7587$2435_Y
-  attribute \src "ls180.v:8525.9-8525.47"
-  wire $ne$ls180.v:8525$2650_Y
+  attribute \src "ls180.v:7489.7-7489.52"
+  wire $ne$ls180.v:7489$2402_Y
+  attribute \src "ls180.v:7539.9-7539.43"
+  wire $ne$ls180.v:7539$2416_Y
+  attribute \src "ls180.v:7575.8-7575.44"
+  wire $ne$ls180.v:7575$2423_Y
+  attribute \src "ls180.v:8513.9-8513.47"
+  wire $ne$ls180.v:8513$2638_Y
   attribute \src "ls180.v:2777.45-2777.80"
   wire $not$ls180.v:2777$14_Y
   attribute \src "ls180.v:2816.61-2816.94"
@@ -79821,136 +79821,136 @@ module \ls180
   wire $not$ls180.v:6918$2319_Y
   attribute \src "ls180.v:7416.18-7416.42"
   wire $not$ls180.v:7416$2372_Y
-  attribute \src "ls180.v:7507.72-7507.101"
-  wire $not$ls180.v:7507$2417_Y
-  attribute \src "ls180.v:7526.8-7526.38"
-  wire $not$ls180.v:7526$2421_Y
-  attribute \src "ls180.v:7534.32-7534.55"
-  wire $not$ls180.v:7534$2423_Y
-  attribute \src "ls180.v:7604.136-7604.189"
-  wire $not$ls180.v:7604$2438_Y
-  attribute \src "ls180.v:7610.136-7610.189"
-  wire $not$ls180.v:7610$2443_Y
-  attribute \src "ls180.v:7611.8-7611.61"
-  wire $not$ls180.v:7611$2445_Y
-  attribute \src "ls180.v:7619.8-7619.56"
-  wire $not$ls180.v:7619$2448_Y
-  attribute \src "ls180.v:7634.8-7634.46"
-  wire $not$ls180.v:7634$2450_Y
-  attribute \src "ls180.v:7650.136-7650.189"
-  wire $not$ls180.v:7650$2454_Y
-  attribute \src "ls180.v:7656.136-7656.189"
-  wire $not$ls180.v:7656$2459_Y
-  attribute \src "ls180.v:7657.8-7657.61"
-  wire $not$ls180.v:7657$2461_Y
-  attribute \src "ls180.v:7665.8-7665.56"
-  wire $not$ls180.v:7665$2464_Y
-  attribute \src "ls180.v:7680.8-7680.46"
-  wire $not$ls180.v:7680$2466_Y
-  attribute \src "ls180.v:7696.136-7696.189"
-  wire $not$ls180.v:7696$2470_Y
-  attribute \src "ls180.v:7702.136-7702.189"
-  wire $not$ls180.v:7702$2475_Y
-  attribute \src "ls180.v:7703.8-7703.61"
-  wire $not$ls180.v:7703$2477_Y
-  attribute \src "ls180.v:7711.8-7711.56"
-  wire $not$ls180.v:7711$2480_Y
-  attribute \src "ls180.v:7726.8-7726.46"
-  wire $not$ls180.v:7726$2482_Y
-  attribute \src "ls180.v:7742.136-7742.189"
-  wire $not$ls180.v:7742$2486_Y
-  attribute \src "ls180.v:7748.136-7748.189"
-  wire $not$ls180.v:7748$2491_Y
-  attribute \src "ls180.v:7749.8-7749.61"
-  wire $not$ls180.v:7749$2493_Y
-  attribute \src "ls180.v:7757.8-7757.56"
-  wire $not$ls180.v:7757$2496_Y
-  attribute \src "ls180.v:7772.8-7772.46"
-  wire $not$ls180.v:7772$2498_Y
-  attribute \src "ls180.v:7780.7-7780.22"
-  wire $not$ls180.v:7780$2501_Y
-  attribute \src "ls180.v:7783.8-7783.29"
-  wire $not$ls180.v:7783$2502_Y
-  attribute \src "ls180.v:7787.7-7787.22"
-  wire $not$ls180.v:7787$2504_Y
-  attribute \src "ls180.v:7790.8-7790.29"
-  wire $not$ls180.v:7790$2505_Y
-  attribute \src "ls180.v:7909.30-7909.60"
-  wire $not$ls180.v:7909$2507_Y
-  attribute \src "ls180.v:7910.30-7910.60"
-  wire $not$ls180.v:7910$2508_Y
-  attribute \src "ls180.v:7911.29-7911.59"
-  wire $not$ls180.v:7911$2509_Y
-  attribute \src "ls180.v:7922.8-7922.33"
-  wire $not$ls180.v:7922$2510_Y
-  attribute \src "ls180.v:7937.8-7937.33"
-  wire $not$ls180.v:7937$2513_Y
-  attribute \src "ls180.v:7973.36-7973.58"
-  wire $not$ls180.v:7973$2543_Y
-  attribute \src "ls180.v:7973.64-7973.89"
-  wire $not$ls180.v:7973$2545_Y
-  attribute \src "ls180.v:8002.7-8002.29"
-  wire $not$ls180.v:8002$2552_Y
-  attribute \src "ls180.v:8003.9-8003.26"
-  wire $not$ls180.v:8003$2553_Y
-  attribute \src "ls180.v:8036.8-8036.29"
-  wire $not$ls180.v:8036$2559_Y
-  attribute \src "ls180.v:8043.8-8043.29"
-  wire $not$ls180.v:8043$2561_Y
-  attribute \src "ls180.v:8053.80-8053.106"
-  wire $not$ls180.v:8053$2564_Y
-  attribute \src "ls180.v:8059.80-8059.106"
-  wire $not$ls180.v:8059$2569_Y
-  attribute \src "ls180.v:8060.8-8060.34"
-  wire $not$ls180.v:8060$2571_Y
-  attribute \src "ls180.v:8075.80-8075.106"
-  wire $not$ls180.v:8075$2575_Y
-  attribute \src "ls180.v:8081.80-8081.106"
-  wire $not$ls180.v:8081$2580_Y
-  attribute \src "ls180.v:8082.8-8082.34"
-  wire $not$ls180.v:8082$2582_Y
-  attribute \src "ls180.v:8113.22-8113.41"
-  wire $not$ls180.v:8113$2586_Y
-  attribute \src "ls180.v:8113.46-8113.73"
-  wire $not$ls180.v:8113$2587_Y
-  attribute \src "ls180.v:8148.22-8148.40"
-  wire $not$ls180.v:8148$2591_Y
-  attribute \src "ls180.v:8148.45-8148.70"
-  wire $not$ls180.v:8148$2592_Y
-  attribute \src "ls180.v:8202.7-8202.31"
-  wire $not$ls180.v:8202$2603_Y
-  attribute \src "ls180.v:8274.8-8274.46"
-  wire $not$ls180.v:8274$2615_Y
-  attribute \src "ls180.v:8355.8-8355.47"
-  wire $not$ls180.v:8355$2627_Y
-  attribute \src "ls180.v:8416.8-8416.48"
-  wire $not$ls180.v:8416$2639_Y
-  attribute \src "ls180.v:8586.88-8586.118"
-  wire $not$ls180.v:8586$2653_Y
-  attribute \src "ls180.v:8592.88-8592.118"
-  wire $not$ls180.v:8592$2658_Y
-  attribute \src "ls180.v:8593.8-8593.38"
-  wire $not$ls180.v:8593$2660_Y
-  attribute \src "ls180.v:8672.88-8672.118"
-  wire $not$ls180.v:8672$2675_Y
-  attribute \src "ls180.v:8678.88-8678.118"
-  wire $not$ls180.v:8678$2680_Y
-  attribute \src "ls180.v:8679.8-8679.38"
-  wire $not$ls180.v:8679$2682_Y
-  attribute \src "ls180.v:8699.9-8699.28"
-  wire $not$ls180.v:8699$2685_Y
-  attribute \src "ls180.v:8718.9-8718.28"
-  wire $not$ls180.v:8718$2686_Y
-  attribute \src "ls180.v:8737.9-8737.28"
-  wire $not$ls180.v:8737$2687_Y
-  attribute \src "ls180.v:8756.9-8756.28"
-  wire $not$ls180.v:8756$2688_Y
-  attribute \src "ls180.v:8775.9-8775.28"
-  wire $not$ls180.v:8775$2689_Y
-  attribute \src "ls180.v:8796.8-8796.21"
-  wire $not$ls180.v:8796$2690_Y
-  attribute \src "ls180.v:10295.8-10295.51"
-  wire $or$ls180.v:10295$2762_Y
+  attribute \src "ls180.v:7495.72-7495.101"
+  wire $not$ls180.v:7495$2405_Y
+  attribute \src "ls180.v:7514.8-7514.38"
+  wire $not$ls180.v:7514$2409_Y
+  attribute \src "ls180.v:7522.32-7522.55"
+  wire $not$ls180.v:7522$2411_Y
+  attribute \src "ls180.v:7592.136-7592.189"
+  wire $not$ls180.v:7592$2426_Y
+  attribute \src "ls180.v:7598.136-7598.189"
+  wire $not$ls180.v:7598$2431_Y
+  attribute \src "ls180.v:7599.8-7599.61"
+  wire $not$ls180.v:7599$2433_Y
+  attribute \src "ls180.v:7607.8-7607.56"
+  wire $not$ls180.v:7607$2436_Y
+  attribute \src "ls180.v:7622.8-7622.46"
+  wire $not$ls180.v:7622$2438_Y
+  attribute \src "ls180.v:7638.136-7638.189"
+  wire $not$ls180.v:7638$2442_Y
+  attribute \src "ls180.v:7644.136-7644.189"
+  wire $not$ls180.v:7644$2447_Y
+  attribute \src "ls180.v:7645.8-7645.61"
+  wire $not$ls180.v:7645$2449_Y
+  attribute \src "ls180.v:7653.8-7653.56"
+  wire $not$ls180.v:7653$2452_Y
+  attribute \src "ls180.v:7668.8-7668.46"
+  wire $not$ls180.v:7668$2454_Y
+  attribute \src "ls180.v:7684.136-7684.189"
+  wire $not$ls180.v:7684$2458_Y
+  attribute \src "ls180.v:7690.136-7690.189"
+  wire $not$ls180.v:7690$2463_Y
+  attribute \src "ls180.v:7691.8-7691.61"
+  wire $not$ls180.v:7691$2465_Y
+  attribute \src "ls180.v:7699.8-7699.56"
+  wire $not$ls180.v:7699$2468_Y
+  attribute \src "ls180.v:7714.8-7714.46"
+  wire $not$ls180.v:7714$2470_Y
+  attribute \src "ls180.v:7730.136-7730.189"
+  wire $not$ls180.v:7730$2474_Y
+  attribute \src "ls180.v:7736.136-7736.189"
+  wire $not$ls180.v:7736$2479_Y
+  attribute \src "ls180.v:7737.8-7737.61"
+  wire $not$ls180.v:7737$2481_Y
+  attribute \src "ls180.v:7745.8-7745.56"
+  wire $not$ls180.v:7745$2484_Y
+  attribute \src "ls180.v:7760.8-7760.46"
+  wire $not$ls180.v:7760$2486_Y
+  attribute \src "ls180.v:7768.7-7768.22"
+  wire $not$ls180.v:7768$2489_Y
+  attribute \src "ls180.v:7771.8-7771.29"
+  wire $not$ls180.v:7771$2490_Y
+  attribute \src "ls180.v:7775.7-7775.22"
+  wire $not$ls180.v:7775$2492_Y
+  attribute \src "ls180.v:7778.8-7778.29"
+  wire $not$ls180.v:7778$2493_Y
+  attribute \src "ls180.v:7897.30-7897.60"
+  wire $not$ls180.v:7897$2495_Y
+  attribute \src "ls180.v:7898.30-7898.60"
+  wire $not$ls180.v:7898$2496_Y
+  attribute \src "ls180.v:7899.29-7899.59"
+  wire $not$ls180.v:7899$2497_Y
+  attribute \src "ls180.v:7910.8-7910.33"
+  wire $not$ls180.v:7910$2498_Y
+  attribute \src "ls180.v:7925.8-7925.33"
+  wire $not$ls180.v:7925$2501_Y
+  attribute \src "ls180.v:7961.36-7961.58"
+  wire $not$ls180.v:7961$2531_Y
+  attribute \src "ls180.v:7961.64-7961.89"
+  wire $not$ls180.v:7961$2533_Y
+  attribute \src "ls180.v:7990.7-7990.29"
+  wire $not$ls180.v:7990$2540_Y
+  attribute \src "ls180.v:7991.9-7991.26"
+  wire $not$ls180.v:7991$2541_Y
+  attribute \src "ls180.v:8024.8-8024.29"
+  wire $not$ls180.v:8024$2547_Y
+  attribute \src "ls180.v:8031.8-8031.29"
+  wire $not$ls180.v:8031$2549_Y
+  attribute \src "ls180.v:8041.80-8041.106"
+  wire $not$ls180.v:8041$2552_Y
+  attribute \src "ls180.v:8047.80-8047.106"
+  wire $not$ls180.v:8047$2557_Y
+  attribute \src "ls180.v:8048.8-8048.34"
+  wire $not$ls180.v:8048$2559_Y
+  attribute \src "ls180.v:8063.80-8063.106"
+  wire $not$ls180.v:8063$2563_Y
+  attribute \src "ls180.v:8069.80-8069.106"
+  wire $not$ls180.v:8069$2568_Y
+  attribute \src "ls180.v:8070.8-8070.34"
+  wire $not$ls180.v:8070$2570_Y
+  attribute \src "ls180.v:8101.22-8101.41"
+  wire $not$ls180.v:8101$2574_Y
+  attribute \src "ls180.v:8101.46-8101.73"
+  wire $not$ls180.v:8101$2575_Y
+  attribute \src "ls180.v:8136.22-8136.40"
+  wire $not$ls180.v:8136$2579_Y
+  attribute \src "ls180.v:8136.45-8136.70"
+  wire $not$ls180.v:8136$2580_Y
+  attribute \src "ls180.v:8190.7-8190.31"
+  wire $not$ls180.v:8190$2591_Y
+  attribute \src "ls180.v:8262.8-8262.46"
+  wire $not$ls180.v:8262$2603_Y
+  attribute \src "ls180.v:8343.8-8343.47"
+  wire $not$ls180.v:8343$2615_Y
+  attribute \src "ls180.v:8404.8-8404.48"
+  wire $not$ls180.v:8404$2627_Y
+  attribute \src "ls180.v:8574.88-8574.118"
+  wire $not$ls180.v:8574$2641_Y
+  attribute \src "ls180.v:8580.88-8580.118"
+  wire $not$ls180.v:8580$2646_Y
+  attribute \src "ls180.v:8581.8-8581.38"
+  wire $not$ls180.v:8581$2648_Y
+  attribute \src "ls180.v:8660.88-8660.118"
+  wire $not$ls180.v:8660$2663_Y
+  attribute \src "ls180.v:8666.88-8666.118"
+  wire $not$ls180.v:8666$2668_Y
+  attribute \src "ls180.v:8667.8-8667.38"
+  wire $not$ls180.v:8667$2670_Y
+  attribute \src "ls180.v:8687.9-8687.28"
+  wire $not$ls180.v:8687$2673_Y
+  attribute \src "ls180.v:8706.9-8706.28"
+  wire $not$ls180.v:8706$2674_Y
+  attribute \src "ls180.v:8725.9-8725.28"
+  wire $not$ls180.v:8725$2675_Y
+  attribute \src "ls180.v:8744.9-8744.28"
+  wire $not$ls180.v:8744$2676_Y
+  attribute \src "ls180.v:8763.9-8763.28"
+  wire $not$ls180.v:8763$2677_Y
+  attribute \src "ls180.v:8784.8-8784.21"
+  wire $not$ls180.v:8784$2678_Y
+  attribute \src "ls180.v:10283.8-10283.51"
+  wire $or$ls180.v:10283$2750_Y
   attribute \src "ls180.v:2818.10-2818.96"
   wire $or$ls180.v:2818$21_Y
   attribute \src "ls180.v:2878.10-2878.96"
@@ -80323,102 +80323,78 @@ module \ls180
   wire $or$ls180.v:7454$2397_Y
   attribute \src "ls180.v:7455.21-7455.73"
   wire $or$ls180.v:7455$2398_Y
-  attribute \src "ls180.v:7456.21-7456.73"
+  attribute \src "ls180.v:7456.7-7456.93"
   wire $or$ls180.v:7456$2399_Y
-  attribute \src "ls180.v:7457.21-7457.73"
-  wire $or$ls180.v:7457$2400_Y
-  attribute \src "ls180.v:7458.21-7458.73"
-  wire $or$ls180.v:7458$2401_Y
-  attribute \src "ls180.v:7459.21-7459.73"
-  wire $or$ls180.v:7459$2402_Y
-  attribute \src "ls180.v:7460.21-7460.73"
-  wire $or$ls180.v:7460$2403_Y
-  attribute \src "ls180.v:7461.21-7461.73"
-  wire $or$ls180.v:7461$2404_Y
-  attribute \src "ls180.v:7462.21-7462.73"
-  wire $or$ls180.v:7462$2405_Y
-  attribute \src "ls180.v:7463.21-7463.73"
-  wire $or$ls180.v:7463$2406_Y
-  attribute \src "ls180.v:7464.21-7464.73"
-  wire $or$ls180.v:7464$2407_Y
-  attribute \src "ls180.v:7465.21-7465.73"
-  wire $or$ls180.v:7465$2408_Y
-  attribute \src "ls180.v:7466.21-7466.73"
-  wire $or$ls180.v:7466$2409_Y
-  attribute \src "ls180.v:7467.21-7467.73"
-  wire $or$ls180.v:7467$2410_Y
-  attribute \src "ls180.v:7468.7-7468.93"
-  wire $or$ls180.v:7468$2411_Y
-  attribute \src "ls180.v:7479.7-7479.93"
-  wire $or$ls180.v:7479$2412_Y
-  attribute \src "ls180.v:7490.7-7490.93"
-  wire $or$ls180.v:7490$2413_Y
-  attribute \src "ls180.v:7619.7-7619.107"
-  wire $or$ls180.v:7619$2449_Y
-  attribute \src "ls180.v:7665.7-7665.107"
-  wire $or$ls180.v:7665$2465_Y
-  attribute \src "ls180.v:7711.7-7711.107"
-  wire $or$ls180.v:7711$2481_Y
-  attribute \src "ls180.v:7757.7-7757.107"
-  wire $or$ls180.v:7757$2497_Y
-  attribute \src "ls180.v:7945.40-7945.125"
-  wire $or$ls180.v:7945$2518_Y
-  attribute \src "ls180.v:7945.39-7945.207"
-  wire $or$ls180.v:7945$2521_Y
-  attribute \src "ls180.v:7945.38-7945.289"
-  wire $or$ls180.v:7945$2524_Y
-  attribute \src "ls180.v:7945.37-7945.371"
-  wire $or$ls180.v:7945$2527_Y
-  attribute \src "ls180.v:7946.41-7946.126"
-  wire $or$ls180.v:7946$2530_Y
-  attribute \src "ls180.v:7946.40-7946.208"
-  wire $or$ls180.v:7946$2533_Y
-  attribute \src "ls180.v:7946.39-7946.290"
-  wire $or$ls180.v:7946$2536_Y
-  attribute \src "ls180.v:7946.38-7946.372"
-  wire $or$ls180.v:7946$2539_Y
-  attribute \src "ls180.v:7950.7-7950.49"
-  wire $or$ls180.v:7950$2540_Y
-  attribute \src "ls180.v:8113.21-8113.74"
-  wire $or$ls180.v:8113$2588_Y
-  attribute \src "ls180.v:8148.21-8148.71"
-  wire $or$ls180.v:8148$2593_Y
-  attribute \src "ls180.v:8216.32-8216.85"
-  wire $or$ls180.v:8216$2605_Y
-  attribute \src "ls180.v:8222.8-8222.97"
-  wire $or$ls180.v:8222$2607_Y
-  attribute \src "ls180.v:8239.52-8239.139"
-  wire $or$ls180.v:8239$2612_Y
-  attribute \src "ls180.v:8240.51-8240.136"
-  wire $or$ls180.v:8240$2613_Y
-  attribute \src "ls180.v:8274.7-8274.87"
-  wire $or$ls180.v:8274$2616_Y
-  attribute \src "ls180.v:8297.33-8297.88"
-  wire $or$ls180.v:8297$2617_Y
-  attribute \src "ls180.v:8303.8-8303.99"
-  wire $or$ls180.v:8303$2619_Y
-  attribute \src "ls180.v:8320.53-8320.142"
-  wire $or$ls180.v:8320$2624_Y
-  attribute \src "ls180.v:8321.52-8321.139"
-  wire $or$ls180.v:8321$2625_Y
-  attribute \src "ls180.v:8355.7-8355.89"
-  wire $or$ls180.v:8355$2628_Y
-  attribute \src "ls180.v:8376.34-8376.91"
-  wire $or$ls180.v:8376$2629_Y
-  attribute \src "ls180.v:8382.8-8382.101"
-  wire $or$ls180.v:8382$2631_Y
-  attribute \src "ls180.v:8399.54-8399.145"
-  wire $or$ls180.v:8399$2636_Y
-  attribute \src "ls180.v:8400.53-8400.142"
-  wire $or$ls180.v:8400$2637_Y
-  attribute \src "ls180.v:8416.7-8416.91"
-  wire $or$ls180.v:8416$2640_Y
-  attribute \src "ls180.v:8605.8-8605.89"
-  wire $or$ls180.v:8605$2664_Y
-  attribute \src "ls180.v:8622.48-8622.127"
-  wire $or$ls180.v:8622$2669_Y
-  attribute \src "ls180.v:8623.47-8623.124"
-  wire $or$ls180.v:8623$2670_Y
+  attribute \src "ls180.v:7467.7-7467.93"
+  wire $or$ls180.v:7467$2400_Y
+  attribute \src "ls180.v:7478.7-7478.93"
+  wire $or$ls180.v:7478$2401_Y
+  attribute \src "ls180.v:7607.7-7607.107"
+  wire $or$ls180.v:7607$2437_Y
+  attribute \src "ls180.v:7653.7-7653.107"
+  wire $or$ls180.v:7653$2453_Y
+  attribute \src "ls180.v:7699.7-7699.107"
+  wire $or$ls180.v:7699$2469_Y
+  attribute \src "ls180.v:7745.7-7745.107"
+  wire $or$ls180.v:7745$2485_Y
+  attribute \src "ls180.v:7933.40-7933.125"
+  wire $or$ls180.v:7933$2506_Y
+  attribute \src "ls180.v:7933.39-7933.207"
+  wire $or$ls180.v:7933$2509_Y
+  attribute \src "ls180.v:7933.38-7933.289"
+  wire $or$ls180.v:7933$2512_Y
+  attribute \src "ls180.v:7933.37-7933.371"
+  wire $or$ls180.v:7933$2515_Y
+  attribute \src "ls180.v:7934.41-7934.126"
+  wire $or$ls180.v:7934$2518_Y
+  attribute \src "ls180.v:7934.40-7934.208"
+  wire $or$ls180.v:7934$2521_Y
+  attribute \src "ls180.v:7934.39-7934.290"
+  wire $or$ls180.v:7934$2524_Y
+  attribute \src "ls180.v:7934.38-7934.372"
+  wire $or$ls180.v:7934$2527_Y
+  attribute \src "ls180.v:7938.7-7938.49"
+  wire $or$ls180.v:7938$2528_Y
+  attribute \src "ls180.v:8101.21-8101.74"
+  wire $or$ls180.v:8101$2576_Y
+  attribute \src "ls180.v:8136.21-8136.71"
+  wire $or$ls180.v:8136$2581_Y
+  attribute \src "ls180.v:8204.32-8204.85"
+  wire $or$ls180.v:8204$2593_Y
+  attribute \src "ls180.v:8210.8-8210.97"
+  wire $or$ls180.v:8210$2595_Y
+  attribute \src "ls180.v:8227.52-8227.139"
+  wire $or$ls180.v:8227$2600_Y
+  attribute \src "ls180.v:8228.51-8228.136"
+  wire $or$ls180.v:8228$2601_Y
+  attribute \src "ls180.v:8262.7-8262.87"
+  wire $or$ls180.v:8262$2604_Y
+  attribute \src "ls180.v:8285.33-8285.88"
+  wire $or$ls180.v:8285$2605_Y
+  attribute \src "ls180.v:8291.8-8291.99"
+  wire $or$ls180.v:8291$2607_Y
+  attribute \src "ls180.v:8308.53-8308.142"
+  wire $or$ls180.v:8308$2612_Y
+  attribute \src "ls180.v:8309.52-8309.139"
+  wire $or$ls180.v:8309$2613_Y
+  attribute \src "ls180.v:8343.7-8343.89"
+  wire $or$ls180.v:8343$2616_Y
+  attribute \src "ls180.v:8364.34-8364.91"
+  wire $or$ls180.v:8364$2617_Y
+  attribute \src "ls180.v:8370.8-8370.101"
+  wire $or$ls180.v:8370$2619_Y
+  attribute \src "ls180.v:8387.54-8387.145"
+  wire $or$ls180.v:8387$2624_Y
+  attribute \src "ls180.v:8388.53-8388.142"
+  wire $or$ls180.v:8388$2625_Y
+  attribute \src "ls180.v:8404.7-8404.91"
+  wire $or$ls180.v:8404$2628_Y
+  attribute \src "ls180.v:8593.8-8593.89"
+  wire $or$ls180.v:8593$2652_Y
+  attribute \src "ls180.v:8610.48-8610.127"
+  wire $or$ls180.v:8610$2657_Y
+  attribute \src "ls180.v:8611.47-8611.124"
+  wire $or$ls180.v:8611$2658_Y
   attribute \src "ls180.v:3182.46-3182.94"
   wire width 13 $sshl$ls180.v:3182$83_Y
   attribute \src "ls180.v:3339.46-3339.94"
@@ -80481,56 +80457,56 @@ module \ls180
   wire width 32 $sub$ls180.v:5568$1008_Y
   attribute \src "ls180.v:5637.40-5637.76"
   wire width 5 $sub$ls180.v:5637$1019_Y
-  attribute \src "ls180.v:7514.31-7514.60"
-  wire width 32 $sub$ls180.v:7514$2420_Y
-  attribute \src "ls180.v:7535.31-7535.61"
-  wire width 10 $sub$ls180.v:7535$2425_Y
-  attribute \src "ls180.v:7541.34-7541.67"
-  wire $sub$ls180.v:7541$2426_Y
-  attribute \src "ls180.v:7552.36-7552.69"
-  wire $sub$ls180.v:7552$2429_Y
-  attribute \src "ls180.v:7616.59-7616.116"
-  wire width 4 $sub$ls180.v:7616$2447_Y
-  attribute \src "ls180.v:7635.46-7635.90"
-  wire width 3 $sub$ls180.v:7635$2451_Y
-  attribute \src "ls180.v:7662.59-7662.116"
-  wire width 4 $sub$ls180.v:7662$2463_Y
-  attribute \src "ls180.v:7681.46-7681.90"
-  wire width 3 $sub$ls180.v:7681$2467_Y
-  attribute \src "ls180.v:7708.59-7708.116"
-  wire width 4 $sub$ls180.v:7708$2479_Y
-  attribute \src "ls180.v:7727.46-7727.90"
-  wire width 3 $sub$ls180.v:7727$2483_Y
-  attribute \src "ls180.v:7754.59-7754.116"
-  wire width 4 $sub$ls180.v:7754$2495_Y
-  attribute \src "ls180.v:7773.46-7773.90"
-  wire width 3 $sub$ls180.v:7773$2499_Y
-  attribute \src "ls180.v:7784.25-7784.48"
-  wire width 5 $sub$ls180.v:7784$2503_Y
-  attribute \src "ls180.v:7791.25-7791.48"
-  wire width 4 $sub$ls180.v:7791$2506_Y
-  attribute \src "ls180.v:7923.33-7923.64"
-  wire $sub$ls180.v:7923$2511_Y
-  attribute \src "ls180.v:7938.33-7938.64"
-  wire width 3 $sub$ls180.v:7938$2514_Y
-  attribute \src "ls180.v:8065.33-8065.64"
-  wire width 5 $sub$ls180.v:8065$2573_Y
-  attribute \src "ls180.v:8087.33-8087.64"
-  wire width 5 $sub$ls180.v:8087$2584_Y
-  attribute \src "ls180.v:8122.34-8122.66"
-  wire width 3 $sub$ls180.v:8122$2589_Y
-  attribute \src "ls180.v:8157.32-8157.62"
-  wire width 3 $sub$ls180.v:8157$2594_Y
-  attribute \src "ls180.v:8181.30-8181.53"
-  wire width 32 $sub$ls180.v:8181$2597_Y
-  attribute \src "ls180.v:8195.30-8195.53"
-  wire width 32 $sub$ls180.v:8195$2601_Y
-  attribute \src "ls180.v:8598.36-8598.70"
-  wire width 6 $sub$ls180.v:8598$2662_Y
-  attribute \src "ls180.v:8684.36-8684.70"
-  wire width 6 $sub$ls180.v:8684$2684_Y
-  attribute \src "ls180.v:8797.22-8797.42"
-  wire width 20 $sub$ls180.v:8797$2691_Y
+  attribute \src "ls180.v:7502.31-7502.60"
+  wire width 32 $sub$ls180.v:7502$2408_Y
+  attribute \src "ls180.v:7523.31-7523.61"
+  wire width 10 $sub$ls180.v:7523$2413_Y
+  attribute \src "ls180.v:7529.34-7529.67"
+  wire $sub$ls180.v:7529$2414_Y
+  attribute \src "ls180.v:7540.36-7540.69"
+  wire $sub$ls180.v:7540$2417_Y
+  attribute \src "ls180.v:7604.59-7604.116"
+  wire width 4 $sub$ls180.v:7604$2435_Y
+  attribute \src "ls180.v:7623.46-7623.90"
+  wire width 3 $sub$ls180.v:7623$2439_Y
+  attribute \src "ls180.v:7650.59-7650.116"
+  wire width 4 $sub$ls180.v:7650$2451_Y
+  attribute \src "ls180.v:7669.46-7669.90"
+  wire width 3 $sub$ls180.v:7669$2455_Y
+  attribute \src "ls180.v:7696.59-7696.116"
+  wire width 4 $sub$ls180.v:7696$2467_Y
+  attribute \src "ls180.v:7715.46-7715.90"
+  wire width 3 $sub$ls180.v:7715$2471_Y
+  attribute \src "ls180.v:7742.59-7742.116"
+  wire width 4 $sub$ls180.v:7742$2483_Y
+  attribute \src "ls180.v:7761.46-7761.90"
+  wire width 3 $sub$ls180.v:7761$2487_Y
+  attribute \src "ls180.v:7772.25-7772.48"
+  wire width 5 $sub$ls180.v:7772$2491_Y
+  attribute \src "ls180.v:7779.25-7779.48"
+  wire width 4 $sub$ls180.v:7779$2494_Y
+  attribute \src "ls180.v:7911.33-7911.64"
+  wire $sub$ls180.v:7911$2499_Y
+  attribute \src "ls180.v:7926.33-7926.64"
+  wire width 3 $sub$ls180.v:7926$2502_Y
+  attribute \src "ls180.v:8053.33-8053.64"
+  wire width 5 $sub$ls180.v:8053$2561_Y
+  attribute \src "ls180.v:8075.33-8075.64"
+  wire width 5 $sub$ls180.v:8075$2572_Y
+  attribute \src "ls180.v:8110.34-8110.66"
+  wire width 3 $sub$ls180.v:8110$2577_Y
+  attribute \src "ls180.v:8145.32-8145.62"
+  wire width 3 $sub$ls180.v:8145$2582_Y
+  attribute \src "ls180.v:8169.30-8169.53"
+  wire width 32 $sub$ls180.v:8169$2585_Y
+  attribute \src "ls180.v:8183.30-8183.53"
+  wire width 32 $sub$ls180.v:8183$2589_Y
+  attribute \src "ls180.v:8586.36-8586.70"
+  wire width 6 $sub$ls180.v:8586$2650_Y
+  attribute \src "ls180.v:8672.36-8672.70"
+  wire width 6 $sub$ls180.v:8672$2672_Y
+  attribute \src "ls180.v:8785.22-8785.42"
+  wire width 20 $sub$ls180.v:8785$2679_Y
   attribute \src "ls180.v:4926.353-4926.425"
   wire $xor$ls180.v:4926$710_Y
   attribute \src "ls180.v:4926.200-4926.272"
@@ -82727,24 +82703,24 @@ module \ls180
   wire \builder_sync_rhs_array_muxed6
   attribute \src "ls180.v:1898.6-1898.18"
   wire \builder_wait
-  attribute \src "ls180.v:35.20-35.24"
-  wire width 3 output 31 \eint
-  attribute \src "ls180.v:154.11-154.17"
+  attribute \src "ls180.v:11.20-11.24"
+  wire width 3 output 7 \eint
+  attribute \src "ls180.v:133.11-133.17"
   wire width 3 \eint_1
-  attribute \src "ls180.v:36.21-36.27"
-  wire width 16 output 32 \gpio_i
-  attribute \src "ls180.v:37.21-37.27"
-  wire width 16 output 33 \gpio_o
-  attribute \src "ls180.v:38.21-38.28"
-  wire width 16 output 34 \gpio_oe
-  attribute \src "ls180.v:5.14-5.21"
-  wire output 1 \i2c_scl
-  attribute \src "ls180.v:6.14-6.23"
-  wire output 2 \i2c_sda_i
-  attribute \src "ls180.v:7.14-7.23"
-  wire output 3 \i2c_sda_o
-  attribute \src "ls180.v:8.14-8.24"
-  wire output 4 \i2c_sda_oe
+  attribute \src "ls180.v:40.21-40.27"
+  wire width 16 output 36 \gpio_i
+  attribute \src "ls180.v:41.21-41.27"
+  wire width 16 output 37 \gpio_o
+  attribute \src "ls180.v:42.21-42.28"
+  wire width 16 output 38 \gpio_oe
+  attribute \src "ls180.v:12.14-12.21"
+  wire output 8 \i2c_scl
+  attribute \src "ls180.v:13.14-13.23"
+  wire output 9 \i2c_sda_i
+  attribute \src "ls180.v:14.14-14.23"
+  wire output 10 \i2c_sda_o
+  attribute \src "ls180.v:15.14-15.24"
+  wire output 11 \i2c_sda_oe
   attribute \src "ls180.v:49.13-49.21"
   wire input 45 \jtag_tck
   attribute \src "ls180.v:50.13-50.21"
@@ -82806,7 +82782,7 @@ module \ls180
   attribute \src "ls180.v:265.12-265.35"
   wire width 2 \main_dfi_p0_wrdata_mask
   attribute \src "ls180.v:1067.12-1067.22"
-  wire width 36 \main_dummy
+  wire width 24 \main_dummy
   attribute \src "ls180.v:984.5-984.20"
   wire \main_gpio_oe_re
   attribute \src "ls180.v:983.12-983.32"
@@ -83037,65 +83013,65 @@ module \ls180
   wire width 64 \main_libresocsim_libresoc2
   attribute \src "ls180.v:127.12-127.45"
   wire width 2 \main_libresocsim_libresoc_clk_sel
-  attribute \src "ls180.v:155.12-155.66"
+  attribute \src "ls180.v:159.12-159.66"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i
-  attribute \src "ls180.v:156.13-156.67"
+  attribute \src "ls180.v:160.13-160.67"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o
-  attribute \src "ls180.v:157.13-157.68"
+  attribute \src "ls180.v:161.13-161.68"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe
-  attribute \src "ls180.v:129.6-129.61"
+  attribute \src "ls180.v:134.6-134.61"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl
-  attribute \src "ls180.v:130.5-130.62"
+  attribute \src "ls180.v:135.5-135.62"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
-  attribute \src "ls180.v:131.6-131.63"
+  attribute \src "ls180.v:136.6-136.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
-  attribute \src "ls180.v:132.6-132.64"
+  attribute \src "ls180.v:137.6-137.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
-  attribute \src "ls180.v:133.6-133.64"
+  attribute \src "ls180.v:143.6-143.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
-  attribute \src "ls180.v:134.5-134.65"
+  attribute \src "ls180.v:144.5-144.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
-  attribute \src "ls180.v:135.6-135.66"
+  attribute \src "ls180.v:145.6-145.66"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
-  attribute \src "ls180.v:136.6-136.67"
+  attribute \src "ls180.v:146.6-146.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
-  attribute \src "ls180.v:142.13-142.68"
+  attribute \src "ls180.v:147.13-147.68"
   wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a
-  attribute \src "ls180.v:151.12-151.68"
+  attribute \src "ls180.v:156.12-156.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba
-  attribute \src "ls180.v:148.6-148.65"
+  attribute \src "ls180.v:153.6-153.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
-  attribute \src "ls180.v:150.6-150.63"
+  attribute \src "ls180.v:155.6-155.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke
-  attribute \src "ls180.v:149.6-149.64"
+  attribute \src "ls180.v:154.6-154.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
-  attribute \src "ls180.v:152.12-152.68"
+  attribute \src "ls180.v:157.12-157.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm
-  attribute \src "ls180.v:143.12-143.70"
+  attribute \src "ls180.v:148.12-148.70"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i
-  attribute \src "ls180.v:144.13-144.71"
+  attribute \src "ls180.v:149.13-149.71"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o
-  attribute \src "ls180.v:145.6-145.65"
+  attribute \src "ls180.v:150.6-150.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
-  attribute \src "ls180.v:147.6-147.65"
+  attribute \src "ls180.v:152.6-152.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
-  attribute \src "ls180.v:146.6-146.64"
+  attribute \src "ls180.v:151.6-151.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
-  attribute \src "ls180.v:138.6-138.67"
+  attribute \src "ls180.v:139.6-139.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk
-  attribute \src "ls180.v:140.6-140.68"
+  attribute \src "ls180.v:141.6-141.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
-  attribute \src "ls180.v:141.5-141.67"
+  attribute \src "ls180.v:142.5-142.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso
-  attribute \src "ls180.v:139.6-139.68"
+  attribute \src "ls180.v:140.6-140.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
-  attribute \src "ls180.v:158.6-158.67"
+  attribute \src "ls180.v:129.6-129.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk
-  attribute \src "ls180.v:160.6-160.68"
+  attribute \src "ls180.v:131.6-131.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n
-  attribute \src "ls180.v:161.5-161.67"
+  attribute \src "ls180.v:132.5-132.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso
-  attribute \src "ls180.v:159.6-159.68"
+  attribute \src "ls180.v:130.6-130.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi
   attribute \src "ls180.v:72.5-72.39"
   wire \main_libresocsim_libresoc_dbus_ack
@@ -83298,7 +83274,7 @@ module \ls180
   attribute \src "ls180.v:831.5-831.24"
   wire \main_litedram_wb_we
   attribute \src "ls180.v:1066.13-1066.20"
-  wire width 36 \main_nc
+  wire width 24 \main_nc
   attribute \src "ls180.v:803.6-803.24"
   wire \main_port_cmd_last
   attribute \src "ls180.v:805.13-805.39"
@@ -86247,76 +86223,76 @@ module \ls180
   wire \main_wb_sdram_we
   attribute \src "ls180.v:837.5-837.24"
   wire \main_wdata_consumed
-  attribute \src "ls180.v:10058.11-10058.17"
+  attribute \src "ls180.v:10046.11-10046.17"
   wire width 7 \memadr
-  attribute \src "ls180.v:10078.12-10078.18"
+  attribute \src "ls180.v:10066.12-10066.18"
   wire width 25 \memdat
-  attribute \src "ls180.v:10092.12-10092.20"
+  attribute \src "ls180.v:10080.12-10080.20"
   wire width 25 \memdat_1
-  attribute \src "ls180.v:10106.12-10106.20"
+  attribute \src "ls180.v:10094.12-10094.20"
   wire width 25 \memdat_2
-  attribute \src "ls180.v:10120.12-10120.20"
+  attribute \src "ls180.v:10108.12-10108.20"
   wire width 25 \memdat_3
-  attribute \src "ls180.v:10134.11-10134.19"
+  attribute \src "ls180.v:10122.11-10122.19"
   wire width 10 \memdat_4
-  attribute \src "ls180.v:10135.11-10135.19"
+  attribute \src "ls180.v:10123.11-10123.19"
   wire width 10 \memdat_5
-  attribute \src "ls180.v:10151.11-10151.19"
+  attribute \src "ls180.v:10139.11-10139.19"
   wire width 10 \memdat_6
-  attribute \src "ls180.v:10152.11-10152.19"
+  attribute \src "ls180.v:10140.11-10140.19"
   wire width 10 \memdat_7
-  attribute \src "ls180.v:10168.11-10168.19"
+  attribute \src "ls180.v:10156.11-10156.19"
   wire width 10 \memdat_8
-  attribute \src "ls180.v:10182.11-10182.19"
+  attribute \src "ls180.v:10170.11-10170.19"
   wire width 10 \memdat_9
   attribute \src "ls180.v:52.20-52.22"
-  wire width 36 input 48 \nc
+  wire width 24 input 48 \nc
   attribute \src "ls180.v:251.6-251.13"
   wire \por_clk
-  attribute \src "ls180.v:18.19-18.22"
-  wire width 2 output 14 \pwm
-  attribute \src "ls180.v:137.12-137.17"
+  attribute \src "ls180.v:16.19-16.22"
+  wire width 2 output 12 \pwm
+  attribute \src "ls180.v:138.12-138.17"
   wire width 2 \pwm_1
-  attribute \src "ls180.v:11.13-11.23"
-  wire output 7 \sdcard_clk
-  attribute \src "ls180.v:12.14-12.26"
-  wire output 8 \sdcard_cmd_i
-  attribute \src "ls180.v:13.13-13.25"
-  wire output 9 \sdcard_cmd_o
-  attribute \src "ls180.v:14.13-14.26"
-  wire output 10 \sdcard_cmd_oe
-  attribute \src "ls180.v:15.19-15.32"
-  wire width 4 input 11 \sdcard_data_i
-  attribute \src "ls180.v:16.19-16.32"
-  wire width 4 output 12 \sdcard_data_o
-  attribute \src "ls180.v:17.13-17.27"
-  wire output 13 \sdcard_data_oe
-  attribute \src "ls180.v:23.20-23.27"
-  wire width 13 output 19 \sdram_a
-  attribute \src "ls180.v:32.19-32.27"
-  wire width 2 output 28 \sdram_ba
-  attribute \src "ls180.v:29.13-29.24"
-  wire output 25 \sdram_cas_n
-  attribute \src "ls180.v:31.13-31.22"
-  wire output 27 \sdram_cke
+  attribute \src "ls180.v:21.13-21.23"
+  wire output 17 \sdcard_clk
+  attribute \src "ls180.v:22.14-22.26"
+  wire output 18 \sdcard_cmd_i
+  attribute \src "ls180.v:23.13-23.25"
+  wire output 19 \sdcard_cmd_o
+  attribute \src "ls180.v:24.13-24.26"
+  wire output 20 \sdcard_cmd_oe
+  attribute \src "ls180.v:25.19-25.32"
+  wire width 4 input 21 \sdcard_data_i
+  attribute \src "ls180.v:26.19-26.32"
+  wire width 4 output 22 \sdcard_data_o
+  attribute \src "ls180.v:27.13-27.27"
+  wire output 23 \sdcard_data_oe
+  attribute \src "ls180.v:28.20-28.27"
+  wire width 13 output 24 \sdram_a
+  attribute \src "ls180.v:37.19-37.27"
+  wire width 2 output 33 \sdram_ba
   attribute \src "ls180.v:34.13-34.24"
-  wire output 30 \sdram_clock
-  attribute \src "ls180.v:153.6-153.19"
+  wire output 30 \sdram_cas_n
+  attribute \src "ls180.v:36.13-36.22"
+  wire output 32 \sdram_cke
+  attribute \src "ls180.v:39.13-39.24"
+  wire output 35 \sdram_clock
+  attribute \src "ls180.v:158.6-158.19"
   wire \sdram_clock_1
-  attribute \src "ls180.v:30.13-30.23"
-  wire output 26 \sdram_cs_n
-  attribute \src "ls180.v:33.19-33.27"
-  wire width 2 output 29 \sdram_dm
-  attribute \src "ls180.v:24.21-24.31"
-  wire width 16 output 20 \sdram_dq_i
-  attribute \src "ls180.v:25.20-25.30"
-  wire width 16 output 21 \sdram_dq_o
-  attribute \src "ls180.v:26.13-26.24"
-  wire output 22 \sdram_dq_oe
-  attribute \src "ls180.v:28.13-28.24"
-  wire output 24 \sdram_ras_n
-  attribute \src "ls180.v:27.13-27.23"
-  wire output 23 \sdram_we_n
+  attribute \src "ls180.v:35.13-35.23"
+  wire output 31 \sdram_cs_n
+  attribute \src "ls180.v:38.19-38.27"
+  wire width 2 output 34 \sdram_dm
+  attribute \src "ls180.v:29.21-29.31"
+  wire width 16 output 25 \sdram_dq_i
+  attribute \src "ls180.v:30.20-30.30"
+  wire width 16 output 26 \sdram_dq_o
+  attribute \src "ls180.v:31.13-31.24"
+  wire output 27 \sdram_dq_oe
+  attribute \src "ls180.v:33.13-33.24"
+  wire output 29 \sdram_ras_n
+  attribute \src "ls180.v:32.13-32.23"
+  wire output 28 \sdram_we_n
   attribute \src "ls180.v:2647.6-2647.15"
   wire \sdrio_clk
   attribute \src "ls180.v:2648.6-2648.17"
@@ -86455,22 +86431,22 @@ module \ls180
   wire \sdrio_clk_8
   attribute \src "ls180.v:2656.6-2656.17"
   wire \sdrio_clk_9
-  attribute \src "ls180.v:19.13-19.26"
-  wire output 15 \spimaster_clk
-  attribute \src "ls180.v:21.13-21.27"
-  wire output 17 \spimaster_cs_n
-  attribute \src "ls180.v:22.14-22.28"
-  wire output 18 \spimaster_miso
-  attribute \src "ls180.v:20.13-20.27"
-  wire output 16 \spimaster_mosi
-  attribute \src "ls180.v:39.13-39.26"
-  wire output 35 \spisdcard_clk
-  attribute \src "ls180.v:41.13-41.27"
-  wire output 37 \spisdcard_cs_n
-  attribute \src "ls180.v:42.14-42.28"
-  wire output 38 \spisdcard_miso
-  attribute \src "ls180.v:40.13-40.27"
-  wire output 36 \spisdcard_mosi
+  attribute \src "ls180.v:17.13-17.26"
+  wire output 13 \spimaster_clk
+  attribute \src "ls180.v:19.13-19.27"
+  wire output 15 \spimaster_cs_n
+  attribute \src "ls180.v:20.14-20.28"
+  wire output 16 \spimaster_miso
+  attribute \src "ls180.v:18.13-18.27"
+  wire output 14 \spimaster_mosi
+  attribute \src "ls180.v:5.13-5.26"
+  wire output 1 \spisdcard_clk
+  attribute \src "ls180.v:7.13-7.27"
+  wire output 3 \spisdcard_cs_n
+  attribute \src "ls180.v:8.14-8.28"
+  wire output 4 \spisdcard_miso
+  attribute \src "ls180.v:6.13-6.27"
+  wire output 2 \spisdcard_mosi
   attribute \src "ls180.v:43.13-43.20"
   wire input 39 \sys_clk
   attribute \src "ls180.v:249.6-249.15"
@@ -86489,23 +86465,23 @@ module \ls180
   wire input 6 \uart_rx
   attribute \src "ls180.v:9.13-9.20"
   wire output 5 \uart_tx
-  attribute \src "ls180.v:10057.12-10057.15"
+  attribute \src "ls180.v:10045.12-10045.15"
   memory width 32 size 128 \mem
-  attribute \src "ls180.v:10077.12-10077.19"
+  attribute \src "ls180.v:10065.12-10065.19"
   memory width 25 size 8 \storage
-  attribute \src "ls180.v:10091.12-10091.21"
+  attribute \src "ls180.v:10079.12-10079.21"
   memory width 25 size 8 \storage_1
-  attribute \src "ls180.v:10105.12-10105.21"
+  attribute \src "ls180.v:10093.12-10093.21"
   memory width 25 size 8 \storage_2
-  attribute \src "ls180.v:10119.12-10119.21"
+  attribute \src "ls180.v:10107.12-10107.21"
   memory width 25 size 8 \storage_3
-  attribute \src "ls180.v:10133.11-10133.20"
+  attribute \src "ls180.v:10121.11-10121.20"
   memory width 10 size 16 \storage_4
-  attribute \src "ls180.v:10150.11-10150.20"
+  attribute \src "ls180.v:10138.11-10138.20"
   memory width 10 size 16 \storage_5
-  attribute \src "ls180.v:10167.11-10167.20"
+  attribute \src "ls180.v:10155.11-10155.20"
   memory width 10 size 32 \storage_6
-  attribute \src "ls180.v:10181.11-10181.20"
+  attribute \src "ls180.v:10169.11-10169.20"
   memory width 10 size 32 \storage_7
   attribute \src "ls180.v:2819.68-2819.110"
   cell $add $add$ls180.v:2819$22
@@ -86782,8 +86758,8 @@ module \ls180
     connect \B 1'1
     connect \Y $add$ls180.v:5571$1011_Y
   end
-  attribute \src "ls180.v:7503.36-7503.70"
-  cell $add $add$ls180.v:7503$2415
+  attribute \src "ls180.v:7491.36-7491.70"
+  cell $add $add$ls180.v:7491$2403
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -86791,10 +86767,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_libresocsim_bus_errors
     connect \B 1'1
-    connect \Y $add$ls180.v:7503$2415_Y
+    connect \Y $add$ls180.v:7491$2403_Y
   end
-  attribute \src "ls180.v:7588.37-7588.72"
-  cell $add $add$ls180.v:7588$2436
+  attribute \src "ls180.v:7576.37-7576.72"
+  cell $add $add$ls180.v:7576$2424
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -86802,10 +86778,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_sequencer_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:7588$2436_Y
+    connect \Y $add$ls180.v:7576$2424_Y
   end
-  attribute \src "ls180.v:7605.60-7605.119"
-  cell $add $add$ls180.v:7605$2440
+  attribute \src "ls180.v:7593.60-7593.119"
+  cell $add $add$ls180.v:7593$2428
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -86813,10 +86789,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:7605$2440_Y
+    connect \Y $add$ls180.v:7593$2428_Y
   end
-  attribute \src "ls180.v:7608.60-7608.119"
-  cell $add $add$ls180.v:7608$2441
+  attribute \src "ls180.v:7596.60-7596.119"
+  cell $add $add$ls180.v:7596$2429
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -86824,10 +86800,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:7608$2441_Y
+    connect \Y $add$ls180.v:7596$2429_Y
   end
-  attribute \src "ls180.v:7612.59-7612.116"
-  cell $add $add$ls180.v:7612$2446
+  attribute \src "ls180.v:7600.59-7600.116"
+  cell $add $add$ls180.v:7600$2434
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -86835,10 +86811,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $add$ls180.v:7612$2446_Y
+    connect \Y $add$ls180.v:7600$2434_Y
   end
-  attribute \src "ls180.v:7651.60-7651.119"
-  cell $add $add$ls180.v:7651$2456
+  attribute \src "ls180.v:7639.60-7639.119"
+  cell $add $add$ls180.v:7639$2444
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -86846,10 +86822,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:7651$2456_Y
+    connect \Y $add$ls180.v:7639$2444_Y
   end
-  attribute \src "ls180.v:7654.60-7654.119"
-  cell $add $add$ls180.v:7654$2457
+  attribute \src "ls180.v:7642.60-7642.119"
+  cell $add $add$ls180.v:7642$2445
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -86857,10 +86833,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:7654$2457_Y
+    connect \Y $add$ls180.v:7642$2445_Y
   end
-  attribute \src "ls180.v:7658.59-7658.116"
-  cell $add $add$ls180.v:7658$2462
+  attribute \src "ls180.v:7646.59-7646.116"
+  cell $add $add$ls180.v:7646$2450
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -86868,10 +86844,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $add$ls180.v:7658$2462_Y
+    connect \Y $add$ls180.v:7646$2450_Y
   end
-  attribute \src "ls180.v:7697.60-7697.119"
-  cell $add $add$ls180.v:7697$2472
+  attribute \src "ls180.v:7685.60-7685.119"
+  cell $add $add$ls180.v:7685$2460
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -86879,10 +86855,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:7697$2472_Y
+    connect \Y $add$ls180.v:7685$2460_Y
   end
-  attribute \src "ls180.v:7700.60-7700.119"
-  cell $add $add$ls180.v:7700$2473
+  attribute \src "ls180.v:7688.60-7688.119"
+  cell $add $add$ls180.v:7688$2461
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -86890,10 +86866,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:7700$2473_Y
+    connect \Y $add$ls180.v:7688$2461_Y
   end
-  attribute \src "ls180.v:7704.59-7704.116"
-  cell $add $add$ls180.v:7704$2478
+  attribute \src "ls180.v:7692.59-7692.116"
+  cell $add $add$ls180.v:7692$2466
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -86901,10 +86877,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $add$ls180.v:7704$2478_Y
+    connect \Y $add$ls180.v:7692$2466_Y
   end
-  attribute \src "ls180.v:7743.60-7743.119"
-  cell $add $add$ls180.v:7743$2488
+  attribute \src "ls180.v:7731.60-7731.119"
+  cell $add $add$ls180.v:7731$2476
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -86912,10 +86888,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:7743$2488_Y
+    connect \Y $add$ls180.v:7731$2476_Y
   end
-  attribute \src "ls180.v:7746.60-7746.119"
-  cell $add $add$ls180.v:7746$2489
+  attribute \src "ls180.v:7734.60-7734.119"
+  cell $add $add$ls180.v:7734$2477
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -86923,10 +86899,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:7746$2489_Y
+    connect \Y $add$ls180.v:7734$2477_Y
   end
-  attribute \src "ls180.v:7750.59-7750.116"
-  cell $add $add$ls180.v:7750$2494
+  attribute \src "ls180.v:7738.59-7738.116"
+  cell $add $add$ls180.v:7738$2482
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -86934,10 +86910,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $add$ls180.v:7750$2494_Y
+    connect \Y $add$ls180.v:7738$2482_Y
   end
-  attribute \src "ls180.v:7980.34-7980.66"
-  cell $add $add$ls180.v:7980$2548
+  attribute \src "ls180.v:7968.34-7968.66"
+  cell $add $add$ls180.v:7968$2536
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -86945,10 +86921,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_phy_tx_bitcount
     connect \B 1'1
-    connect \Y $add$ls180.v:7980$2548_Y
+    connect \Y $add$ls180.v:7968$2536_Y
   end
-  attribute \src "ls180.v:7996.73-7996.131"
-  cell $add $add$ls180.v:7996$2551
+  attribute \src "ls180.v:7984.73-7984.131"
+  cell $add $add$ls180.v:7984$2539
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -86956,10 +86932,10 @@ module \ls180
     parameter \Y_WIDTH 33
     connect \A \main_uart_phy_phase_accumulator_tx
     connect \B \main_uart_phy_storage
-    connect \Y $add$ls180.v:7996$2551_Y
+    connect \Y $add$ls180.v:7984$2539_Y
   end
-  attribute \src "ls180.v:8009.34-8009.66"
-  cell $add $add$ls180.v:8009$2555
+  attribute \src "ls180.v:7997.34-7997.66"
+  cell $add $add$ls180.v:7997$2543
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -86967,10 +86943,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_phy_rx_bitcount
     connect \B 1'1
-    connect \Y $add$ls180.v:8009$2555_Y
+    connect \Y $add$ls180.v:7997$2543_Y
   end
-  attribute \src "ls180.v:8028.73-8028.131"
-  cell $add $add$ls180.v:8028$2558
+  attribute \src "ls180.v:8016.73-8016.131"
+  cell $add $add$ls180.v:8016$2546
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -86978,10 +86954,10 @@ module \ls180
     parameter \Y_WIDTH 33
     connect \A \main_uart_phy_phase_accumulator_rx
     connect \B \main_uart_phy_storage
-    connect \Y $add$ls180.v:8028$2558_Y
+    connect \Y $add$ls180.v:8016$2546_Y
   end
-  attribute \src "ls180.v:8054.33-8054.65"
-  cell $add $add$ls180.v:8054$2566
+  attribute \src "ls180.v:8042.33-8042.65"
+  cell $add $add$ls180.v:8042$2554
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -86989,10 +86965,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_tx_fifo_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:8054$2566_Y
+    connect \Y $add$ls180.v:8042$2554_Y
   end
-  attribute \src "ls180.v:8057.33-8057.65"
-  cell $add $add$ls180.v:8057$2567
+  attribute \src "ls180.v:8045.33-8045.65"
+  cell $add $add$ls180.v:8045$2555
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -87000,10 +86976,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_tx_fifo_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:8057$2567_Y
+    connect \Y $add$ls180.v:8045$2555_Y
   end
-  attribute \src "ls180.v:8061.33-8061.64"
-  cell $add $add$ls180.v:8061$2572
+  attribute \src "ls180.v:8049.33-8049.64"
+  cell $add $add$ls180.v:8049$2560
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -87011,10 +86987,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_uart_tx_fifo_level0
     connect \B 1'1
-    connect \Y $add$ls180.v:8061$2572_Y
+    connect \Y $add$ls180.v:8049$2560_Y
   end
-  attribute \src "ls180.v:8076.33-8076.65"
-  cell $add $add$ls180.v:8076$2577
+  attribute \src "ls180.v:8064.33-8064.65"
+  cell $add $add$ls180.v:8064$2565
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -87022,10 +86998,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_rx_fifo_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:8076$2577_Y
+    connect \Y $add$ls180.v:8064$2565_Y
   end
-  attribute \src "ls180.v:8079.33-8079.65"
-  cell $add $add$ls180.v:8079$2578
+  attribute \src "ls180.v:8067.33-8067.65"
+  cell $add $add$ls180.v:8067$2566
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -87033,10 +87009,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_uart_rx_fifo_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:8079$2578_Y
+    connect \Y $add$ls180.v:8067$2566_Y
   end
-  attribute \src "ls180.v:8083.33-8083.64"
-  cell $add $add$ls180.v:8083$2583
+  attribute \src "ls180.v:8071.33-8071.64"
+  cell $add $add$ls180.v:8071$2571
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -87044,10 +87020,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_uart_rx_fifo_level0
     connect \B 1'1
-    connect \Y $add$ls180.v:8083$2583_Y
+    connect \Y $add$ls180.v:8071$2571_Y
   end
-  attribute \src "ls180.v:8104.35-8104.70"
-  cell $add $add$ls180.v:8104$2585
+  attribute \src "ls180.v:8092.35-8092.70"
+  cell $add $add$ls180.v:8092$2573
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
@@ -87055,10 +87031,10 @@ module \ls180
     parameter \Y_WIDTH 16
     connect \A \main_spimaster30_clk_divider
     connect \B 1'1
-    connect \Y $add$ls180.v:8104$2585_Y
+    connect \Y $add$ls180.v:8092$2573_Y
   end
-  attribute \src "ls180.v:8139.34-8139.68"
-  cell $add $add$ls180.v:8139$2590
+  attribute \src "ls180.v:8127.34-8127.68"
+  cell $add $add$ls180.v:8127$2578
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
@@ -87066,10 +87042,10 @@ module \ls180
     parameter \Y_WIDTH 16
     connect \A \main_spisdcard_clk_divider1
     connect \B 1'1
-    connect \Y $add$ls180.v:8139$2590_Y
+    connect \Y $add$ls180.v:8127$2578_Y
   end
-  attribute \src "ls180.v:8175.25-8175.49"
-  cell $add $add$ls180.v:8175$2595
+  attribute \src "ls180.v:8163.25-8163.49"
+  cell $add $add$ls180.v:8163$2583
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -87077,10 +87053,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_pwm0_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:8175$2595_Y
+    connect \Y $add$ls180.v:8163$2583_Y
   end
-  attribute \src "ls180.v:8189.25-8189.49"
-  cell $add $add$ls180.v:8189$2599
+  attribute \src "ls180.v:8177.25-8177.49"
+  cell $add $add$ls180.v:8177$2587
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -87088,10 +87064,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_pwm1_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:8189$2599_Y
+    connect \Y $add$ls180.v:8177$2587_Y
   end
-  attribute \src "ls180.v:8203.31-8203.61"
-  cell $add $add$ls180.v:8203$2604
+  attribute \src "ls180.v:8191.31-8191.61"
+  cell $add $add$ls180.v:8191$2592
     parameter \A_SIGNED 0
     parameter \A_WIDTH 9
     parameter \B_SIGNED 0
@@ -87099,10 +87075,10 @@ module \ls180
     parameter \Y_WIDTH 9
     connect \A \main_sdphy_clocker_clks
     connect \B 1'1
-    connect \Y $add$ls180.v:8203$2604_Y
+    connect \Y $add$ls180.v:8191$2592_Y
   end
-  attribute \src "ls180.v:8226.45-8226.88"
-  cell $add $add$ls180.v:8226$2608
+  attribute \src "ls180.v:8214.45-8214.88"
+  cell $add $add$ls180.v:8214$2596
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -87110,10 +87086,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdphy_cmdr_cmdr_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8226$2608_Y
+    connect \Y $add$ls180.v:8214$2596_Y
   end
-  attribute \src "ls180.v:8272.71-8272.114"
-  cell $add $add$ls180.v:8272$2614
+  attribute \src "ls180.v:8260.71-8260.114"
+  cell $add $add$ls180.v:8260$2602
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -87121,10 +87097,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdphy_cmdr_cmdr_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8272$2614_Y
+    connect \Y $add$ls180.v:8260$2602_Y
   end
-  attribute \src "ls180.v:8307.46-8307.90"
-  cell $add $add$ls180.v:8307$2620
+  attribute \src "ls180.v:8295.46-8295.90"
+  cell $add $add$ls180.v:8295$2608
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -87132,10 +87108,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdphy_dataw_crcr_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8307$2620_Y
+    connect \Y $add$ls180.v:8295$2608_Y
   end
-  attribute \src "ls180.v:8353.72-8353.116"
-  cell $add $add$ls180.v:8353$2626
+  attribute \src "ls180.v:8341.72-8341.116"
+  cell $add $add$ls180.v:8341$2614
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -87143,10 +87119,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdphy_dataw_crcr_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8353$2626_Y
+    connect \Y $add$ls180.v:8341$2614_Y
   end
-  attribute \src "ls180.v:8386.47-8386.92"
-  cell $add $add$ls180.v:8386$2632
+  attribute \src "ls180.v:8374.47-8374.92"
+  cell $add $add$ls180.v:8374$2620
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -87154,10 +87130,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8386$2632_Y
+    connect \Y $add$ls180.v:8374$2620_Y
   end
-  attribute \src "ls180.v:8414.73-8414.118"
-  cell $add $add$ls180.v:8414$2638
+  attribute \src "ls180.v:8402.73-8402.118"
+  cell $add $add$ls180.v:8402$2626
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -87165,10 +87141,10 @@ module \ls180
     parameter \Y_WIDTH 2
     connect \A \main_sdphy_datar_datar_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8414$2638_Y
+    connect \Y $add$ls180.v:8402$2626_Y
   end
-  attribute \src "ls180.v:8526.39-8526.75"
-  cell $add $add$ls180.v:8526$2651
+  attribute \src "ls180.v:8514.39-8514.75"
+  cell $add $add$ls180.v:8514$2639
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -87176,10 +87152,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdcore_crc16_checker_cnt
     connect \B 1'1
-    connect \Y $add$ls180.v:8526$2651_Y
+    connect \Y $add$ls180.v:8514$2639_Y
   end
-  attribute \src "ls180.v:8587.37-8587.73"
-  cell $add $add$ls180.v:8587$2655
+  attribute \src "ls180.v:8575.37-8575.73"
+  cell $add $add$ls180.v:8575$2643
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -87187,10 +87163,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_sdblock2mem_fifo_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:8587$2655_Y
+    connect \Y $add$ls180.v:8575$2643_Y
   end
-  attribute \src "ls180.v:8590.37-8590.73"
-  cell $add $add$ls180.v:8590$2656
+  attribute \src "ls180.v:8578.37-8578.73"
+  cell $add $add$ls180.v:8578$2644
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -87198,10 +87174,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_sdblock2mem_fifo_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:8590$2656_Y
+    connect \Y $add$ls180.v:8578$2644_Y
   end
-  attribute \src "ls180.v:8594.36-8594.70"
-  cell $add $add$ls180.v:8594$2661
+  attribute \src "ls180.v:8582.36-8582.70"
+  cell $add $add$ls180.v:8582$2649
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -87209,10 +87185,10 @@ module \ls180
     parameter \Y_WIDTH 6
     connect \A \main_sdblock2mem_fifo_level
     connect \B 1'1
-    connect \Y $add$ls180.v:8594$2661_Y
+    connect \Y $add$ls180.v:8582$2649_Y
   end
-  attribute \src "ls180.v:8609.41-8609.80"
-  cell $add $add$ls180.v:8609$2665
+  attribute \src "ls180.v:8597.41-8597.80"
+  cell $add $add$ls180.v:8597$2653
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -87220,10 +87196,10 @@ module \ls180
     parameter \Y_WIDTH 2
     connect \A \main_sdblock2mem_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8609$2665_Y
+    connect \Y $add$ls180.v:8597$2653_Y
   end
-  attribute \src "ls180.v:8643.67-8643.106"
-  cell $add $add$ls180.v:8643$2671
+  attribute \src "ls180.v:8631.67-8631.106"
+  cell $add $add$ls180.v:8631$2659
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -87231,10 +87207,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdblock2mem_converter_demux
     connect \B 1'1
-    connect \Y $add$ls180.v:8643$2671_Y
+    connect \Y $add$ls180.v:8631$2659_Y
   end
-  attribute \src "ls180.v:8669.39-8669.76"
-  cell $add $add$ls180.v:8669$2673
+  attribute \src "ls180.v:8657.39-8657.76"
+  cell $add $add$ls180.v:8657$2661
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -87242,10 +87218,10 @@ module \ls180
     parameter \Y_WIDTH 2
     connect \A \main_sdmem2block_converter_mux
     connect \B 1'1
-    connect \Y $add$ls180.v:8669$2673_Y
+    connect \Y $add$ls180.v:8657$2661_Y
   end
-  attribute \src "ls180.v:8673.37-8673.73"
-  cell $add $add$ls180.v:8673$2677
+  attribute \src "ls180.v:8661.37-8661.73"
+  cell $add $add$ls180.v:8661$2665
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -87253,10 +87229,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_sdmem2block_fifo_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:8673$2677_Y
+    connect \Y $add$ls180.v:8661$2665_Y
   end
-  attribute \src "ls180.v:8676.37-8676.73"
-  cell $add $add$ls180.v:8676$2678
+  attribute \src "ls180.v:8664.37-8664.73"
+  cell $add $add$ls180.v:8664$2666
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -87264,10 +87240,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_sdmem2block_fifo_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:8676$2678_Y
+    connect \Y $add$ls180.v:8664$2666_Y
   end
-  attribute \src "ls180.v:8680.36-8680.70"
-  cell $add $add$ls180.v:8680$2683
+  attribute \src "ls180.v:8668.36-8668.70"
+  cell $add $add$ls180.v:8668$2671
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -87275,7 +87251,7 @@ module \ls180
     parameter \Y_WIDTH 6
     connect \A \main_sdmem2block_fifo_level
     connect \B 1'1
-    connect \Y $add$ls180.v:8680$2683_Y
+    connect \Y $add$ls180.v:8668$2671_Y
   end
   attribute \src "ls180.v:2813.9-2813.80"
   cell $and $and$ls180.v:2813$17
@@ -98354,8 +98330,8 @@ module \ls180
     connect \B \main_sdphy_sdpads_clk
     connect \Y $and$ls180.v:7416$2373_Y
   end
-  attribute \src "ls180.v:7507.8-7507.67"
-  cell $and $and$ls180.v:7507$2416
+  attribute \src "ls180.v:7495.8-7495.67"
+  cell $and $and$ls180.v:7495$2404
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98363,54 +98339,54 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_ram_bus_cyc
     connect \B \main_libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:7507$2416_Y
+    connect \Y $and$ls180.v:7495$2404_Y
   end
-  attribute \src "ls180.v:7507.7-7507.102"
-  cell $and $and$ls180.v:7507$2418
+  attribute \src "ls180.v:7495.7-7495.102"
+  cell $and $and$ls180.v:7495$2406
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7507$2416_Y
-    connect \B $not$ls180.v:7507$2417_Y
-    connect \Y $and$ls180.v:7507$2418_Y
+    connect \A $and$ls180.v:7495$2404_Y
+    connect \B $not$ls180.v:7495$2405_Y
+    connect \Y $and$ls180.v:7495$2406_Y
   end
-  attribute \src "ls180.v:7526.7-7526.75"
-  cell $and $and$ls180.v:7526$2422
+  attribute \src "ls180.v:7514.7-7514.75"
+  cell $and $and$ls180.v:7514$2410
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:7526$2421_Y
+    connect \A $not$ls180.v:7514$2409_Y
     connect \B \main_libresocsim_zero_old_trigger
-    connect \Y $and$ls180.v:7526$2422_Y
+    connect \Y $and$ls180.v:7514$2410_Y
   end
-  attribute \src "ls180.v:7534.7-7534.56"
-  cell $and $and$ls180.v:7534$2424
+  attribute \src "ls180.v:7522.7-7522.56"
+  cell $and $and$ls180.v:7522$2412
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_timer_wait
-    connect \B $not$ls180.v:7534$2423_Y
-    connect \Y $and$ls180.v:7534$2424_Y
+    connect \B $not$ls180.v:7522$2411_Y
+    connect \Y $and$ls180.v:7522$2412_Y
   end
-  attribute \src "ls180.v:7562.7-7562.75"
-  cell $and $and$ls180.v:7562$2431
+  attribute \src "ls180.v:7550.7-7550.75"
+  cell $and $and$ls180.v:7550$2419
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_start1
-    connect \B $eq$ls180.v:7562$2430_Y
-    connect \Y $and$ls180.v:7562$2431_Y
+    connect \B $eq$ls180.v:7550$2418_Y
+    connect \Y $and$ls180.v:7550$2419_Y
   end
-  attribute \src "ls180.v:7604.8-7604.131"
-  cell $and $and$ls180.v:7604$2437
+  attribute \src "ls180.v:7592.8-7592.131"
+  cell $and $and$ls180.v:7592$2425
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98418,21 +98394,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
     connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
-    connect \Y $and$ls180.v:7604$2437_Y
+    connect \Y $and$ls180.v:7592$2425_Y
   end
-  attribute \src "ls180.v:7604.7-7604.190"
-  cell $and $and$ls180.v:7604$2439
+  attribute \src "ls180.v:7592.7-7592.190"
+  cell $and $and$ls180.v:7592$2427
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7604$2437_Y
-    connect \B $not$ls180.v:7604$2438_Y
-    connect \Y $and$ls180.v:7604$2439_Y
+    connect \A $and$ls180.v:7592$2425_Y
+    connect \B $not$ls180.v:7592$2426_Y
+    connect \Y $and$ls180.v:7592$2427_Y
   end
-  attribute \src "ls180.v:7610.8-7610.131"
-  cell $and $and$ls180.v:7610$2442
+  attribute \src "ls180.v:7598.8-7598.131"
+  cell $and $and$ls180.v:7598$2430
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98440,21 +98416,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
     connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
-    connect \Y $and$ls180.v:7610$2442_Y
+    connect \Y $and$ls180.v:7598$2430_Y
   end
-  attribute \src "ls180.v:7610.7-7610.190"
-  cell $and $and$ls180.v:7610$2444
+  attribute \src "ls180.v:7598.7-7598.190"
+  cell $and $and$ls180.v:7598$2432
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7610$2442_Y
-    connect \B $not$ls180.v:7610$2443_Y
-    connect \Y $and$ls180.v:7610$2444_Y
+    connect \A $and$ls180.v:7598$2430_Y
+    connect \B $not$ls180.v:7598$2431_Y
+    connect \Y $and$ls180.v:7598$2432_Y
   end
-  attribute \src "ls180.v:7650.8-7650.131"
-  cell $and $and$ls180.v:7650$2453
+  attribute \src "ls180.v:7638.8-7638.131"
+  cell $and $and$ls180.v:7638$2441
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98462,21 +98438,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
     connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
-    connect \Y $and$ls180.v:7650$2453_Y
+    connect \Y $and$ls180.v:7638$2441_Y
   end
-  attribute \src "ls180.v:7650.7-7650.190"
-  cell $and $and$ls180.v:7650$2455
+  attribute \src "ls180.v:7638.7-7638.190"
+  cell $and $and$ls180.v:7638$2443
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7650$2453_Y
-    connect \B $not$ls180.v:7650$2454_Y
-    connect \Y $and$ls180.v:7650$2455_Y
+    connect \A $and$ls180.v:7638$2441_Y
+    connect \B $not$ls180.v:7638$2442_Y
+    connect \Y $and$ls180.v:7638$2443_Y
   end
-  attribute \src "ls180.v:7656.8-7656.131"
-  cell $and $and$ls180.v:7656$2458
+  attribute \src "ls180.v:7644.8-7644.131"
+  cell $and $and$ls180.v:7644$2446
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98484,21 +98460,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
     connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
-    connect \Y $and$ls180.v:7656$2458_Y
+    connect \Y $and$ls180.v:7644$2446_Y
   end
-  attribute \src "ls180.v:7656.7-7656.190"
-  cell $and $and$ls180.v:7656$2460
+  attribute \src "ls180.v:7644.7-7644.190"
+  cell $and $and$ls180.v:7644$2448
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7656$2458_Y
-    connect \B $not$ls180.v:7656$2459_Y
-    connect \Y $and$ls180.v:7656$2460_Y
+    connect \A $and$ls180.v:7644$2446_Y
+    connect \B $not$ls180.v:7644$2447_Y
+    connect \Y $and$ls180.v:7644$2448_Y
   end
-  attribute \src "ls180.v:7696.8-7696.131"
-  cell $and $and$ls180.v:7696$2469
+  attribute \src "ls180.v:7684.8-7684.131"
+  cell $and $and$ls180.v:7684$2457
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98506,21 +98482,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
     connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
-    connect \Y $and$ls180.v:7696$2469_Y
+    connect \Y $and$ls180.v:7684$2457_Y
   end
-  attribute \src "ls180.v:7696.7-7696.190"
-  cell $and $and$ls180.v:7696$2471
+  attribute \src "ls180.v:7684.7-7684.190"
+  cell $and $and$ls180.v:7684$2459
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7696$2469_Y
-    connect \B $not$ls180.v:7696$2470_Y
-    connect \Y $and$ls180.v:7696$2471_Y
+    connect \A $and$ls180.v:7684$2457_Y
+    connect \B $not$ls180.v:7684$2458_Y
+    connect \Y $and$ls180.v:7684$2459_Y
   end
-  attribute \src "ls180.v:7702.8-7702.131"
-  cell $and $and$ls180.v:7702$2474
+  attribute \src "ls180.v:7690.8-7690.131"
+  cell $and $and$ls180.v:7690$2462
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98528,21 +98504,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
     connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
-    connect \Y $and$ls180.v:7702$2474_Y
+    connect \Y $and$ls180.v:7690$2462_Y
   end
-  attribute \src "ls180.v:7702.7-7702.190"
-  cell $and $and$ls180.v:7702$2476
+  attribute \src "ls180.v:7690.7-7690.190"
+  cell $and $and$ls180.v:7690$2464
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7702$2474_Y
-    connect \B $not$ls180.v:7702$2475_Y
-    connect \Y $and$ls180.v:7702$2476_Y
+    connect \A $and$ls180.v:7690$2462_Y
+    connect \B $not$ls180.v:7690$2463_Y
+    connect \Y $and$ls180.v:7690$2464_Y
   end
-  attribute \src "ls180.v:7742.8-7742.131"
-  cell $and $and$ls180.v:7742$2485
+  attribute \src "ls180.v:7730.8-7730.131"
+  cell $and $and$ls180.v:7730$2473
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98550,21 +98526,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
     connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
-    connect \Y $and$ls180.v:7742$2485_Y
+    connect \Y $and$ls180.v:7730$2473_Y
   end
-  attribute \src "ls180.v:7742.7-7742.190"
-  cell $and $and$ls180.v:7742$2487
+  attribute \src "ls180.v:7730.7-7730.190"
+  cell $and $and$ls180.v:7730$2475
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7742$2485_Y
-    connect \B $not$ls180.v:7742$2486_Y
-    connect \Y $and$ls180.v:7742$2487_Y
+    connect \A $and$ls180.v:7730$2473_Y
+    connect \B $not$ls180.v:7730$2474_Y
+    connect \Y $and$ls180.v:7730$2475_Y
   end
-  attribute \src "ls180.v:7748.8-7748.131"
-  cell $and $and$ls180.v:7748$2490
+  attribute \src "ls180.v:7736.8-7736.131"
+  cell $and $and$ls180.v:7736$2478
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98572,109 +98548,109 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
     connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
-    connect \Y $and$ls180.v:7748$2490_Y
+    connect \Y $and$ls180.v:7736$2478_Y
   end
-  attribute \src "ls180.v:7748.7-7748.190"
-  cell $and $and$ls180.v:7748$2492
+  attribute \src "ls180.v:7736.7-7736.190"
+  cell $and $and$ls180.v:7736$2480
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7748$2490_Y
-    connect \B $not$ls180.v:7748$2491_Y
-    connect \Y $and$ls180.v:7748$2492_Y
+    connect \A $and$ls180.v:7736$2478_Y
+    connect \B $not$ls180.v:7736$2479_Y
+    connect \Y $and$ls180.v:7736$2480_Y
   end
-  attribute \src "ls180.v:7945.48-7945.124"
-  cell $and $and$ls180.v:7945$2517
+  attribute \src "ls180.v:7933.48-7933.124"
+  cell $and $and$ls180.v:7933$2505
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7945$2516_Y
+    connect \A $eq$ls180.v:7933$2504_Y
     connect \B \main_sdram_interface_bank0_wdata_ready
-    connect \Y $and$ls180.v:7945$2517_Y
+    connect \Y $and$ls180.v:7933$2505_Y
   end
-  attribute \src "ls180.v:7945.130-7945.206"
-  cell $and $and$ls180.v:7945$2520
+  attribute \src "ls180.v:7933.130-7933.206"
+  cell $and $and$ls180.v:7933$2508
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7945$2519_Y
+    connect \A $eq$ls180.v:7933$2507_Y
     connect \B \main_sdram_interface_bank1_wdata_ready
-    connect \Y $and$ls180.v:7945$2520_Y
+    connect \Y $and$ls180.v:7933$2508_Y
   end
-  attribute \src "ls180.v:7945.212-7945.288"
-  cell $and $and$ls180.v:7945$2523
+  attribute \src "ls180.v:7933.212-7933.288"
+  cell $and $and$ls180.v:7933$2511
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7945$2522_Y
+    connect \A $eq$ls180.v:7933$2510_Y
     connect \B \main_sdram_interface_bank2_wdata_ready
-    connect \Y $and$ls180.v:7945$2523_Y
+    connect \Y $and$ls180.v:7933$2511_Y
   end
-  attribute \src "ls180.v:7945.294-7945.370"
-  cell $and $and$ls180.v:7945$2526
+  attribute \src "ls180.v:7933.294-7933.370"
+  cell $and $and$ls180.v:7933$2514
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7945$2525_Y
+    connect \A $eq$ls180.v:7933$2513_Y
     connect \B \main_sdram_interface_bank3_wdata_ready
-    connect \Y $and$ls180.v:7945$2526_Y
+    connect \Y $and$ls180.v:7933$2514_Y
   end
-  attribute \src "ls180.v:7946.49-7946.125"
-  cell $and $and$ls180.v:7946$2529
+  attribute \src "ls180.v:7934.49-7934.125"
+  cell $and $and$ls180.v:7934$2517
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7946$2528_Y
+    connect \A $eq$ls180.v:7934$2516_Y
     connect \B \main_sdram_interface_bank0_rdata_valid
-    connect \Y $and$ls180.v:7946$2529_Y
+    connect \Y $and$ls180.v:7934$2517_Y
   end
-  attribute \src "ls180.v:7946.131-7946.207"
-  cell $and $and$ls180.v:7946$2532
+  attribute \src "ls180.v:7934.131-7934.207"
+  cell $and $and$ls180.v:7934$2520
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7946$2531_Y
+    connect \A $eq$ls180.v:7934$2519_Y
     connect \B \main_sdram_interface_bank1_rdata_valid
-    connect \Y $and$ls180.v:7946$2532_Y
+    connect \Y $and$ls180.v:7934$2520_Y
   end
-  attribute \src "ls180.v:7946.213-7946.289"
-  cell $and $and$ls180.v:7946$2535
+  attribute \src "ls180.v:7934.213-7934.289"
+  cell $and $and$ls180.v:7934$2523
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7946$2534_Y
+    connect \A $eq$ls180.v:7934$2522_Y
     connect \B \main_sdram_interface_bank2_rdata_valid
-    connect \Y $and$ls180.v:7946$2535_Y
+    connect \Y $and$ls180.v:7934$2523_Y
   end
-  attribute \src "ls180.v:7946.295-7946.371"
-  cell $and $and$ls180.v:7946$2538
+  attribute \src "ls180.v:7934.295-7934.371"
+  cell $and $and$ls180.v:7934$2526
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:7946$2537_Y
+    connect \A $eq$ls180.v:7934$2525_Y
     connect \B \main_sdram_interface_bank3_rdata_valid
-    connect \Y $and$ls180.v:7946$2538_Y
+    connect \Y $and$ls180.v:7934$2526_Y
   end
-  attribute \src "ls180.v:7965.8-7965.49"
-  cell $and $and$ls180.v:7965$2541
+  attribute \src "ls180.v:7953.8-7953.49"
+  cell $and $and$ls180.v:7953$2529
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98682,10 +98658,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_cmd_valid
     connect \B \main_port_cmd_ready
-    connect \Y $and$ls180.v:7965$2541_Y
+    connect \Y $and$ls180.v:7953$2529_Y
   end
-  attribute \src "ls180.v:7968.8-7968.53"
-  cell $and $and$ls180.v:7968$2542
+  attribute \src "ls180.v:7956.8-7956.53"
+  cell $and $and$ls180.v:7956$2530
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98693,32 +98669,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_port_wdata_valid
     connect \B \main_port_wdata_ready
-    connect \Y $and$ls180.v:7968$2542_Y
+    connect \Y $and$ls180.v:7956$2530_Y
   end
-  attribute \src "ls180.v:7973.8-7973.59"
-  cell $and $and$ls180.v:7973$2544
+  attribute \src "ls180.v:7961.8-7961.59"
+  cell $and $and$ls180.v:7961$2532
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_sink_valid
-    connect \B $not$ls180.v:7973$2543_Y
-    connect \Y $and$ls180.v:7973$2544_Y
+    connect \B $not$ls180.v:7961$2531_Y
+    connect \Y $and$ls180.v:7961$2532_Y
   end
-  attribute \src "ls180.v:7973.7-7973.90"
-  cell $and $and$ls180.v:7973$2546
+  attribute \src "ls180.v:7961.7-7961.90"
+  cell $and $and$ls180.v:7961$2534
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:7973$2544_Y
-    connect \B $not$ls180.v:7973$2545_Y
-    connect \Y $and$ls180.v:7973$2546_Y
+    connect \A $and$ls180.v:7961$2532_Y
+    connect \B $not$ls180.v:7961$2533_Y
+    connect \Y $and$ls180.v:7961$2534_Y
   end
-  attribute \src "ls180.v:7979.8-7979.59"
-  cell $and $and$ls180.v:7979$2547
+  attribute \src "ls180.v:7967.8-7967.59"
+  cell $and $and$ls180.v:7967$2535
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98726,43 +98702,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_uart_clk_txen
     connect \B \main_uart_phy_tx_busy
-    connect \Y $and$ls180.v:7979$2547_Y
+    connect \Y $and$ls180.v:7967$2535_Y
   end
-  attribute \src "ls180.v:8003.8-8003.48"
-  cell $and $and$ls180.v:8003$2554
+  attribute \src "ls180.v:7991.8-7991.48"
+  cell $and $and$ls180.v:7991$2542
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8003$2553_Y
+    connect \A $not$ls180.v:7991$2541_Y
     connect \B \main_uart_phy_rx_r
-    connect \Y $and$ls180.v:8003$2554_Y
+    connect \Y $and$ls180.v:7991$2542_Y
   end
-  attribute \src "ls180.v:8036.7-8036.57"
-  cell $and $and$ls180.v:8036$2560
+  attribute \src "ls180.v:8024.7-8024.57"
+  cell $and $and$ls180.v:8024$2548
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8036$2559_Y
+    connect \A $not$ls180.v:8024$2547_Y
     connect \B \main_uart_tx_old_trigger
-    connect \Y $and$ls180.v:8036$2560_Y
+    connect \Y $and$ls180.v:8024$2548_Y
   end
-  attribute \src "ls180.v:8043.7-8043.57"
-  cell $and $and$ls180.v:8043$2562
+  attribute \src "ls180.v:8031.7-8031.57"
+  cell $and $and$ls180.v:8031$2550
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8043$2561_Y
+    connect \A $not$ls180.v:8031$2549_Y
     connect \B \main_uart_rx_old_trigger
-    connect \Y $and$ls180.v:8043$2562_Y
+    connect \Y $and$ls180.v:8031$2550_Y
   end
-  attribute \src "ls180.v:8053.8-8053.75"
-  cell $and $and$ls180.v:8053$2563
+  attribute \src "ls180.v:8041.8-8041.75"
+  cell $and $and$ls180.v:8041$2551
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98770,21 +98746,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_syncfifo_we
     connect \B \main_uart_tx_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8053$2563_Y
+    connect \Y $and$ls180.v:8041$2551_Y
   end
-  attribute \src "ls180.v:8053.7-8053.107"
-  cell $and $and$ls180.v:8053$2565
+  attribute \src "ls180.v:8041.7-8041.107"
+  cell $and $and$ls180.v:8041$2553
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8053$2563_Y
-    connect \B $not$ls180.v:8053$2564_Y
-    connect \Y $and$ls180.v:8053$2565_Y
+    connect \A $and$ls180.v:8041$2551_Y
+    connect \B $not$ls180.v:8041$2552_Y
+    connect \Y $and$ls180.v:8041$2553_Y
   end
-  attribute \src "ls180.v:8059.8-8059.75"
-  cell $and $and$ls180.v:8059$2568
+  attribute \src "ls180.v:8047.8-8047.75"
+  cell $and $and$ls180.v:8047$2556
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98792,21 +98768,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_syncfifo_we
     connect \B \main_uart_tx_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8059$2568_Y
+    connect \Y $and$ls180.v:8047$2556_Y
   end
-  attribute \src "ls180.v:8059.7-8059.107"
-  cell $and $and$ls180.v:8059$2570
+  attribute \src "ls180.v:8047.7-8047.107"
+  cell $and $and$ls180.v:8047$2558
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8059$2568_Y
-    connect \B $not$ls180.v:8059$2569_Y
-    connect \Y $and$ls180.v:8059$2570_Y
+    connect \A $and$ls180.v:8047$2556_Y
+    connect \B $not$ls180.v:8047$2557_Y
+    connect \Y $and$ls180.v:8047$2558_Y
   end
-  attribute \src "ls180.v:8075.8-8075.75"
-  cell $and $and$ls180.v:8075$2574
+  attribute \src "ls180.v:8063.8-8063.75"
+  cell $and $and$ls180.v:8063$2562
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98814,21 +98790,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_syncfifo_we
     connect \B \main_uart_rx_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8075$2574_Y
+    connect \Y $and$ls180.v:8063$2562_Y
   end
-  attribute \src "ls180.v:8075.7-8075.107"
-  cell $and $and$ls180.v:8075$2576
+  attribute \src "ls180.v:8063.7-8063.107"
+  cell $and $and$ls180.v:8063$2564
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8075$2574_Y
-    connect \B $not$ls180.v:8075$2575_Y
-    connect \Y $and$ls180.v:8075$2576_Y
+    connect \A $and$ls180.v:8063$2562_Y
+    connect \B $not$ls180.v:8063$2563_Y
+    connect \Y $and$ls180.v:8063$2564_Y
   end
-  attribute \src "ls180.v:8081.8-8081.75"
-  cell $and $and$ls180.v:8081$2579
+  attribute \src "ls180.v:8069.8-8069.75"
+  cell $and $and$ls180.v:8069$2567
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98836,21 +98812,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_syncfifo_we
     connect \B \main_uart_rx_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8081$2579_Y
+    connect \Y $and$ls180.v:8069$2567_Y
   end
-  attribute \src "ls180.v:8081.7-8081.107"
-  cell $and $and$ls180.v:8081$2581
+  attribute \src "ls180.v:8069.7-8069.107"
+  cell $and $and$ls180.v:8069$2569
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8081$2579_Y
-    connect \B $not$ls180.v:8081$2580_Y
-    connect \Y $and$ls180.v:8081$2581_Y
+    connect \A $and$ls180.v:8069$2567_Y
+    connect \B $not$ls180.v:8069$2568_Y
+    connect \Y $and$ls180.v:8069$2569_Y
   end
-  attribute \src "ls180.v:8229.7-8229.96"
-  cell $and $and$ls180.v:8229$2609
+  attribute \src "ls180.v:8217.7-8217.96"
+  cell $and $and$ls180.v:8217$2597
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98858,10 +98834,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_source_valid
     connect \B \main_sdphy_cmdr_cmdr_converter_source_ready
-    connect \Y $and$ls180.v:8229$2609_Y
+    connect \Y $and$ls180.v:8217$2597_Y
   end
-  attribute \src "ls180.v:8230.8-8230.93"
-  cell $and $and$ls180.v:8230$2610
+  attribute \src "ls180.v:8218.8-8218.93"
+  cell $and $and$ls180.v:8218$2598
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98869,10 +98845,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
     connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
-    connect \Y $and$ls180.v:8230$2610_Y
+    connect \Y $and$ls180.v:8218$2598_Y
   end
-  attribute \src "ls180.v:8238.8-8238.93"
-  cell $and $and$ls180.v:8238$2611
+  attribute \src "ls180.v:8226.8-8226.93"
+  cell $and $and$ls180.v:8226$2599
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98880,10 +98856,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
     connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
-    connect \Y $and$ls180.v:8238$2611_Y
+    connect \Y $and$ls180.v:8226$2599_Y
   end
-  attribute \src "ls180.v:8310.7-8310.98"
-  cell $and $and$ls180.v:8310$2621
+  attribute \src "ls180.v:8298.7-8298.98"
+  cell $and $and$ls180.v:8298$2609
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98891,10 +98867,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_source_valid
     connect \B \main_sdphy_dataw_crcr_converter_source_ready
-    connect \Y $and$ls180.v:8310$2621_Y
+    connect \Y $and$ls180.v:8298$2609_Y
   end
-  attribute \src "ls180.v:8311.8-8311.95"
-  cell $and $and$ls180.v:8311$2622
+  attribute \src "ls180.v:8299.8-8299.95"
+  cell $and $and$ls180.v:8299$2610
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98902,10 +98878,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_sink_valid
     connect \B \main_sdphy_dataw_crcr_converter_sink_ready
-    connect \Y $and$ls180.v:8311$2622_Y
+    connect \Y $and$ls180.v:8299$2610_Y
   end
-  attribute \src "ls180.v:8319.8-8319.95"
-  cell $and $and$ls180.v:8319$2623
+  attribute \src "ls180.v:8307.8-8307.95"
+  cell $and $and$ls180.v:8307$2611
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98913,10 +98889,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_sink_valid
     connect \B \main_sdphy_dataw_crcr_converter_sink_ready
-    connect \Y $and$ls180.v:8319$2623_Y
+    connect \Y $and$ls180.v:8307$2611_Y
   end
-  attribute \src "ls180.v:8389.7-8389.100"
-  cell $and $and$ls180.v:8389$2633
+  attribute \src "ls180.v:8377.7-8377.100"
+  cell $and $and$ls180.v:8377$2621
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98924,10 +98900,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_source_valid
     connect \B \main_sdphy_datar_datar_converter_source_ready
-    connect \Y $and$ls180.v:8389$2633_Y
+    connect \Y $and$ls180.v:8377$2621_Y
   end
-  attribute \src "ls180.v:8390.8-8390.97"
-  cell $and $and$ls180.v:8390$2634
+  attribute \src "ls180.v:8378.8-8378.97"
+  cell $and $and$ls180.v:8378$2622
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98935,10 +98911,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_sink_valid
     connect \B \main_sdphy_datar_datar_converter_sink_ready
-    connect \Y $and$ls180.v:8390$2634_Y
+    connect \Y $and$ls180.v:8378$2622_Y
   end
-  attribute \src "ls180.v:8398.8-8398.97"
-  cell $and $and$ls180.v:8398$2635
+  attribute \src "ls180.v:8386.8-8386.97"
+  cell $and $and$ls180.v:8386$2623
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98946,10 +98922,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_sink_valid
     connect \B \main_sdphy_datar_datar_converter_sink_ready
-    connect \Y $and$ls180.v:8398$2635_Y
+    connect \Y $and$ls180.v:8386$2623_Y
   end
-  attribute \src "ls180.v:8489.7-8489.82"
-  cell $and $and$ls180.v:8489$2641
+  attribute \src "ls180.v:8477.7-8477.82"
+  cell $and $and$ls180.v:8477$2629
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98957,10 +98933,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_ready
     connect \B \main_sdcore_crc16_checker_sink_valid
-    connect \Y $and$ls180.v:8489$2641_Y
+    connect \Y $and$ls180.v:8477$2629_Y
   end
-  attribute \src "ls180.v:8492.7-8492.82"
-  cell $and $and$ls180.v:8492$2642
+  attribute \src "ls180.v:8480.7-8480.82"
+  cell $and $and$ls180.v:8480$2630
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98968,10 +98944,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_ready
     connect \B \main_sdcore_crc16_checker_sink_valid
-    connect \Y $and$ls180.v:8492$2642_Y
+    connect \Y $and$ls180.v:8480$2630_Y
   end
-  attribute \src "ls180.v:8495.7-8495.82"
-  cell $and $and$ls180.v:8495$2643
+  attribute \src "ls180.v:8483.7-8483.82"
+  cell $and $and$ls180.v:8483$2631
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98979,10 +98955,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_ready
     connect \B \main_sdcore_crc16_checker_sink_valid
-    connect \Y $and$ls180.v:8495$2643_Y
+    connect \Y $and$ls180.v:8483$2631_Y
   end
-  attribute \src "ls180.v:8498.7-8498.82"
-  cell $and $and$ls180.v:8498$2644
+  attribute \src "ls180.v:8486.7-8486.82"
+  cell $and $and$ls180.v:8486$2632
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -98990,10 +98966,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_ready
     connect \B \main_sdcore_crc16_checker_sink_valid
-    connect \Y $and$ls180.v:8498$2644_Y
+    connect \Y $and$ls180.v:8486$2632_Y
   end
-  attribute \src "ls180.v:8501.7-8501.82"
-  cell $and $and$ls180.v:8501$2645
+  attribute \src "ls180.v:8489.7-8489.82"
+  cell $and $and$ls180.v:8489$2633
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -99001,10 +98977,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:8501$2645_Y
+    connect \Y $and$ls180.v:8489$2633_Y
   end
-  attribute \src "ls180.v:8506.7-8506.82"
-  cell $and $and$ls180.v:8506$2646
+  attribute \src "ls180.v:8494.7-8494.82"
+  cell $and $and$ls180.v:8494$2634
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -99012,10 +98988,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:8506$2646_Y
+    connect \Y $and$ls180.v:8494$2634_Y
   end
-  attribute \src "ls180.v:8511.7-8511.82"
-  cell $and $and$ls180.v:8511$2647
+  attribute \src "ls180.v:8499.7-8499.82"
+  cell $and $and$ls180.v:8499$2635
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -99023,10 +98999,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:8511$2647_Y
+    connect \Y $and$ls180.v:8499$2635_Y
   end
-  attribute \src "ls180.v:8516.7-8516.82"
-  cell $and $and$ls180.v:8516$2648
+  attribute \src "ls180.v:8504.7-8504.82"
+  cell $and $and$ls180.v:8504$2636
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -99034,10 +99010,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:8516$2648_Y
+    connect \Y $and$ls180.v:8504$2636_Y
   end
-  attribute \src "ls180.v:8521.7-8521.82"
-  cell $and $and$ls180.v:8521$2649
+  attribute \src "ls180.v:8509.7-8509.82"
+  cell $and $and$ls180.v:8509$2637
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -99045,10 +99021,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_sink_valid
     connect \B \main_sdcore_crc16_checker_sink_ready
-    connect \Y $and$ls180.v:8521$2649_Y
+    connect \Y $and$ls180.v:8509$2637_Y
   end
-  attribute \src "ls180.v:8586.8-8586.83"
-  cell $and $and$ls180.v:8586$2652
+  attribute \src "ls180.v:8574.8-8574.83"
+  cell $and $and$ls180.v:8574$2640
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -99056,21 +99032,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_syncfifo_we
     connect \B \main_sdblock2mem_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8586$2652_Y
+    connect \Y $and$ls180.v:8574$2640_Y
   end
-  attribute \src "ls180.v:8586.7-8586.119"
-  cell $and $and$ls180.v:8586$2654
+  attribute \src "ls180.v:8574.7-8574.119"
+  cell $and $and$ls180.v:8574$2642
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8586$2652_Y
-    connect \B $not$ls180.v:8586$2653_Y
-    connect \Y $and$ls180.v:8586$2654_Y
+    connect \A $and$ls180.v:8574$2640_Y
+    connect \B $not$ls180.v:8574$2641_Y
+    connect \Y $and$ls180.v:8574$2642_Y
   end
-  attribute \src "ls180.v:8592.8-8592.83"
-  cell $and $and$ls180.v:8592$2657
+  attribute \src "ls180.v:8580.8-8580.83"
+  cell $and $and$ls180.v:8580$2645
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -99078,21 +99054,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_syncfifo_we
     connect \B \main_sdblock2mem_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8592$2657_Y
+    connect \Y $and$ls180.v:8580$2645_Y
   end
-  attribute \src "ls180.v:8592.7-8592.119"
-  cell $and $and$ls180.v:8592$2659
+  attribute \src "ls180.v:8580.7-8580.119"
+  cell $and $and$ls180.v:8580$2647
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8592$2657_Y
-    connect \B $not$ls180.v:8592$2658_Y
-    connect \Y $and$ls180.v:8592$2659_Y
+    connect \A $and$ls180.v:8580$2645_Y
+    connect \B $not$ls180.v:8580$2646_Y
+    connect \Y $and$ls180.v:8580$2647_Y
   end
-  attribute \src "ls180.v:8612.7-8612.88"
-  cell $and $and$ls180.v:8612$2666
+  attribute \src "ls180.v:8600.7-8600.88"
+  cell $and $and$ls180.v:8600$2654
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -99100,10 +99076,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_source_valid
     connect \B \main_sdblock2mem_converter_source_ready
-    connect \Y $and$ls180.v:8612$2666_Y
+    connect \Y $and$ls180.v:8600$2654_Y
   end
-  attribute \src "ls180.v:8613.8-8613.85"
-  cell $and $and$ls180.v:8613$2667
+  attribute \src "ls180.v:8601.8-8601.85"
+  cell $and $and$ls180.v:8601$2655
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -99111,10 +99087,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_sink_valid
     connect \B \main_sdblock2mem_converter_sink_ready
-    connect \Y $and$ls180.v:8613$2667_Y
+    connect \Y $and$ls180.v:8601$2655_Y
   end
-  attribute \src "ls180.v:8621.8-8621.85"
-  cell $and $and$ls180.v:8621$2668
+  attribute \src "ls180.v:8609.8-8609.85"
+  cell $and $and$ls180.v:8609$2656
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -99122,10 +99098,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_sink_valid
     connect \B \main_sdblock2mem_converter_sink_ready
-    connect \Y $and$ls180.v:8621$2668_Y
+    connect \Y $and$ls180.v:8609$2656_Y
   end
-  attribute \src "ls180.v:8665.7-8665.88"
-  cell $and $and$ls180.v:8665$2672
+  attribute \src "ls180.v:8653.7-8653.88"
+  cell $and $and$ls180.v:8653$2660
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -99133,10 +99109,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_converter_source_valid
     connect \B \main_sdmem2block_converter_source_ready
-    connect \Y $and$ls180.v:8665$2672_Y
+    connect \Y $and$ls180.v:8653$2660_Y
   end
-  attribute \src "ls180.v:8672.8-8672.83"
-  cell $and $and$ls180.v:8672$2674
+  attribute \src "ls180.v:8660.8-8660.83"
+  cell $and $and$ls180.v:8660$2662
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -99144,21 +99120,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_syncfifo_we
     connect \B \main_sdmem2block_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8672$2674_Y
+    connect \Y $and$ls180.v:8660$2662_Y
   end
-  attribute \src "ls180.v:8672.7-8672.119"
-  cell $and $and$ls180.v:8672$2676
+  attribute \src "ls180.v:8660.7-8660.119"
+  cell $and $and$ls180.v:8660$2664
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8672$2674_Y
-    connect \B $not$ls180.v:8672$2675_Y
-    connect \Y $and$ls180.v:8672$2676_Y
+    connect \A $and$ls180.v:8660$2662_Y
+    connect \B $not$ls180.v:8660$2663_Y
+    connect \Y $and$ls180.v:8660$2664_Y
   end
-  attribute \src "ls180.v:8678.8-8678.83"
-  cell $and $and$ls180.v:8678$2679
+  attribute \src "ls180.v:8666.8-8666.83"
+  cell $and $and$ls180.v:8666$2667
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -99166,18 +99142,18 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_syncfifo_we
     connect \B \main_sdmem2block_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:8678$2679_Y
+    connect \Y $and$ls180.v:8666$2667_Y
   end
-  attribute \src "ls180.v:8678.7-8678.119"
-  cell $and $and$ls180.v:8678$2681
+  attribute \src "ls180.v:8666.7-8666.119"
+  cell $and $and$ls180.v:8666$2669
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:8678$2679_Y
-    connect \B $not$ls180.v:8678$2680_Y
-    connect \Y $and$ls180.v:8678$2681_Y
+    connect \A $and$ls180.v:8666$2667_Y
+    connect \B $not$ls180.v:8666$2668_Y
+    connect \Y $and$ls180.v:8666$2669_Y
   end
   attribute \src "ls180.v:2814.42-2814.101"
   cell $eq $eq$ls180.v:2814$18
@@ -104657,8 +104633,8 @@ module \ls180
     connect \B 1'0
     connect \Y $eq$ls180.v:6918$2316_Y
   end
-  attribute \src "ls180.v:7511.8-7511.38"
-  cell $eq $eq$ls180.v:7511$2419
+  attribute \src "ls180.v:7499.8-7499.38"
+  cell $eq $eq$ls180.v:7499$2407
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -104666,10 +104642,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_value
     connect \B 1'0
-    connect \Y $eq$ls180.v:7511$2419_Y
+    connect \Y $eq$ls180.v:7499$2407_Y
   end
-  attribute \src "ls180.v:7542.8-7542.42"
-  cell $eq $eq$ls180.v:7542$2427
+  attribute \src "ls180.v:7530.8-7530.42"
+  cell $eq $eq$ls180.v:7530$2415
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -104677,10 +104653,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_postponer_count
     connect \B 1'0
-    connect \Y $eq$ls180.v:7542$2427_Y
+    connect \Y $eq$ls180.v:7530$2415_Y
   end
-  attribute \src "ls180.v:7562.38-7562.74"
-  cell $eq $eq$ls180.v:7562$2430
+  attribute \src "ls180.v:7550.38-7550.74"
+  cell $eq $eq$ls180.v:7550$2418
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -104688,10 +104664,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_counter
     connect \B 1'0
-    connect \Y $eq$ls180.v:7562$2430_Y
+    connect \Y $eq$ls180.v:7550$2418_Y
   end
-  attribute \src "ls180.v:7569.7-7569.43"
-  cell $eq $eq$ls180.v:7569$2432
+  attribute \src "ls180.v:7557.7-7557.43"
+  cell $eq $eq$ls180.v:7557$2420
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -104699,10 +104675,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_counter
     connect \B 2'10
-    connect \Y $eq$ls180.v:7569$2432_Y
+    connect \Y $eq$ls180.v:7557$2420_Y
   end
-  attribute \src "ls180.v:7576.7-7576.43"
-  cell $eq $eq$ls180.v:7576$2433
+  attribute \src "ls180.v:7564.7-7564.43"
+  cell $eq $eq$ls180.v:7564$2421
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -104710,10 +104686,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_counter
     connect \B 4'1000
-    connect \Y $eq$ls180.v:7576$2433_Y
+    connect \Y $eq$ls180.v:7564$2421_Y
   end
-  attribute \src "ls180.v:7584.7-7584.43"
-  cell $eq $eq$ls180.v:7584$2434
+  attribute \src "ls180.v:7572.7-7572.43"
+  cell $eq $eq$ls180.v:7572$2422
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -104721,10 +104697,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_counter
     connect \B 4'1000
-    connect \Y $eq$ls180.v:7584$2434_Y
+    connect \Y $eq$ls180.v:7572$2422_Y
   end
-  attribute \src "ls180.v:7636.9-7636.54"
-  cell $eq $eq$ls180.v:7636$2452
+  attribute \src "ls180.v:7624.9-7624.54"
+  cell $eq $eq$ls180.v:7624$2440
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -104732,10 +104708,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_twtpcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:7636$2452_Y
+    connect \Y $eq$ls180.v:7624$2440_Y
   end
-  attribute \src "ls180.v:7682.9-7682.54"
-  cell $eq $eq$ls180.v:7682$2468
+  attribute \src "ls180.v:7670.9-7670.54"
+  cell $eq $eq$ls180.v:7670$2456
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -104743,10 +104719,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_twtpcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:7682$2468_Y
+    connect \Y $eq$ls180.v:7670$2456_Y
   end
-  attribute \src "ls180.v:7728.9-7728.54"
-  cell $eq $eq$ls180.v:7728$2484
+  attribute \src "ls180.v:7716.9-7716.54"
+  cell $eq $eq$ls180.v:7716$2472
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -104754,10 +104730,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_twtpcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:7728$2484_Y
+    connect \Y $eq$ls180.v:7716$2472_Y
   end
-  attribute \src "ls180.v:7774.9-7774.54"
-  cell $eq $eq$ls180.v:7774$2500
+  attribute \src "ls180.v:7762.9-7762.54"
+  cell $eq $eq$ls180.v:7762$2488
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -104765,10 +104741,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_twtpcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:7774$2500_Y
+    connect \Y $eq$ls180.v:7762$2488_Y
   end
-  attribute \src "ls180.v:7924.9-7924.41"
-  cell $eq $eq$ls180.v:7924$2512
+  attribute \src "ls180.v:7912.9-7912.41"
+  cell $eq $eq$ls180.v:7912$2500
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -104776,10 +104752,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_tccdcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:7924$2512_Y
+    connect \Y $eq$ls180.v:7912$2500_Y
   end
-  attribute \src "ls180.v:7939.9-7939.41"
-  cell $eq $eq$ls180.v:7939$2515
+  attribute \src "ls180.v:7927.9-7927.41"
+  cell $eq $eq$ls180.v:7927$2503
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -104787,10 +104763,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_twtrcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:7939$2515_Y
+    connect \Y $eq$ls180.v:7927$2503_Y
   end
-  attribute \src "ls180.v:7945.49-7945.82"
-  cell $eq $eq$ls180.v:7945$2516
+  attribute \src "ls180.v:7933.49-7933.82"
+  cell $eq $eq$ls180.v:7933$2504
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -104798,10 +104774,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7945$2516_Y
+    connect \Y $eq$ls180.v:7933$2504_Y
   end
-  attribute \src "ls180.v:7945.131-7945.164"
-  cell $eq $eq$ls180.v:7945$2519
+  attribute \src "ls180.v:7933.131-7933.164"
+  cell $eq $eq$ls180.v:7933$2507
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -104809,10 +104785,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7945$2519_Y
+    connect \Y $eq$ls180.v:7933$2507_Y
   end
-  attribute \src "ls180.v:7945.213-7945.246"
-  cell $eq $eq$ls180.v:7945$2522
+  attribute \src "ls180.v:7933.213-7933.246"
+  cell $eq $eq$ls180.v:7933$2510
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -104820,10 +104796,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7945$2522_Y
+    connect \Y $eq$ls180.v:7933$2510_Y
   end
-  attribute \src "ls180.v:7945.295-7945.328"
-  cell $eq $eq$ls180.v:7945$2525
+  attribute \src "ls180.v:7933.295-7933.328"
+  cell $eq $eq$ls180.v:7933$2513
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -104831,10 +104807,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7945$2525_Y
+    connect \Y $eq$ls180.v:7933$2513_Y
   end
-  attribute \src "ls180.v:7946.50-7946.83"
-  cell $eq $eq$ls180.v:7946$2528
+  attribute \src "ls180.v:7934.50-7934.83"
+  cell $eq $eq$ls180.v:7934$2516
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -104842,10 +104818,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7946$2528_Y
+    connect \Y $eq$ls180.v:7934$2516_Y
   end
-  attribute \src "ls180.v:7946.132-7946.165"
-  cell $eq $eq$ls180.v:7946$2531
+  attribute \src "ls180.v:7934.132-7934.165"
+  cell $eq $eq$ls180.v:7934$2519
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -104853,10 +104829,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7946$2531_Y
+    connect \Y $eq$ls180.v:7934$2519_Y
   end
-  attribute \src "ls180.v:7946.214-7946.247"
-  cell $eq $eq$ls180.v:7946$2534
+  attribute \src "ls180.v:7934.214-7934.247"
+  cell $eq $eq$ls180.v:7934$2522
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -104864,10 +104840,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7946$2534_Y
+    connect \Y $eq$ls180.v:7934$2522_Y
   end
-  attribute \src "ls180.v:7946.296-7946.329"
-  cell $eq $eq$ls180.v:7946$2537
+  attribute \src "ls180.v:7934.296-7934.329"
+  cell $eq $eq$ls180.v:7934$2525
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -104875,10 +104851,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \builder_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:7946$2537_Y
+    connect \Y $eq$ls180.v:7934$2525_Y
   end
-  attribute \src "ls180.v:7981.9-7981.42"
-  cell $eq $eq$ls180.v:7981$2549
+  attribute \src "ls180.v:7969.9-7969.42"
+  cell $eq $eq$ls180.v:7969$2537
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -104886,10 +104862,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_tx_bitcount
     connect \B 4'1000
-    connect \Y $eq$ls180.v:7981$2549_Y
+    connect \Y $eq$ls180.v:7969$2537_Y
   end
-  attribute \src "ls180.v:7984.10-7984.43"
-  cell $eq $eq$ls180.v:7984$2550
+  attribute \src "ls180.v:7972.10-7972.43"
+  cell $eq $eq$ls180.v:7972$2538
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -104897,10 +104873,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_tx_bitcount
     connect \B 4'1001
-    connect \Y $eq$ls180.v:7984$2550_Y
+    connect \Y $eq$ls180.v:7972$2538_Y
   end
-  attribute \src "ls180.v:8010.9-8010.42"
-  cell $eq $eq$ls180.v:8010$2556
+  attribute \src "ls180.v:7998.9-7998.42"
+  cell $eq $eq$ls180.v:7998$2544
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -104908,10 +104884,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_rx_bitcount
     connect \B 1'0
-    connect \Y $eq$ls180.v:8010$2556_Y
+    connect \Y $eq$ls180.v:7998$2544_Y
   end
-  attribute \src "ls180.v:8015.10-8015.43"
-  cell $eq $eq$ls180.v:8015$2557
+  attribute \src "ls180.v:8003.10-8003.43"
+  cell $eq $eq$ls180.v:8003$2545
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -104919,10 +104895,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_rx_bitcount
     connect \B 4'1001
-    connect \Y $eq$ls180.v:8015$2557_Y
+    connect \Y $eq$ls180.v:8003$2545_Y
   end
-  attribute \src "ls180.v:8222.9-8222.53"
-  cell $eq $eq$ls180.v:8222$2606
+  attribute \src "ls180.v:8210.9-8210.53"
+  cell $eq $eq$ls180.v:8210$2594
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -104930,10 +104906,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_demux
     connect \B 3'111
-    connect \Y $eq$ls180.v:8222$2606_Y
+    connect \Y $eq$ls180.v:8210$2594_Y
   end
-  attribute \src "ls180.v:8303.9-8303.54"
-  cell $eq $eq$ls180.v:8303$2618
+  attribute \src "ls180.v:8291.9-8291.54"
+  cell $eq $eq$ls180.v:8291$2606
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -104941,10 +104917,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_demux
     connect \B 3'111
-    connect \Y $eq$ls180.v:8303$2618_Y
+    connect \Y $eq$ls180.v:8291$2606_Y
   end
-  attribute \src "ls180.v:8382.9-8382.55"
-  cell $eq $eq$ls180.v:8382$2630
+  attribute \src "ls180.v:8370.9-8370.55"
+  cell $eq $eq$ls180.v:8370$2618
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -104952,10 +104928,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_demux
     connect \B 1'1
-    connect \Y $eq$ls180.v:8382$2630_Y
+    connect \Y $eq$ls180.v:8370$2618_Y
   end
-  attribute \src "ls180.v:8605.9-8605.49"
-  cell $eq $eq$ls180.v:8605$2663
+  attribute \src "ls180.v:8593.9-8593.49"
+  cell $eq $eq$ls180.v:8593$2651
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -104963,29 +104939,29 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_demux
     connect \B 2'11
-    connect \Y $eq$ls180.v:8605$2663_Y
+    connect \Y $eq$ls180.v:8593$2651_Y
   end
-  attribute \src "ls180.v:8181.8-8181.54"
-  cell $ge $ge$ls180.v:8181$2598
+  attribute \src "ls180.v:8169.8-8169.54"
+  cell $ge $ge$ls180.v:8169$2586
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 1
     connect \A \main_pwm0_counter
-    connect \B $sub$ls180.v:8181$2597_Y
-    connect \Y $ge$ls180.v:8181$2598_Y
+    connect \B $sub$ls180.v:8169$2585_Y
+    connect \Y $ge$ls180.v:8169$2586_Y
   end
-  attribute \src "ls180.v:8195.8-8195.54"
-  cell $ge $ge$ls180.v:8195$2602
+  attribute \src "ls180.v:8183.8-8183.54"
+  cell $ge $ge$ls180.v:8183$2590
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
     parameter \B_WIDTH 32
     parameter \Y_WIDTH 1
     connect \A \main_pwm1_counter
-    connect \B $sub$ls180.v:8195$2601_Y
-    connect \Y $ge$ls180.v:8195$2602_Y
+    connect \B $sub$ls180.v:8183$2589_Y
+    connect \Y $ge$ls180.v:8183$2590_Y
   end
   attribute \src "ls180.v:5155.47-5155.83"
   cell $gt $gt$ls180.v:5155$914
@@ -105009,8 +104985,8 @@ module \ls180
     connect \B 4'1000
     connect \Y $lt$ls180.v:5161$917_Y
   end
-  attribute \src "ls180.v:8176.8-8176.43"
-  cell $lt $lt$ls180.v:8176$2596
+  attribute \src "ls180.v:8164.8-8164.43"
+  cell $lt $lt$ls180.v:8164$2584
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -105018,10 +104994,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_pwm0_counter
     connect \B \main_pwm0_width
-    connect \Y $lt$ls180.v:8176$2596_Y
+    connect \Y $lt$ls180.v:8164$2584_Y
   end
-  attribute \src "ls180.v:8190.8-8190.43"
-  cell $lt $lt$ls180.v:8190$2600
+  attribute \src "ls180.v:8178.8-8178.43"
+  cell $lt $lt$ls180.v:8178$2588
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -105029,10 +105005,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_pwm1_counter
     connect \B \main_pwm1_width
-    connect \Y $lt$ls180.v:8190$2600_Y
+    connect \Y $lt$ls180.v:8178$2588_Y
   end
-  attribute \src "ls180.v:10071.33-10071.36"
-  cell $memrd $memrd$\mem$ls180.v:10071$2705
+  attribute \src "ls180.v:10059.33-10059.36"
+  cell $memrd $memrd$\mem$ls180.v:10059$2693
     parameter \ABITS 7
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105041,11 +105017,11 @@ module \ls180
     parameter \WIDTH 32
     connect \ADDR \memadr
     connect \CLK 1'x
-    connect \DATA $memrd$\mem$ls180.v:10071$2705_DATA
+    connect \DATA $memrd$\mem$ls180.v:10059$2693_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10082.12-10082.19"
-  cell $memrd $memrd$\storage$ls180.v:10082$2710
+  attribute \src "ls180.v:10070.12-10070.19"
+  cell $memrd $memrd$\storage$ls180.v:10070$2698
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105054,11 +105030,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage$ls180.v:10082$2710_DATA
+    connect \DATA $memrd$\storage$ls180.v:10070$2698_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10089.68-10089.75"
-  cell $memrd $memrd$\storage$ls180.v:10089$2712
+  attribute \src "ls180.v:10077.68-10077.75"
+  cell $memrd $memrd$\storage$ls180.v:10077$2700
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105067,11 +105043,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage$ls180.v:10089$2712_DATA
+    connect \DATA $memrd$\storage$ls180.v:10077$2700_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10096.14-10096.23"
-  cell $memrd $memrd$\storage_1$ls180.v:10096$2717
+  attribute \src "ls180.v:10084.14-10084.23"
+  cell $memrd $memrd$\storage_1$ls180.v:10084$2705
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105080,11 +105056,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_1$ls180.v:10096$2717_DATA
+    connect \DATA $memrd$\storage_1$ls180.v:10084$2705_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10103.68-10103.77"
-  cell $memrd $memrd$\storage_1$ls180.v:10103$2719
+  attribute \src "ls180.v:10091.68-10091.77"
+  cell $memrd $memrd$\storage_1$ls180.v:10091$2707
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105093,11 +105069,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_1$ls180.v:10103$2719_DATA
+    connect \DATA $memrd$\storage_1$ls180.v:10091$2707_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10110.14-10110.23"
-  cell $memrd $memrd$\storage_2$ls180.v:10110$2724
+  attribute \src "ls180.v:10098.14-10098.23"
+  cell $memrd $memrd$\storage_2$ls180.v:10098$2712
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105106,11 +105082,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_2$ls180.v:10110$2724_DATA
+    connect \DATA $memrd$\storage_2$ls180.v:10098$2712_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10117.68-10117.77"
-  cell $memrd $memrd$\storage_2$ls180.v:10117$2726
+  attribute \src "ls180.v:10105.68-10105.77"
+  cell $memrd $memrd$\storage_2$ls180.v:10105$2714
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105119,11 +105095,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_2$ls180.v:10117$2726_DATA
+    connect \DATA $memrd$\storage_2$ls180.v:10105$2714_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10124.14-10124.23"
-  cell $memrd $memrd$\storage_3$ls180.v:10124$2731
+  attribute \src "ls180.v:10112.14-10112.23"
+  cell $memrd $memrd$\storage_3$ls180.v:10112$2719
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105132,11 +105108,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_3$ls180.v:10124$2731_DATA
+    connect \DATA $memrd$\storage_3$ls180.v:10112$2719_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10131.68-10131.77"
-  cell $memrd $memrd$\storage_3$ls180.v:10131$2733
+  attribute \src "ls180.v:10119.68-10119.77"
+  cell $memrd $memrd$\storage_3$ls180.v:10119$2721
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105145,11 +105121,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_3$ls180.v:10131$2733_DATA
+    connect \DATA $memrd$\storage_3$ls180.v:10119$2721_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10139.14-10139.23"
-  cell $memrd $memrd$\storage_4$ls180.v:10139$2738
+  attribute \src "ls180.v:10127.14-10127.23"
+  cell $memrd $memrd$\storage_4$ls180.v:10127$2726
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105158,11 +105134,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_uart_tx_fifo_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_4$ls180.v:10139$2738_DATA
+    connect \DATA $memrd$\storage_4$ls180.v:10127$2726_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10144.15-10144.24"
-  cell $memrd $memrd$\storage_4$ls180.v:10144$2740
+  attribute \src "ls180.v:10132.15-10132.24"
+  cell $memrd $memrd$\storage_4$ls180.v:10132$2728
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105171,11 +105147,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_uart_tx_fifo_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_4$ls180.v:10144$2740_DATA
+    connect \DATA $memrd$\storage_4$ls180.v:10132$2728_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10156.14-10156.23"
-  cell $memrd $memrd$\storage_5$ls180.v:10156$2745
+  attribute \src "ls180.v:10144.14-10144.23"
+  cell $memrd $memrd$\storage_5$ls180.v:10144$2733
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105184,11 +105160,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_uart_rx_fifo_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_5$ls180.v:10156$2745_DATA
+    connect \DATA $memrd$\storage_5$ls180.v:10144$2733_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10161.15-10161.24"
-  cell $memrd $memrd$\storage_5$ls180.v:10161$2747
+  attribute \src "ls180.v:10149.15-10149.24"
+  cell $memrd $memrd$\storage_5$ls180.v:10149$2735
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105197,11 +105173,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_uart_rx_fifo_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_5$ls180.v:10161$2747_DATA
+    connect \DATA $memrd$\storage_5$ls180.v:10149$2735_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10172.14-10172.23"
-  cell $memrd $memrd$\storage_6$ls180.v:10172$2752
+  attribute \src "ls180.v:10160.14-10160.23"
+  cell $memrd $memrd$\storage_6$ls180.v:10160$2740
     parameter \ABITS 5
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105210,11 +105186,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_sdblock2mem_fifo_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_6$ls180.v:10172$2752_DATA
+    connect \DATA $memrd$\storage_6$ls180.v:10160$2740_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10179.45-10179.54"
-  cell $memrd $memrd$\storage_6$ls180.v:10179$2754
+  attribute \src "ls180.v:10167.45-10167.54"
+  cell $memrd $memrd$\storage_6$ls180.v:10167$2742
     parameter \ABITS 5
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105223,11 +105199,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_sdblock2mem_fifo_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_6$ls180.v:10179$2754_DATA
+    connect \DATA $memrd$\storage_6$ls180.v:10167$2742_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10186.14-10186.23"
-  cell $memrd $memrd$\storage_7$ls180.v:10186$2759
+  attribute \src "ls180.v:10174.14-10174.23"
+  cell $memrd $memrd$\storage_7$ls180.v:10174$2747
     parameter \ABITS 5
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105236,11 +105212,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_sdmem2block_fifo_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_7$ls180.v:10186$2759_DATA
+    connect \DATA $memrd$\storage_7$ls180.v:10174$2747_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:10193.45-10193.54"
-  cell $memrd $memrd$\storage_7$ls180.v:10193$2761
+  attribute \src "ls180.v:10181.45-10181.54"
+  cell $memrd $memrd$\storage_7$ls180.v:10181$2749
     parameter \ABITS 5
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -105249,164 +105225,164 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \main_sdmem2block_fifo_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_7$ls180.v:10193$2761_DATA
+    connect \DATA $memrd$\storage_7$ls180.v:10181$2749_DATA
     connect \EN 1'x
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\mem$ls180.v:0$2763
+  cell $memwr $memwr$\mem$ls180.v:0$2751
     parameter \ABITS 7
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
-    parameter \PRIORITY 2763
+    parameter \PRIORITY 2751
     parameter \WIDTH 32
-    connect \ADDR $memwr$\mem$ls180.v:10061$1_ADDR
+    connect \ADDR $memwr$\mem$ls180.v:10049$1_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\mem$ls180.v:10061$1_DATA
-    connect \EN $memwr$\mem$ls180.v:10061$1_EN
+    connect \DATA $memwr$\mem$ls180.v:10049$1_DATA
+    connect \EN $memwr$\mem$ls180.v:10049$1_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\mem$ls180.v:0$2764
+  cell $memwr $memwr$\mem$ls180.v:0$2752
     parameter \ABITS 7
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
-    parameter \PRIORITY 2764
+    parameter \PRIORITY 2752
     parameter \WIDTH 32
-    connect \ADDR $memwr$\mem$ls180.v:10063$2_ADDR
+    connect \ADDR $memwr$\mem$ls180.v:10051$2_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\mem$ls180.v:10063$2_DATA
-    connect \EN $memwr$\mem$ls180.v:10063$2_EN
+    connect \DATA $memwr$\mem$ls180.v:10051$2_DATA
+    connect \EN $memwr$\mem$ls180.v:10051$2_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\mem$ls180.v:0$2765
+  cell $memwr $memwr$\mem$ls180.v:0$2753
     parameter \ABITS 7
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
-    parameter \PRIORITY 2765
+    parameter \PRIORITY 2753
     parameter \WIDTH 32
-    connect \ADDR $memwr$\mem$ls180.v:10065$3_ADDR
+    connect \ADDR $memwr$\mem$ls180.v:10053$3_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\mem$ls180.v:10065$3_DATA
-    connect \EN $memwr$\mem$ls180.v:10065$3_EN
+    connect \DATA $memwr$\mem$ls180.v:10053$3_DATA
+    connect \EN $memwr$\mem$ls180.v:10053$3_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\mem$ls180.v:0$2766
+  cell $memwr $memwr$\mem$ls180.v:0$2754
     parameter \ABITS 7
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
-    parameter \PRIORITY 2766
+    parameter \PRIORITY 2754
     parameter \WIDTH 32
-    connect \ADDR $memwr$\mem$ls180.v:10067$4_ADDR
+    connect \ADDR $memwr$\mem$ls180.v:10055$4_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\mem$ls180.v:10067$4_DATA
-    connect \EN $memwr$\mem$ls180.v:10067$4_EN
+    connect \DATA $memwr$\mem$ls180.v:10055$4_DATA
+    connect \EN $memwr$\mem$ls180.v:10055$4_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage$ls180.v:0$2767
+  cell $memwr $memwr$\storage$ls180.v:0$2755
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage"
-    parameter \PRIORITY 2767
+    parameter \PRIORITY 2755
     parameter \WIDTH 25
-    connect \ADDR $memwr$\storage$ls180.v:10081$5_ADDR
+    connect \ADDR $memwr$\storage$ls180.v:10069$5_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage$ls180.v:10081$5_DATA
-    connect \EN $memwr$\storage$ls180.v:10081$5_EN
+    connect \DATA $memwr$\storage$ls180.v:10069$5_DATA
+    connect \EN $memwr$\storage$ls180.v:10069$5_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_1$ls180.v:0$2768
+  cell $memwr $memwr$\storage_1$ls180.v:0$2756
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_1"
-    parameter \PRIORITY 2768
+    parameter \PRIORITY 2756
     parameter \WIDTH 25
-    connect \ADDR $memwr$\storage_1$ls180.v:10095$6_ADDR
+    connect \ADDR $memwr$\storage_1$ls180.v:10083$6_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_1$ls180.v:10095$6_DATA
-    connect \EN $memwr$\storage_1$ls180.v:10095$6_EN
+    connect \DATA $memwr$\storage_1$ls180.v:10083$6_DATA
+    connect \EN $memwr$\storage_1$ls180.v:10083$6_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_2$ls180.v:0$2769
+  cell $memwr $memwr$\storage_2$ls180.v:0$2757
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_2"
-    parameter \PRIORITY 2769
+    parameter \PRIORITY 2757
     parameter \WIDTH 25
-    connect \ADDR $memwr$\storage_2$ls180.v:10109$7_ADDR
+    connect \ADDR $memwr$\storage_2$ls180.v:10097$7_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_2$ls180.v:10109$7_DATA
-    connect \EN $memwr$\storage_2$ls180.v:10109$7_EN
+    connect \DATA $memwr$\storage_2$ls180.v:10097$7_DATA
+    connect \EN $memwr$\storage_2$ls180.v:10097$7_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_3$ls180.v:0$2770
+  cell $memwr $memwr$\storage_3$ls180.v:0$2758
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_3"
-    parameter \PRIORITY 2770
+    parameter \PRIORITY 2758
     parameter \WIDTH 25
-    connect \ADDR $memwr$\storage_3$ls180.v:10123$8_ADDR
+    connect \ADDR $memwr$\storage_3$ls180.v:10111$8_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_3$ls180.v:10123$8_DATA
-    connect \EN $memwr$\storage_3$ls180.v:10123$8_EN
+    connect \DATA $memwr$\storage_3$ls180.v:10111$8_DATA
+    connect \EN $memwr$\storage_3$ls180.v:10111$8_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_4$ls180.v:0$2771
+  cell $memwr $memwr$\storage_4$ls180.v:0$2759
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_4"
-    parameter \PRIORITY 2771
+    parameter \PRIORITY 2759
     parameter \WIDTH 10
-    connect \ADDR $memwr$\storage_4$ls180.v:10138$9_ADDR
+    connect \ADDR $memwr$\storage_4$ls180.v:10126$9_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_4$ls180.v:10138$9_DATA
-    connect \EN $memwr$\storage_4$ls180.v:10138$9_EN
+    connect \DATA $memwr$\storage_4$ls180.v:10126$9_DATA
+    connect \EN $memwr$\storage_4$ls180.v:10126$9_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_5$ls180.v:0$2772
+  cell $memwr $memwr$\storage_5$ls180.v:0$2760
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_5"
-    parameter \PRIORITY 2772
+    parameter \PRIORITY 2760
     parameter \WIDTH 10
-    connect \ADDR $memwr$\storage_5$ls180.v:10155$10_ADDR
+    connect \ADDR $memwr$\storage_5$ls180.v:10143$10_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_5$ls180.v:10155$10_DATA
-    connect \EN $memwr$\storage_5$ls180.v:10155$10_EN
+    connect \DATA $memwr$\storage_5$ls180.v:10143$10_DATA
+    connect \EN $memwr$\storage_5$ls180.v:10143$10_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_6$ls180.v:0$2773
+  cell $memwr $memwr$\storage_6$ls180.v:0$2761
     parameter \ABITS 5
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_6"
-    parameter \PRIORITY 2773
+    parameter \PRIORITY 2761
     parameter \WIDTH 10
-    connect \ADDR $memwr$\storage_6$ls180.v:10171$11_ADDR
+    connect \ADDR $memwr$\storage_6$ls180.v:10159$11_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_6$ls180.v:10171$11_DATA
-    connect \EN $memwr$\storage_6$ls180.v:10171$11_EN
+    connect \DATA $memwr$\storage_6$ls180.v:10159$11_DATA
+    connect \EN $memwr$\storage_6$ls180.v:10159$11_EN
   end
   attribute \src "ls180.v:0.0-0.0"
-  cell $memwr $memwr$\storage_7$ls180.v:0$2774
+  cell $memwr $memwr$\storage_7$ls180.v:0$2762
     parameter \ABITS 5
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\storage_7"
-    parameter \PRIORITY 2774
+    parameter \PRIORITY 2762
     parameter \WIDTH 10
-    connect \ADDR $memwr$\storage_7$ls180.v:10185$12_ADDR
+    connect \ADDR $memwr$\storage_7$ls180.v:10173$12_ADDR
     connect \CLK 1'x
-    connect \DATA $memwr$\storage_7$ls180.v:10185$12_DATA
-    connect \EN $memwr$\storage_7$ls180.v:10185$12_EN
+    connect \DATA $memwr$\storage_7$ls180.v:10173$12_DATA
+    connect \EN $memwr$\storage_7$ls180.v:10173$12_EN
   end
   attribute \src "ls180.v:2969.41-2969.71"
   cell $ne $ne$ls180.v:2969$60
@@ -105683,8 +105659,8 @@ module \ls180
     connect \B 1'0
     connect \Y $ne$ls180.v:5679$1027_Y
   end
-  attribute \src "ls180.v:7501.7-7501.52"
-  cell $ne $ne$ls180.v:7501$2414
+  attribute \src "ls180.v:7489.7-7489.52"
+  cell $ne $ne$ls180.v:7489$2402
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -105692,10 +105668,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_bus_errors
     connect \B 32'11111111111111111111111111111111
-    connect \Y $ne$ls180.v:7501$2414_Y
+    connect \Y $ne$ls180.v:7489$2402_Y
   end
-  attribute \src "ls180.v:7551.9-7551.43"
-  cell $ne $ne$ls180.v:7551$2428
+  attribute \src "ls180.v:7539.9-7539.43"
+  cell $ne $ne$ls180.v:7539$2416
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -105703,10 +105679,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_count
     connect \B 1'0
-    connect \Y $ne$ls180.v:7551$2428_Y
+    connect \Y $ne$ls180.v:7539$2416_Y
   end
-  attribute \src "ls180.v:7587.8-7587.44"
-  cell $ne $ne$ls180.v:7587$2435
+  attribute \src "ls180.v:7575.8-7575.44"
+  cell $ne $ne$ls180.v:7575$2423
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -105714,10 +105690,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_counter
     connect \B 1'0
-    connect \Y $ne$ls180.v:7587$2435_Y
+    connect \Y $ne$ls180.v:7575$2423_Y
   end
-  attribute \src "ls180.v:8525.9-8525.47"
-  cell $ne $ne$ls180.v:8525$2650
+  attribute \src "ls180.v:8513.9-8513.47"
+  cell $ne $ne$ls180.v:8513$2638
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -105725,7 +105701,7 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdcore_crc16_checker_cnt
     connect \B 4'1010
-    connect \Y $ne$ls180.v:8525$2650_Y
+    connect \Y $ne$ls180.v:8513$2638_Y
   end
   attribute \src "ls180.v:2777.45-2777.80"
   cell $not $not$ls180.v:2777$14
@@ -107911,520 +107887,520 @@ module \ls180
     connect \A \main_sdphy_clocker_clk0
     connect \Y $not$ls180.v:7416$2372_Y
   end
-  attribute \src "ls180.v:7507.72-7507.101"
-  cell $not $not$ls180.v:7507$2417
+  attribute \src "ls180.v:7495.72-7495.101"
+  cell $not $not$ls180.v:7495$2405
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_ram_bus_ack
-    connect \Y $not$ls180.v:7507$2417_Y
+    connect \Y $not$ls180.v:7495$2405_Y
   end
-  attribute \src "ls180.v:7526.8-7526.38"
-  cell $not $not$ls180.v:7526$2421
+  attribute \src "ls180.v:7514.8-7514.38"
+  cell $not $not$ls180.v:7514$2409
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_zero_trigger
-    connect \Y $not$ls180.v:7526$2421_Y
+    connect \Y $not$ls180.v:7514$2409_Y
   end
-  attribute \src "ls180.v:7534.32-7534.55"
-  cell $not $not$ls180.v:7534$2423
+  attribute \src "ls180.v:7522.32-7522.55"
+  cell $not $not$ls180.v:7522$2411
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_timer_done0
-    connect \Y $not$ls180.v:7534$2423_Y
+    connect \Y $not$ls180.v:7522$2411_Y
   end
-  attribute \src "ls180.v:7604.136-7604.189"
-  cell $not $not$ls180.v:7604$2438
+  attribute \src "ls180.v:7592.136-7592.189"
+  cell $not $not$ls180.v:7592$2426
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7604$2438_Y
+    connect \Y $not$ls180.v:7592$2426_Y
   end
-  attribute \src "ls180.v:7610.136-7610.189"
-  cell $not $not$ls180.v:7610$2443
+  attribute \src "ls180.v:7598.136-7598.189"
+  cell $not $not$ls180.v:7598$2431
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7610$2443_Y
+    connect \Y $not$ls180.v:7598$2431_Y
   end
-  attribute \src "ls180.v:7611.8-7611.61"
-  cell $not $not$ls180.v:7611$2445
+  attribute \src "ls180.v:7599.8-7599.61"
+  cell $not $not$ls180.v:7599$2433
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
-    connect \Y $not$ls180.v:7611$2445_Y
+    connect \Y $not$ls180.v:7599$2433_Y
   end
-  attribute \src "ls180.v:7619.8-7619.56"
-  cell $not $not$ls180.v:7619$2448
+  attribute \src "ls180.v:7607.8-7607.56"
+  cell $not $not$ls180.v:7607$2436
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:7619$2448_Y
+    connect \Y $not$ls180.v:7607$2436_Y
   end
-  attribute \src "ls180.v:7634.8-7634.46"
-  cell $not $not$ls180.v:7634$2450
+  attribute \src "ls180.v:7622.8-7622.46"
+  cell $not $not$ls180.v:7622$2438
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine0_twtpcon_ready
-    connect \Y $not$ls180.v:7634$2450_Y
+    connect \Y $not$ls180.v:7622$2438_Y
   end
-  attribute \src "ls180.v:7650.136-7650.189"
-  cell $not $not$ls180.v:7650$2454
+  attribute \src "ls180.v:7638.136-7638.189"
+  cell $not $not$ls180.v:7638$2442
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7650$2454_Y
+    connect \Y $not$ls180.v:7638$2442_Y
   end
-  attribute \src "ls180.v:7656.136-7656.189"
-  cell $not $not$ls180.v:7656$2459
+  attribute \src "ls180.v:7644.136-7644.189"
+  cell $not $not$ls180.v:7644$2447
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7656$2459_Y
+    connect \Y $not$ls180.v:7644$2447_Y
   end
-  attribute \src "ls180.v:7657.8-7657.61"
-  cell $not $not$ls180.v:7657$2461
+  attribute \src "ls180.v:7645.8-7645.61"
+  cell $not $not$ls180.v:7645$2449
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
-    connect \Y $not$ls180.v:7657$2461_Y
+    connect \Y $not$ls180.v:7645$2449_Y
   end
-  attribute \src "ls180.v:7665.8-7665.56"
-  cell $not $not$ls180.v:7665$2464
+  attribute \src "ls180.v:7653.8-7653.56"
+  cell $not $not$ls180.v:7653$2452
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:7665$2464_Y
+    connect \Y $not$ls180.v:7653$2452_Y
   end
-  attribute \src "ls180.v:7680.8-7680.46"
-  cell $not $not$ls180.v:7680$2466
+  attribute \src "ls180.v:7668.8-7668.46"
+  cell $not $not$ls180.v:7668$2454
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine1_twtpcon_ready
-    connect \Y $not$ls180.v:7680$2466_Y
+    connect \Y $not$ls180.v:7668$2454_Y
   end
-  attribute \src "ls180.v:7696.136-7696.189"
-  cell $not $not$ls180.v:7696$2470
+  attribute \src "ls180.v:7684.136-7684.189"
+  cell $not $not$ls180.v:7684$2458
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7696$2470_Y
+    connect \Y $not$ls180.v:7684$2458_Y
   end
-  attribute \src "ls180.v:7702.136-7702.189"
-  cell $not $not$ls180.v:7702$2475
+  attribute \src "ls180.v:7690.136-7690.189"
+  cell $not $not$ls180.v:7690$2463
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7702$2475_Y
+    connect \Y $not$ls180.v:7690$2463_Y
   end
-  attribute \src "ls180.v:7703.8-7703.61"
-  cell $not $not$ls180.v:7703$2477
+  attribute \src "ls180.v:7691.8-7691.61"
+  cell $not $not$ls180.v:7691$2465
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
-    connect \Y $not$ls180.v:7703$2477_Y
+    connect \Y $not$ls180.v:7691$2465_Y
   end
-  attribute \src "ls180.v:7711.8-7711.56"
-  cell $not $not$ls180.v:7711$2480
+  attribute \src "ls180.v:7699.8-7699.56"
+  cell $not $not$ls180.v:7699$2468
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:7711$2480_Y
+    connect \Y $not$ls180.v:7699$2468_Y
   end
-  attribute \src "ls180.v:7726.8-7726.46"
-  cell $not $not$ls180.v:7726$2482
+  attribute \src "ls180.v:7714.8-7714.46"
+  cell $not $not$ls180.v:7714$2470
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine2_twtpcon_ready
-    connect \Y $not$ls180.v:7726$2482_Y
+    connect \Y $not$ls180.v:7714$2470_Y
   end
-  attribute \src "ls180.v:7742.136-7742.189"
-  cell $not $not$ls180.v:7742$2486
+  attribute \src "ls180.v:7730.136-7730.189"
+  cell $not $not$ls180.v:7730$2474
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7742$2486_Y
+    connect \Y $not$ls180.v:7730$2474_Y
   end
-  attribute \src "ls180.v:7748.136-7748.189"
-  cell $not $not$ls180.v:7748$2491
+  attribute \src "ls180.v:7736.136-7736.189"
+  cell $not $not$ls180.v:7736$2479
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:7748$2491_Y
+    connect \Y $not$ls180.v:7736$2479_Y
   end
-  attribute \src "ls180.v:7749.8-7749.61"
-  cell $not $not$ls180.v:7749$2493
+  attribute \src "ls180.v:7737.8-7737.61"
+  cell $not $not$ls180.v:7737$2481
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
-    connect \Y $not$ls180.v:7749$2493_Y
+    connect \Y $not$ls180.v:7737$2481_Y
   end
-  attribute \src "ls180.v:7757.8-7757.56"
-  cell $not $not$ls180.v:7757$2496
+  attribute \src "ls180.v:7745.8-7745.56"
+  cell $not $not$ls180.v:7745$2484
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:7757$2496_Y
+    connect \Y $not$ls180.v:7745$2484_Y
   end
-  attribute \src "ls180.v:7772.8-7772.46"
-  cell $not $not$ls180.v:7772$2498
+  attribute \src "ls180.v:7760.8-7760.46"
+  cell $not $not$ls180.v:7760$2486
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_bankmachine3_twtpcon_ready
-    connect \Y $not$ls180.v:7772$2498_Y
+    connect \Y $not$ls180.v:7760$2486_Y
   end
-  attribute \src "ls180.v:7780.7-7780.22"
-  cell $not $not$ls180.v:7780$2501
+  attribute \src "ls180.v:7768.7-7768.22"
+  cell $not $not$ls180.v:7768$2489
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_en0
-    connect \Y $not$ls180.v:7780$2501_Y
+    connect \Y $not$ls180.v:7768$2489_Y
   end
-  attribute \src "ls180.v:7783.8-7783.29"
-  cell $not $not$ls180.v:7783$2502
+  attribute \src "ls180.v:7771.8-7771.29"
+  cell $not $not$ls180.v:7771$2490
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_max_time0
-    connect \Y $not$ls180.v:7783$2502_Y
+    connect \Y $not$ls180.v:7771$2490_Y
   end
-  attribute \src "ls180.v:7787.7-7787.22"
-  cell $not $not$ls180.v:7787$2504
+  attribute \src "ls180.v:7775.7-7775.22"
+  cell $not $not$ls180.v:7775$2492
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_en1
-    connect \Y $not$ls180.v:7787$2504_Y
+    connect \Y $not$ls180.v:7775$2492_Y
   end
-  attribute \src "ls180.v:7790.8-7790.29"
-  cell $not $not$ls180.v:7790$2505
+  attribute \src "ls180.v:7778.8-7778.29"
+  cell $not $not$ls180.v:7778$2493
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_max_time1
-    connect \Y $not$ls180.v:7790$2505_Y
+    connect \Y $not$ls180.v:7778$2493_Y
   end
-  attribute \src "ls180.v:7909.30-7909.60"
-  cell $not $not$ls180.v:7909$2507
+  attribute \src "ls180.v:7897.30-7897.60"
+  cell $not $not$ls180.v:7897$2495
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_sync_rhs_array_muxed2
-    connect \Y $not$ls180.v:7909$2507_Y
+    connect \Y $not$ls180.v:7897$2495_Y
   end
-  attribute \src "ls180.v:7910.30-7910.60"
-  cell $not $not$ls180.v:7910$2508
+  attribute \src "ls180.v:7898.30-7898.60"
+  cell $not $not$ls180.v:7898$2496
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_sync_rhs_array_muxed3
-    connect \Y $not$ls180.v:7910$2508_Y
+    connect \Y $not$ls180.v:7898$2496_Y
   end
-  attribute \src "ls180.v:7911.29-7911.59"
-  cell $not $not$ls180.v:7911$2509
+  attribute \src "ls180.v:7899.29-7899.59"
+  cell $not $not$ls180.v:7899$2497
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_sync_rhs_array_muxed4
-    connect \Y $not$ls180.v:7911$2509_Y
+    connect \Y $not$ls180.v:7899$2497_Y
   end
-  attribute \src "ls180.v:7922.8-7922.33"
-  cell $not $not$ls180.v:7922$2510
+  attribute \src "ls180.v:7910.8-7910.33"
+  cell $not $not$ls180.v:7910$2498
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_tccdcon_ready
-    connect \Y $not$ls180.v:7922$2510_Y
+    connect \Y $not$ls180.v:7910$2498_Y
   end
-  attribute \src "ls180.v:7937.8-7937.33"
-  cell $not $not$ls180.v:7937$2513
+  attribute \src "ls180.v:7925.8-7925.33"
+  cell $not $not$ls180.v:7925$2501
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdram_twtrcon_ready
-    connect \Y $not$ls180.v:7937$2513_Y
+    connect \Y $not$ls180.v:7925$2501_Y
   end
-  attribute \src "ls180.v:7973.36-7973.58"
-  cell $not $not$ls180.v:7973$2543
+  attribute \src "ls180.v:7961.36-7961.58"
+  cell $not $not$ls180.v:7961$2531
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_tx_busy
-    connect \Y $not$ls180.v:7973$2543_Y
+    connect \Y $not$ls180.v:7961$2531_Y
   end
-  attribute \src "ls180.v:7973.64-7973.89"
-  cell $not $not$ls180.v:7973$2545
+  attribute \src "ls180.v:7961.64-7961.89"
+  cell $not $not$ls180.v:7961$2533
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_sink_ready
-    connect \Y $not$ls180.v:7973$2545_Y
+    connect \Y $not$ls180.v:7961$2533_Y
   end
-  attribute \src "ls180.v:8002.7-8002.29"
-  cell $not $not$ls180.v:8002$2552
+  attribute \src "ls180.v:7990.7-7990.29"
+  cell $not $not$ls180.v:7990$2540
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_rx_busy
-    connect \Y $not$ls180.v:8002$2552_Y
+    connect \Y $not$ls180.v:7990$2540_Y
   end
-  attribute \src "ls180.v:8003.9-8003.26"
-  cell $not $not$ls180.v:8003$2553
+  attribute \src "ls180.v:7991.9-7991.26"
+  cell $not $not$ls180.v:7991$2541
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_phy_rx
-    connect \Y $not$ls180.v:8003$2553_Y
+    connect \Y $not$ls180.v:7991$2541_Y
   end
-  attribute \src "ls180.v:8036.8-8036.29"
-  cell $not $not$ls180.v:8036$2559
+  attribute \src "ls180.v:8024.8-8024.29"
+  cell $not $not$ls180.v:8024$2547
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_trigger
-    connect \Y $not$ls180.v:8036$2559_Y
+    connect \Y $not$ls180.v:8024$2547_Y
   end
-  attribute \src "ls180.v:8043.8-8043.29"
-  cell $not $not$ls180.v:8043$2561
+  attribute \src "ls180.v:8031.8-8031.29"
+  cell $not $not$ls180.v:8031$2549
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_trigger
-    connect \Y $not$ls180.v:8043$2561_Y
+    connect \Y $not$ls180.v:8031$2549_Y
   end
-  attribute \src "ls180.v:8053.80-8053.106"
-  cell $not $not$ls180.v:8053$2564
+  attribute \src "ls180.v:8041.80-8041.106"
+  cell $not $not$ls180.v:8041$2552
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_replace
-    connect \Y $not$ls180.v:8053$2564_Y
+    connect \Y $not$ls180.v:8041$2552_Y
   end
-  attribute \src "ls180.v:8059.80-8059.106"
-  cell $not $not$ls180.v:8059$2569
+  attribute \src "ls180.v:8047.80-8047.106"
+  cell $not $not$ls180.v:8047$2557
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_replace
-    connect \Y $not$ls180.v:8059$2569_Y
+    connect \Y $not$ls180.v:8047$2557_Y
   end
-  attribute \src "ls180.v:8060.8-8060.34"
-  cell $not $not$ls180.v:8060$2571
+  attribute \src "ls180.v:8048.8-8048.34"
+  cell $not $not$ls180.v:8048$2559
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_tx_fifo_do_read
-    connect \Y $not$ls180.v:8060$2571_Y
+    connect \Y $not$ls180.v:8048$2559_Y
   end
-  attribute \src "ls180.v:8075.80-8075.106"
-  cell $not $not$ls180.v:8075$2575
+  attribute \src "ls180.v:8063.80-8063.106"
+  cell $not $not$ls180.v:8063$2563
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_replace
-    connect \Y $not$ls180.v:8075$2575_Y
+    connect \Y $not$ls180.v:8063$2563_Y
   end
-  attribute \src "ls180.v:8081.80-8081.106"
-  cell $not $not$ls180.v:8081$2580
+  attribute \src "ls180.v:8069.80-8069.106"
+  cell $not $not$ls180.v:8069$2568
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_replace
-    connect \Y $not$ls180.v:8081$2580_Y
+    connect \Y $not$ls180.v:8069$2568_Y
   end
-  attribute \src "ls180.v:8082.8-8082.34"
-  cell $not $not$ls180.v:8082$2582
+  attribute \src "ls180.v:8070.8-8070.34"
+  cell $not $not$ls180.v:8070$2570
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_uart_rx_fifo_do_read
-    connect \Y $not$ls180.v:8082$2582_Y
+    connect \Y $not$ls180.v:8070$2570_Y
   end
-  attribute \src "ls180.v:8113.22-8113.41"
-  cell $not $not$ls180.v:8113$2586
+  attribute \src "ls180.v:8101.22-8101.41"
+  cell $not $not$ls180.v:8101$2574
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_spimaster6_cs
-    connect \Y $not$ls180.v:8113$2586_Y
+    connect \Y $not$ls180.v:8101$2574_Y
   end
-  attribute \src "ls180.v:8113.46-8113.73"
-  cell $not $not$ls180.v:8113$2587
+  attribute \src "ls180.v:8101.46-8101.73"
+  cell $not $not$ls180.v:8101$2575
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_spimaster26_cs_enable
-    connect \Y $not$ls180.v:8113$2587_Y
+    connect \Y $not$ls180.v:8101$2575_Y
   end
-  attribute \src "ls180.v:8148.22-8148.40"
-  cell $not $not$ls180.v:8148$2591
+  attribute \src "ls180.v:8136.22-8136.40"
+  cell $not $not$ls180.v:8136$2579
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_spisdcard_cs
-    connect \Y $not$ls180.v:8148$2591_Y
+    connect \Y $not$ls180.v:8136$2579_Y
   end
-  attribute \src "ls180.v:8148.45-8148.70"
-  cell $not $not$ls180.v:8148$2592
+  attribute \src "ls180.v:8136.45-8136.70"
+  cell $not $not$ls180.v:8136$2580
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_spisdcard_cs_enable
-    connect \Y $not$ls180.v:8148$2592_Y
+    connect \Y $not$ls180.v:8136$2580_Y
   end
-  attribute \src "ls180.v:8202.7-8202.31"
-  cell $not $not$ls180.v:8202$2603
+  attribute \src "ls180.v:8190.7-8190.31"
+  cell $not $not$ls180.v:8190$2591
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_clocker_stop
-    connect \Y $not$ls180.v:8202$2603_Y
+    connect \Y $not$ls180.v:8190$2591_Y
   end
-  attribute \src "ls180.v:8274.8-8274.46"
-  cell $not $not$ls180.v:8274$2615
+  attribute \src "ls180.v:8262.8-8262.46"
+  cell $not $not$ls180.v:8262$2603
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_buf_source_valid
-    connect \Y $not$ls180.v:8274$2615_Y
+    connect \Y $not$ls180.v:8262$2603_Y
   end
-  attribute \src "ls180.v:8355.8-8355.47"
-  cell $not $not$ls180.v:8355$2627
+  attribute \src "ls180.v:8343.8-8343.47"
+  cell $not $not$ls180.v:8343$2615
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_buf_source_valid
-    connect \Y $not$ls180.v:8355$2627_Y
+    connect \Y $not$ls180.v:8343$2615_Y
   end
-  attribute \src "ls180.v:8416.8-8416.48"
-  cell $not $not$ls180.v:8416$2639
+  attribute \src "ls180.v:8404.8-8404.48"
+  cell $not $not$ls180.v:8404$2627
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_buf_source_valid
-    connect \Y $not$ls180.v:8416$2639_Y
+    connect \Y $not$ls180.v:8404$2627_Y
   end
-  attribute \src "ls180.v:8586.88-8586.118"
-  cell $not $not$ls180.v:8586$2653
+  attribute \src "ls180.v:8574.88-8574.118"
+  cell $not $not$ls180.v:8574$2641
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_replace
-    connect \Y $not$ls180.v:8586$2653_Y
+    connect \Y $not$ls180.v:8574$2641_Y
   end
-  attribute \src "ls180.v:8592.88-8592.118"
-  cell $not $not$ls180.v:8592$2658
+  attribute \src "ls180.v:8580.88-8580.118"
+  cell $not $not$ls180.v:8580$2646
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_replace
-    connect \Y $not$ls180.v:8592$2658_Y
+    connect \Y $not$ls180.v:8580$2646_Y
   end
-  attribute \src "ls180.v:8593.8-8593.38"
-  cell $not $not$ls180.v:8593$2660
+  attribute \src "ls180.v:8581.8-8581.38"
+  cell $not $not$ls180.v:8581$2648
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_fifo_do_read
-    connect \Y $not$ls180.v:8593$2660_Y
+    connect \Y $not$ls180.v:8581$2648_Y
   end
-  attribute \src "ls180.v:8672.88-8672.118"
-  cell $not $not$ls180.v:8672$2675
+  attribute \src "ls180.v:8660.88-8660.118"
+  cell $not $not$ls180.v:8660$2663
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_replace
-    connect \Y $not$ls180.v:8672$2675_Y
+    connect \Y $not$ls180.v:8660$2663_Y
   end
-  attribute \src "ls180.v:8678.88-8678.118"
-  cell $not $not$ls180.v:8678$2680
+  attribute \src "ls180.v:8666.88-8666.118"
+  cell $not $not$ls180.v:8666$2668
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_replace
-    connect \Y $not$ls180.v:8678$2680_Y
+    connect \Y $not$ls180.v:8666$2668_Y
   end
-  attribute \src "ls180.v:8679.8-8679.38"
-  cell $not $not$ls180.v:8679$2682
+  attribute \src "ls180.v:8667.8-8667.38"
+  cell $not $not$ls180.v:8667$2670
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \main_sdmem2block_fifo_do_read
-    connect \Y $not$ls180.v:8679$2682_Y
+    connect \Y $not$ls180.v:8667$2670_Y
   end
-  attribute \src "ls180.v:8699.9-8699.28"
-  cell $not $not$ls180.v:8699$2685
+  attribute \src "ls180.v:8687.9-8687.28"
+  cell $not $not$ls180.v:8687$2673
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_request [0]
-    connect \Y $not$ls180.v:8699$2685_Y
+    connect \Y $not$ls180.v:8687$2673_Y
   end
-  attribute \src "ls180.v:8718.9-8718.28"
-  cell $not $not$ls180.v:8718$2686
+  attribute \src "ls180.v:8706.9-8706.28"
+  cell $not $not$ls180.v:8706$2674
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_request [1]
-    connect \Y $not$ls180.v:8718$2686_Y
+    connect \Y $not$ls180.v:8706$2674_Y
   end
-  attribute \src "ls180.v:8737.9-8737.28"
-  cell $not $not$ls180.v:8737$2687
+  attribute \src "ls180.v:8725.9-8725.28"
+  cell $not $not$ls180.v:8725$2675
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_request [2]
-    connect \Y $not$ls180.v:8737$2687_Y
+    connect \Y $not$ls180.v:8725$2675_Y
   end
-  attribute \src "ls180.v:8756.9-8756.28"
-  cell $not $not$ls180.v:8756$2688
+  attribute \src "ls180.v:8744.9-8744.28"
+  cell $not $not$ls180.v:8744$2676
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_request [3]
-    connect \Y $not$ls180.v:8756$2688_Y
+    connect \Y $not$ls180.v:8744$2676_Y
   end
-  attribute \src "ls180.v:8775.9-8775.28"
-  cell $not $not$ls180.v:8775$2689
+  attribute \src "ls180.v:8763.9-8763.28"
+  cell $not $not$ls180.v:8763$2677
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_request [4]
-    connect \Y $not$ls180.v:8775$2689_Y
+    connect \Y $not$ls180.v:8763$2677_Y
   end
-  attribute \src "ls180.v:8796.8-8796.21"
-  cell $not $not$ls180.v:8796$2690
+  attribute \src "ls180.v:8784.8-8784.21"
+  cell $not $not$ls180.v:8784$2678
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \builder_done
-    connect \Y $not$ls180.v:8796$2690_Y
+    connect \Y $not$ls180.v:8784$2678_Y
   end
-  attribute \src "ls180.v:10295.8-10295.51"
-  cell $or $or$ls180.v:10295$2762
+  attribute \src "ls180.v:10283.8-10283.51"
+  cell $or $or$ls180.v:10283$2750
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -108432,7 +108408,7 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sys_rst_1
     connect \B \main_libresocsim_libresoc_reset
-    connect \Y $or$ls180.v:10295$2762_Y
+    connect \Y $or$ls180.v:10283$2750_Y
   end
   attribute \src "ls180.v:2818.10-2818.96"
   cell $or $or$ls180.v:2818$21
@@ -110480,140 +110456,8 @@ module \ls180
     connect \B \main_libresocsim_libresoc_interrupt [0]
     connect \Y $or$ls180.v:7455$2398_Y
   end
-  attribute \src "ls180.v:7456.21-7456.73"
+  attribute \src "ls180.v:7456.7-7456.93"
   cell $or $or$ls180.v:7456$2399
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \main_nc [24]
-    connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7456$2399_Y
-  end
-  attribute \src "ls180.v:7457.21-7457.73"
-  cell $or $or$ls180.v:7457$2400
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \main_nc [25]
-    connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7457$2400_Y
-  end
-  attribute \src "ls180.v:7458.21-7458.73"
-  cell $or $or$ls180.v:7458$2401
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \main_nc [26]
-    connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7458$2401_Y
-  end
-  attribute \src "ls180.v:7459.21-7459.73"
-  cell $or $or$ls180.v:7459$2402
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \main_nc [27]
-    connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7459$2402_Y
-  end
-  attribute \src "ls180.v:7460.21-7460.73"
-  cell $or $or$ls180.v:7460$2403
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \main_nc [28]
-    connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7460$2403_Y
-  end
-  attribute \src "ls180.v:7461.21-7461.73"
-  cell $or $or$ls180.v:7461$2404
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \main_nc [29]
-    connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7461$2404_Y
-  end
-  attribute \src "ls180.v:7462.21-7462.73"
-  cell $or $or$ls180.v:7462$2405
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \main_nc [30]
-    connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7462$2405_Y
-  end
-  attribute \src "ls180.v:7463.21-7463.73"
-  cell $or $or$ls180.v:7463$2406
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \main_nc [31]
-    connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7463$2406_Y
-  end
-  attribute \src "ls180.v:7464.21-7464.73"
-  cell $or $or$ls180.v:7464$2407
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \main_nc [32]
-    connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7464$2407_Y
-  end
-  attribute \src "ls180.v:7465.21-7465.73"
-  cell $or $or$ls180.v:7465$2408
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \main_nc [33]
-    connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7465$2408_Y
-  end
-  attribute \src "ls180.v:7466.21-7466.73"
-  cell $or $or$ls180.v:7466$2409
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \main_nc [34]
-    connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7466$2409_Y
-  end
-  attribute \src "ls180.v:7467.21-7467.73"
-  cell $or $or$ls180.v:7467$2410
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \main_nc [35]
-    connect \B \main_libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:7467$2410_Y
-  end
-  attribute \src "ls180.v:7468.7-7468.93"
-  cell $or $or$ls180.v:7468$2411
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110621,10 +110465,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_interface0_converted_interface_ack
     connect \B \main_libresocsim_converter0_skip
-    connect \Y $or$ls180.v:7468$2411_Y
+    connect \Y $or$ls180.v:7456$2399_Y
   end
-  attribute \src "ls180.v:7479.7-7479.93"
-  cell $or $or$ls180.v:7479$2412
+  attribute \src "ls180.v:7467.7-7467.93"
+  cell $or $or$ls180.v:7467$2400
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110632,10 +110476,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_interface1_converted_interface_ack
     connect \B \main_libresocsim_converter1_skip
-    connect \Y $or$ls180.v:7479$2412_Y
+    connect \Y $or$ls180.v:7467$2400_Y
   end
-  attribute \src "ls180.v:7490.7-7490.93"
-  cell $or $or$ls180.v:7490$2413
+  attribute \src "ls180.v:7478.7-7478.93"
+  cell $or $or$ls180.v:7478$2401
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110643,142 +110487,142 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_libresocsim_interface2_converted_interface_ack
     connect \B \main_libresocsim_converter2_skip
-    connect \Y $or$ls180.v:7490$2413_Y
+    connect \Y $or$ls180.v:7478$2401_Y
   end
-  attribute \src "ls180.v:7619.7-7619.107"
-  cell $or $or$ls180.v:7619$2449
+  attribute \src "ls180.v:7607.7-7607.107"
+  cell $or $or$ls180.v:7607$2437
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:7619$2448_Y
+    connect \A $not$ls180.v:7607$2436_Y
     connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:7619$2449_Y
+    connect \Y $or$ls180.v:7607$2437_Y
   end
-  attribute \src "ls180.v:7665.7-7665.107"
-  cell $or $or$ls180.v:7665$2465
+  attribute \src "ls180.v:7653.7-7653.107"
+  cell $or $or$ls180.v:7653$2453
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:7665$2464_Y
+    connect \A $not$ls180.v:7653$2452_Y
     connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:7665$2465_Y
+    connect \Y $or$ls180.v:7653$2453_Y
   end
-  attribute \src "ls180.v:7711.7-7711.107"
-  cell $or $or$ls180.v:7711$2481
+  attribute \src "ls180.v:7699.7-7699.107"
+  cell $or $or$ls180.v:7699$2469
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:7711$2480_Y
+    connect \A $not$ls180.v:7699$2468_Y
     connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:7711$2481_Y
+    connect \Y $or$ls180.v:7699$2469_Y
   end
-  attribute \src "ls180.v:7757.7-7757.107"
-  cell $or $or$ls180.v:7757$2497
+  attribute \src "ls180.v:7745.7-7745.107"
+  cell $or $or$ls180.v:7745$2485
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:7757$2496_Y
+    connect \A $not$ls180.v:7745$2484_Y
     connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:7757$2497_Y
+    connect \Y $or$ls180.v:7745$2485_Y
   end
-  attribute \src "ls180.v:7945.40-7945.125"
-  cell $or $or$ls180.v:7945$2518
+  attribute \src "ls180.v:7933.40-7933.125"
+  cell $or $or$ls180.v:7933$2506
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A 1'0
-    connect \B $and$ls180.v:7945$2517_Y
-    connect \Y $or$ls180.v:7945$2518_Y
+    connect \B $and$ls180.v:7933$2505_Y
+    connect \Y $or$ls180.v:7933$2506_Y
   end
-  attribute \src "ls180.v:7945.39-7945.207"
-  cell $or $or$ls180.v:7945$2521
+  attribute \src "ls180.v:7933.39-7933.207"
+  cell $or $or$ls180.v:7933$2509
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:7945$2518_Y
-    connect \B $and$ls180.v:7945$2520_Y
-    connect \Y $or$ls180.v:7945$2521_Y
+    connect \A $or$ls180.v:7933$2506_Y
+    connect \B $and$ls180.v:7933$2508_Y
+    connect \Y $or$ls180.v:7933$2509_Y
   end
-  attribute \src "ls180.v:7945.38-7945.289"
-  cell $or $or$ls180.v:7945$2524
+  attribute \src "ls180.v:7933.38-7933.289"
+  cell $or $or$ls180.v:7933$2512
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:7945$2521_Y
-    connect \B $and$ls180.v:7945$2523_Y
-    connect \Y $or$ls180.v:7945$2524_Y
+    connect \A $or$ls180.v:7933$2509_Y
+    connect \B $and$ls180.v:7933$2511_Y
+    connect \Y $or$ls180.v:7933$2512_Y
   end
-  attribute \src "ls180.v:7945.37-7945.371"
-  cell $or $or$ls180.v:7945$2527
+  attribute \src "ls180.v:7933.37-7933.371"
+  cell $or $or$ls180.v:7933$2515
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:7945$2524_Y
-    connect \B $and$ls180.v:7945$2526_Y
-    connect \Y $or$ls180.v:7945$2527_Y
+    connect \A $or$ls180.v:7933$2512_Y
+    connect \B $and$ls180.v:7933$2514_Y
+    connect \Y $or$ls180.v:7933$2515_Y
   end
-  attribute \src "ls180.v:7946.41-7946.126"
-  cell $or $or$ls180.v:7946$2530
+  attribute \src "ls180.v:7934.41-7934.126"
+  cell $or $or$ls180.v:7934$2518
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A 1'0
-    connect \B $and$ls180.v:7946$2529_Y
-    connect \Y $or$ls180.v:7946$2530_Y
+    connect \B $and$ls180.v:7934$2517_Y
+    connect \Y $or$ls180.v:7934$2518_Y
   end
-  attribute \src "ls180.v:7946.40-7946.208"
-  cell $or $or$ls180.v:7946$2533
+  attribute \src "ls180.v:7934.40-7934.208"
+  cell $or $or$ls180.v:7934$2521
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:7946$2530_Y
-    connect \B $and$ls180.v:7946$2532_Y
-    connect \Y $or$ls180.v:7946$2533_Y
+    connect \A $or$ls180.v:7934$2518_Y
+    connect \B $and$ls180.v:7934$2520_Y
+    connect \Y $or$ls180.v:7934$2521_Y
   end
-  attribute \src "ls180.v:7946.39-7946.290"
-  cell $or $or$ls180.v:7946$2536
+  attribute \src "ls180.v:7934.39-7934.290"
+  cell $or $or$ls180.v:7934$2524
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:7946$2533_Y
-    connect \B $and$ls180.v:7946$2535_Y
-    connect \Y $or$ls180.v:7946$2536_Y
+    connect \A $or$ls180.v:7934$2521_Y
+    connect \B $and$ls180.v:7934$2523_Y
+    connect \Y $or$ls180.v:7934$2524_Y
   end
-  attribute \src "ls180.v:7946.38-7946.372"
-  cell $or $or$ls180.v:7946$2539
+  attribute \src "ls180.v:7934.38-7934.372"
+  cell $or $or$ls180.v:7934$2527
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:7946$2536_Y
-    connect \B $and$ls180.v:7946$2538_Y
-    connect \Y $or$ls180.v:7946$2539_Y
+    connect \A $or$ls180.v:7934$2524_Y
+    connect \B $and$ls180.v:7934$2526_Y
+    connect \Y $or$ls180.v:7934$2527_Y
   end
-  attribute \src "ls180.v:7950.7-7950.49"
-  cell $or $or$ls180.v:7950$2540
+  attribute \src "ls180.v:7938.7-7938.49"
+  cell $or $or$ls180.v:7938$2528
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110786,32 +110630,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_litedram_wb_ack
     connect \B \main_converter_skip
-    connect \Y $or$ls180.v:7950$2540_Y
+    connect \Y $or$ls180.v:7938$2528_Y
   end
-  attribute \src "ls180.v:8113.21-8113.74"
-  cell $or $or$ls180.v:8113$2588
+  attribute \src "ls180.v:8101.21-8101.74"
+  cell $or $or$ls180.v:8101$2576
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8113$2586_Y
-    connect \B $not$ls180.v:8113$2587_Y
-    connect \Y $or$ls180.v:8113$2588_Y
+    connect \A $not$ls180.v:8101$2574_Y
+    connect \B $not$ls180.v:8101$2575_Y
+    connect \Y $or$ls180.v:8101$2576_Y
   end
-  attribute \src "ls180.v:8148.21-8148.71"
-  cell $or $or$ls180.v:8148$2593
+  attribute \src "ls180.v:8136.21-8136.71"
+  cell $or $or$ls180.v:8136$2581
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8148$2591_Y
-    connect \B $not$ls180.v:8148$2592_Y
-    connect \Y $or$ls180.v:8148$2593_Y
+    connect \A $not$ls180.v:8136$2579_Y
+    connect \B $not$ls180.v:8136$2580_Y
+    connect \Y $or$ls180.v:8136$2581_Y
   end
-  attribute \src "ls180.v:8216.32-8216.85"
-  cell $or $or$ls180.v:8216$2605
+  attribute \src "ls180.v:8204.32-8204.85"
+  cell $or $or$ls180.v:8204$2593
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110819,21 +110663,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_start
     connect \B \main_sdphy_cmdr_cmdr_run
-    connect \Y $or$ls180.v:8216$2605_Y
+    connect \Y $or$ls180.v:8204$2593_Y
   end
-  attribute \src "ls180.v:8222.8-8222.97"
-  cell $or $or$ls180.v:8222$2607
+  attribute \src "ls180.v:8210.8-8210.97"
+  cell $or $or$ls180.v:8210$2595
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:8222$2606_Y
+    connect \A $eq$ls180.v:8210$2594_Y
     connect \B \main_sdphy_cmdr_cmdr_converter_sink_last
-    connect \Y $or$ls180.v:8222$2607_Y
+    connect \Y $or$ls180.v:8210$2595_Y
   end
-  attribute \src "ls180.v:8239.52-8239.139"
-  cell $or $or$ls180.v:8239$2612
+  attribute \src "ls180.v:8227.52-8227.139"
+  cell $or $or$ls180.v:8227$2600
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110841,10 +110685,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_sink_first
     connect \B \main_sdphy_cmdr_cmdr_converter_source_first
-    connect \Y $or$ls180.v:8239$2612_Y
+    connect \Y $or$ls180.v:8227$2600_Y
   end
-  attribute \src "ls180.v:8240.51-8240.136"
-  cell $or $or$ls180.v:8240$2613
+  attribute \src "ls180.v:8228.51-8228.136"
+  cell $or $or$ls180.v:8228$2601
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110852,21 +110696,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_cmdr_cmdr_converter_sink_last
     connect \B \main_sdphy_cmdr_cmdr_converter_source_last
-    connect \Y $or$ls180.v:8240$2613_Y
+    connect \Y $or$ls180.v:8228$2601_Y
   end
-  attribute \src "ls180.v:8274.7-8274.87"
-  cell $or $or$ls180.v:8274$2616
+  attribute \src "ls180.v:8262.7-8262.87"
+  cell $or $or$ls180.v:8262$2604
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8274$2615_Y
+    connect \A $not$ls180.v:8262$2603_Y
     connect \B \main_sdphy_cmdr_cmdr_buf_source_ready
-    connect \Y $or$ls180.v:8274$2616_Y
+    connect \Y $or$ls180.v:8262$2604_Y
   end
-  attribute \src "ls180.v:8297.33-8297.88"
-  cell $or $or$ls180.v:8297$2617
+  attribute \src "ls180.v:8285.33-8285.88"
+  cell $or $or$ls180.v:8285$2605
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110874,21 +110718,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_start
     connect \B \main_sdphy_dataw_crcr_run
-    connect \Y $or$ls180.v:8297$2617_Y
+    connect \Y $or$ls180.v:8285$2605_Y
   end
-  attribute \src "ls180.v:8303.8-8303.99"
-  cell $or $or$ls180.v:8303$2619
+  attribute \src "ls180.v:8291.8-8291.99"
+  cell $or $or$ls180.v:8291$2607
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:8303$2618_Y
+    connect \A $eq$ls180.v:8291$2606_Y
     connect \B \main_sdphy_dataw_crcr_converter_sink_last
-    connect \Y $or$ls180.v:8303$2619_Y
+    connect \Y $or$ls180.v:8291$2607_Y
   end
-  attribute \src "ls180.v:8320.53-8320.142"
-  cell $or $or$ls180.v:8320$2624
+  attribute \src "ls180.v:8308.53-8308.142"
+  cell $or $or$ls180.v:8308$2612
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110896,10 +110740,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_sink_first
     connect \B \main_sdphy_dataw_crcr_converter_source_first
-    connect \Y $or$ls180.v:8320$2624_Y
+    connect \Y $or$ls180.v:8308$2612_Y
   end
-  attribute \src "ls180.v:8321.52-8321.139"
-  cell $or $or$ls180.v:8321$2625
+  attribute \src "ls180.v:8309.52-8309.139"
+  cell $or $or$ls180.v:8309$2613
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110907,21 +110751,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_dataw_crcr_converter_sink_last
     connect \B \main_sdphy_dataw_crcr_converter_source_last
-    connect \Y $or$ls180.v:8321$2625_Y
+    connect \Y $or$ls180.v:8309$2613_Y
   end
-  attribute \src "ls180.v:8355.7-8355.89"
-  cell $or $or$ls180.v:8355$2628
+  attribute \src "ls180.v:8343.7-8343.89"
+  cell $or $or$ls180.v:8343$2616
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8355$2627_Y
+    connect \A $not$ls180.v:8343$2615_Y
     connect \B \main_sdphy_dataw_crcr_buf_source_ready
-    connect \Y $or$ls180.v:8355$2628_Y
+    connect \Y $or$ls180.v:8343$2616_Y
   end
-  attribute \src "ls180.v:8376.34-8376.91"
-  cell $or $or$ls180.v:8376$2629
+  attribute \src "ls180.v:8364.34-8364.91"
+  cell $or $or$ls180.v:8364$2617
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110929,21 +110773,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_start
     connect \B \main_sdphy_datar_datar_run
-    connect \Y $or$ls180.v:8376$2629_Y
+    connect \Y $or$ls180.v:8364$2617_Y
   end
-  attribute \src "ls180.v:8382.8-8382.101"
-  cell $or $or$ls180.v:8382$2631
+  attribute \src "ls180.v:8370.8-8370.101"
+  cell $or $or$ls180.v:8370$2619
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:8382$2630_Y
+    connect \A $eq$ls180.v:8370$2618_Y
     connect \B \main_sdphy_datar_datar_converter_sink_last
-    connect \Y $or$ls180.v:8382$2631_Y
+    connect \Y $or$ls180.v:8370$2619_Y
   end
-  attribute \src "ls180.v:8399.54-8399.145"
-  cell $or $or$ls180.v:8399$2636
+  attribute \src "ls180.v:8387.54-8387.145"
+  cell $or $or$ls180.v:8387$2624
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110951,10 +110795,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_sink_first
     connect \B \main_sdphy_datar_datar_converter_source_first
-    connect \Y $or$ls180.v:8399$2636_Y
+    connect \Y $or$ls180.v:8387$2624_Y
   end
-  attribute \src "ls180.v:8400.53-8400.142"
-  cell $or $or$ls180.v:8400$2637
+  attribute \src "ls180.v:8388.53-8388.142"
+  cell $or $or$ls180.v:8388$2625
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110962,32 +110806,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdphy_datar_datar_converter_sink_last
     connect \B \main_sdphy_datar_datar_converter_source_last
-    connect \Y $or$ls180.v:8400$2637_Y
+    connect \Y $or$ls180.v:8388$2625_Y
   end
-  attribute \src "ls180.v:8416.7-8416.91"
-  cell $or $or$ls180.v:8416$2640
+  attribute \src "ls180.v:8404.7-8404.91"
+  cell $or $or$ls180.v:8404$2628
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:8416$2639_Y
+    connect \A $not$ls180.v:8404$2627_Y
     connect \B \main_sdphy_datar_datar_buf_source_ready
-    connect \Y $or$ls180.v:8416$2640_Y
+    connect \Y $or$ls180.v:8404$2628_Y
   end
-  attribute \src "ls180.v:8605.8-8605.89"
-  cell $or $or$ls180.v:8605$2664
+  attribute \src "ls180.v:8593.8-8593.89"
+  cell $or $or$ls180.v:8593$2652
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:8605$2663_Y
+    connect \A $eq$ls180.v:8593$2651_Y
     connect \B \main_sdblock2mem_converter_sink_last
-    connect \Y $or$ls180.v:8605$2664_Y
+    connect \Y $or$ls180.v:8593$2652_Y
   end
-  attribute \src "ls180.v:8622.48-8622.127"
-  cell $or $or$ls180.v:8622$2669
+  attribute \src "ls180.v:8610.48-8610.127"
+  cell $or $or$ls180.v:8610$2657
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110995,10 +110839,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_sink_first
     connect \B \main_sdblock2mem_converter_source_first
-    connect \Y $or$ls180.v:8622$2669_Y
+    connect \Y $or$ls180.v:8610$2657_Y
   end
-  attribute \src "ls180.v:8623.47-8623.124"
-  cell $or $or$ls180.v:8623$2670
+  attribute \src "ls180.v:8611.47-8611.124"
+  cell $or $or$ls180.v:8611$2658
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -111006,7 +110850,7 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdblock2mem_converter_sink_last
     connect \B \main_sdblock2mem_converter_source_last
-    connect \Y $or$ls180.v:8623$2670_Y
+    connect \Y $or$ls180.v:8611$2658_Y
   end
   attribute \src "ls180.v:3182.46-3182.94"
   cell $sshl $sshl$ls180.v:3182$83
@@ -111349,8 +111193,8 @@ module \ls180
     connect \B 1'1
     connect \Y $sub$ls180.v:5637$1019_Y
   end
-  attribute \src "ls180.v:7514.31-7514.60"
-  cell $sub $sub$ls180.v:7514$2420
+  attribute \src "ls180.v:7502.31-7502.60"
+  cell $sub $sub$ls180.v:7502$2408
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -111358,10 +111202,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_libresocsim_value
     connect \B 1'1
-    connect \Y $sub$ls180.v:7514$2420_Y
+    connect \Y $sub$ls180.v:7502$2408_Y
   end
-  attribute \src "ls180.v:7535.31-7535.61"
-  cell $sub $sub$ls180.v:7535$2425
+  attribute \src "ls180.v:7523.31-7523.61"
+  cell $sub $sub$ls180.v:7523$2413
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \B_SIGNED 0
@@ -111369,10 +111213,10 @@ module \ls180
     parameter \Y_WIDTH 10
     connect \A \main_sdram_timer_count1
     connect \B 1'1
-    connect \Y $sub$ls180.v:7535$2425_Y
+    connect \Y $sub$ls180.v:7523$2413_Y
   end
-  attribute \src "ls180.v:7541.34-7541.67"
-  cell $sub $sub$ls180.v:7541$2426
+  attribute \src "ls180.v:7529.34-7529.67"
+  cell $sub $sub$ls180.v:7529$2414
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -111380,10 +111224,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_postponer_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7541$2426_Y
+    connect \Y $sub$ls180.v:7529$2414_Y
   end
-  attribute \src "ls180.v:7552.36-7552.69"
-  cell $sub $sub$ls180.v:7552$2429
+  attribute \src "ls180.v:7540.36-7540.69"
+  cell $sub $sub$ls180.v:7540$2417
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -111391,10 +111235,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_sequencer_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7552$2429_Y
+    connect \Y $sub$ls180.v:7540$2417_Y
   end
-  attribute \src "ls180.v:7616.59-7616.116"
-  cell $sub $sub$ls180.v:7616$2447
+  attribute \src "ls180.v:7604.59-7604.116"
+  cell $sub $sub$ls180.v:7604$2435
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -111402,10 +111246,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:7616$2447_Y
+    connect \Y $sub$ls180.v:7604$2435_Y
   end
-  attribute \src "ls180.v:7635.46-7635.90"
-  cell $sub $sub$ls180.v:7635$2451
+  attribute \src "ls180.v:7623.46-7623.90"
+  cell $sub $sub$ls180.v:7623$2439
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -111413,10 +111257,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine0_twtpcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7635$2451_Y
+    connect \Y $sub$ls180.v:7623$2439_Y
   end
-  attribute \src "ls180.v:7662.59-7662.116"
-  cell $sub $sub$ls180.v:7662$2463
+  attribute \src "ls180.v:7650.59-7650.116"
+  cell $sub $sub$ls180.v:7650$2451
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -111424,10 +111268,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:7662$2463_Y
+    connect \Y $sub$ls180.v:7650$2451_Y
   end
-  attribute \src "ls180.v:7681.46-7681.90"
-  cell $sub $sub$ls180.v:7681$2467
+  attribute \src "ls180.v:7669.46-7669.90"
+  cell $sub $sub$ls180.v:7669$2455
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -111435,10 +111279,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine1_twtpcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7681$2467_Y
+    connect \Y $sub$ls180.v:7669$2455_Y
   end
-  attribute \src "ls180.v:7708.59-7708.116"
-  cell $sub $sub$ls180.v:7708$2479
+  attribute \src "ls180.v:7696.59-7696.116"
+  cell $sub $sub$ls180.v:7696$2467
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -111446,10 +111290,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:7708$2479_Y
+    connect \Y $sub$ls180.v:7696$2467_Y
   end
-  attribute \src "ls180.v:7727.46-7727.90"
-  cell $sub $sub$ls180.v:7727$2483
+  attribute \src "ls180.v:7715.46-7715.90"
+  cell $sub $sub$ls180.v:7715$2471
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -111457,10 +111301,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine2_twtpcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7727$2483_Y
+    connect \Y $sub$ls180.v:7715$2471_Y
   end
-  attribute \src "ls180.v:7754.59-7754.116"
-  cell $sub $sub$ls180.v:7754$2495
+  attribute \src "ls180.v:7742.59-7742.116"
+  cell $sub $sub$ls180.v:7742$2483
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -111468,10 +111312,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:7754$2495_Y
+    connect \Y $sub$ls180.v:7742$2483_Y
   end
-  attribute \src "ls180.v:7773.46-7773.90"
-  cell $sub $sub$ls180.v:7773$2499
+  attribute \src "ls180.v:7761.46-7761.90"
+  cell $sub $sub$ls180.v:7761$2487
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -111479,10 +111323,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_bankmachine3_twtpcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7773$2499_Y
+    connect \Y $sub$ls180.v:7761$2487_Y
   end
-  attribute \src "ls180.v:7784.25-7784.48"
-  cell $sub $sub$ls180.v:7784$2503
+  attribute \src "ls180.v:7772.25-7772.48"
+  cell $sub $sub$ls180.v:7772$2491
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -111490,10 +111334,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_sdram_time0
     connect \B 1'1
-    connect \Y $sub$ls180.v:7784$2503_Y
+    connect \Y $sub$ls180.v:7772$2491_Y
   end
-  attribute \src "ls180.v:7791.25-7791.48"
-  cell $sub $sub$ls180.v:7791$2506
+  attribute \src "ls180.v:7779.25-7779.48"
+  cell $sub $sub$ls180.v:7779$2494
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -111501,10 +111345,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \main_sdram_time1
     connect \B 1'1
-    connect \Y $sub$ls180.v:7791$2506_Y
+    connect \Y $sub$ls180.v:7779$2494_Y
   end
-  attribute \src "ls180.v:7923.33-7923.64"
-  cell $sub $sub$ls180.v:7923$2511
+  attribute \src "ls180.v:7911.33-7911.64"
+  cell $sub $sub$ls180.v:7911$2499
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -111512,10 +111356,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \main_sdram_tccdcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7923$2511_Y
+    connect \Y $sub$ls180.v:7911$2499_Y
   end
-  attribute \src "ls180.v:7938.33-7938.64"
-  cell $sub $sub$ls180.v:7938$2514
+  attribute \src "ls180.v:7926.33-7926.64"
+  cell $sub $sub$ls180.v:7926$2502
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -111523,10 +111367,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_sdram_twtrcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:7938$2514_Y
+    connect \Y $sub$ls180.v:7926$2502_Y
   end
-  attribute \src "ls180.v:8065.33-8065.64"
-  cell $sub $sub$ls180.v:8065$2573
+  attribute \src "ls180.v:8053.33-8053.64"
+  cell $sub $sub$ls180.v:8053$2561
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -111534,10 +111378,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_uart_tx_fifo_level0
     connect \B 1'1
-    connect \Y $sub$ls180.v:8065$2573_Y
+    connect \Y $sub$ls180.v:8053$2561_Y
   end
-  attribute \src "ls180.v:8087.33-8087.64"
-  cell $sub $sub$ls180.v:8087$2584
+  attribute \src "ls180.v:8075.33-8075.64"
+  cell $sub $sub$ls180.v:8075$2572
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -111545,10 +111389,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \main_uart_rx_fifo_level0
     connect \B 1'1
-    connect \Y $sub$ls180.v:8087$2584_Y
+    connect \Y $sub$ls180.v:8075$2572_Y
   end
-  attribute \src "ls180.v:8122.34-8122.66"
-  cell $sub $sub$ls180.v:8122$2589
+  attribute \src "ls180.v:8110.34-8110.66"
+  cell $sub $sub$ls180.v:8110$2577
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -111556,10 +111400,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_spimaster34_mosi_sel
     connect \B 1'1
-    connect \Y $sub$ls180.v:8122$2589_Y
+    connect \Y $sub$ls180.v:8110$2577_Y
   end
-  attribute \src "ls180.v:8157.32-8157.62"
-  cell $sub $sub$ls180.v:8157$2594
+  attribute \src "ls180.v:8145.32-8145.62"
+  cell $sub $sub$ls180.v:8145$2582
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -111567,10 +111411,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \main_spisdcard_mosi_sel
     connect \B 1'1
-    connect \Y $sub$ls180.v:8157$2594_Y
+    connect \Y $sub$ls180.v:8145$2582_Y
   end
-  attribute \src "ls180.v:8181.30-8181.53"
-  cell $sub $sub$ls180.v:8181$2597
+  attribute \src "ls180.v:8169.30-8169.53"
+  cell $sub $sub$ls180.v:8169$2585
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -111578,10 +111422,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_pwm0_period
     connect \B 1'1
-    connect \Y $sub$ls180.v:8181$2597_Y
+    connect \Y $sub$ls180.v:8169$2585_Y
   end
-  attribute \src "ls180.v:8195.30-8195.53"
-  cell $sub $sub$ls180.v:8195$2601
+  attribute \src "ls180.v:8183.30-8183.53"
+  cell $sub $sub$ls180.v:8183$2589
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -111589,10 +111433,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \main_pwm1_period
     connect \B 1'1
-    connect \Y $sub$ls180.v:8195$2601_Y
+    connect \Y $sub$ls180.v:8183$2589_Y
   end
-  attribute \src "ls180.v:8598.36-8598.70"
-  cell $sub $sub$ls180.v:8598$2662
+  attribute \src "ls180.v:8586.36-8586.70"
+  cell $sub $sub$ls180.v:8586$2650
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -111600,10 +111444,10 @@ module \ls180
     parameter \Y_WIDTH 6
     connect \A \main_sdblock2mem_fifo_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:8598$2662_Y
+    connect \Y $sub$ls180.v:8586$2650_Y
   end
-  attribute \src "ls180.v:8684.36-8684.70"
-  cell $sub $sub$ls180.v:8684$2684
+  attribute \src "ls180.v:8672.36-8672.70"
+  cell $sub $sub$ls180.v:8672$2672
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
@@ -111611,10 +111455,10 @@ module \ls180
     parameter \Y_WIDTH 6
     connect \A \main_sdmem2block_fifo_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:8684$2684_Y
+    connect \Y $sub$ls180.v:8672$2672_Y
   end
-  attribute \src "ls180.v:8797.22-8797.42"
-  cell $sub $sub$ls180.v:8797$2691
+  attribute \src "ls180.v:8785.22-8785.42"
+  cell $sub $sub$ls180.v:8785$2679
     parameter \A_SIGNED 0
     parameter \A_WIDTH 20
     parameter \B_SIGNED 0
@@ -111622,7 +111466,7 @@ module \ls180
     parameter \Y_WIDTH 20
     connect \A \builder_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:8797$2691_Y
+    connect \Y $sub$ls180.v:8785$2679_Y
   end
   attribute \src "ls180.v:4926.353-4926.425"
   cell $xor $xor$ls180.v:4926$710
@@ -113825,7 +113669,7 @@ module \ls180
     connect \Y $xor$ls180.v:5199$960_Y
   end
   attribute \module_not_derived 1
-  attribute \src "ls180.v:10195.13-10573.2"
+  attribute \src "ls180.v:10183.13-10561.2"
   cell \test_issuer \test_issuer
     connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck
     connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi
@@ -114025,7 +113869,7 @@ module \ls180
     connect \pwm_0__pad__o \pwm_1 [0]
     connect \pwm_1__core__o \pwm [1]
     connect \pwm_1__pad__o \pwm_1 [1]
-    connect \rst $or$ls180.v:10295$2762_Y
+    connect \rst $or$ls180.v:10283$2750_Y
     connect \sd0_clk__core__o \sdcard_clk
     connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
     connect \sd0_cmd__core__i \sdcard_cmd_i
@@ -114206,12 +114050,12 @@ module \ls180
     connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
   end
   attribute \src "ls180.v:0.0-0.0"
-  process $proc$ls180.v:0$3720
+  process $proc$ls180.v:0$3708
     sync always
     sync init
   end
   attribute \src "ls180.v:1000.12-1000.47"
-  process $proc$ls180.v:1000$3146
+  process $proc$ls180.v:1000$3134
     assign { } { }
     assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111
     sync always
@@ -114219,7 +114063,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1001.5-1001.33"
-  process $proc$ls180.v:1001$3147
+  process $proc$ls180.v:1001$3135
     assign { } { }
     assign $1\main_spimaster9_start[0:0] 1'0
     sync always
@@ -114227,7 +114071,7 @@ module \ls180
       update \main_spimaster9_start $1\main_spimaster9_start[0:0]
   end
   attribute \src "ls180.v:1003.12-1003.44"
-  process $proc$ls180.v:1003$3148
+  process $proc$ls180.v:1003$3136
     assign { } { }
     assign $1\main_spimaster11_storage[15:0] 16'0000000000000000
     sync always
@@ -114235,15 +114079,15 @@ module \ls180
       update \main_spimaster11_storage $1\main_spimaster11_storage[15:0]
   end
   attribute \src "ls180.v:1004.5-1004.31"
-  process $proc$ls180.v:1004$3149
+  process $proc$ls180.v:1004$3137
     assign { } { }
     assign $1\main_spimaster12_re[0:0] 1'0
     sync always
     sync init
       update \main_spimaster12_re $1\main_spimaster12_re[0:0]
   end
-  attribute \src "ls180.v:10059.1-10069.4"
-  process $proc$ls180.v:10059$2692
+  attribute \src "ls180.v:10047.1-10057.4"
+  process $proc$ls180.v:10047$2680
     assign { } { }
     assign { } { }
     assign { } { }
@@ -114257,386 +114101,386 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\mem$ls180.v:10067$4_ADDR[6:0]$2702 7'xxxxxxx
-    assign $0$memwr$\mem$ls180.v:10067$4_DATA[31:0]$2703 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\mem$ls180.v:10067$4_EN[31:0]$2704 0
-    assign $0$memwr$\mem$ls180.v:10065$3_ADDR[6:0]$2699 7'xxxxxxx
-    assign $0$memwr$\mem$ls180.v:10065$3_DATA[31:0]$2700 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\mem$ls180.v:10065$3_EN[31:0]$2701 0
-    assign $0$memwr$\mem$ls180.v:10063$2_ADDR[6:0]$2696 7'xxxxxxx
-    assign $0$memwr$\mem$ls180.v:10063$2_DATA[31:0]$2697 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\mem$ls180.v:10063$2_EN[31:0]$2698 0
-    assign $0$memwr$\mem$ls180.v:10061$1_ADDR[6:0]$2693 7'xxxxxxx
-    assign $0$memwr$\mem$ls180.v:10061$1_DATA[31:0]$2694 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\mem$ls180.v:10061$1_EN[31:0]$2695 0
+    assign $0$memwr$\mem$ls180.v:10055$4_ADDR[6:0]$2690 7'xxxxxxx
+    assign $0$memwr$\mem$ls180.v:10055$4_DATA[31:0]$2691 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10055$4_EN[31:0]$2692 0
+    assign $0$memwr$\mem$ls180.v:10053$3_ADDR[6:0]$2687 7'xxxxxxx
+    assign $0$memwr$\mem$ls180.v:10053$3_DATA[31:0]$2688 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10053$3_EN[31:0]$2689 0
+    assign $0$memwr$\mem$ls180.v:10051$2_ADDR[6:0]$2684 7'xxxxxxx
+    assign $0$memwr$\mem$ls180.v:10051$2_DATA[31:0]$2685 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10051$2_EN[31:0]$2686 0
+    assign $0$memwr$\mem$ls180.v:10049$1_ADDR[6:0]$2681 7'xxxxxxx
+    assign $0$memwr$\mem$ls180.v:10049$1_DATA[31:0]$2682 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10049$1_EN[31:0]$2683 0
     assign $0\memadr[6:0] \main_libresocsim_adr
-    attribute \src "ls180.v:10060.2-10061.65"
+    attribute \src "ls180.v:10048.2-10049.65"
     switch \main_libresocsim_we [0]
-      attribute \src "ls180.v:10060.6-10060.28"
+      attribute \src "ls180.v:10048.6-10048.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10061$1_ADDR[6:0]$2693 \main_libresocsim_adr
-        assign $0$memwr$\mem$ls180.v:10061$1_DATA[31:0]$2694 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] }
-        assign $0$memwr$\mem$ls180.v:10061$1_EN[31:0]$2695 255
+        assign $0$memwr$\mem$ls180.v:10049$1_ADDR[6:0]$2681 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10049$1_DATA[31:0]$2682 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] }
+        assign $0$memwr$\mem$ls180.v:10049$1_EN[31:0]$2683 255
       case 
     end
-    attribute \src "ls180.v:10062.2-10063.67"
+    attribute \src "ls180.v:10050.2-10051.67"
     switch \main_libresocsim_we [1]
-      attribute \src "ls180.v:10062.6-10062.28"
+      attribute \src "ls180.v:10050.6-10050.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10063$2_ADDR[6:0]$2696 \main_libresocsim_adr
-        assign $0$memwr$\mem$ls180.v:10063$2_DATA[31:0]$2697 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx }
-        assign $0$memwr$\mem$ls180.v:10063$2_EN[31:0]$2698 65280
+        assign $0$memwr$\mem$ls180.v:10051$2_ADDR[6:0]$2684 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10051$2_DATA[31:0]$2685 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx }
+        assign $0$memwr$\mem$ls180.v:10051$2_EN[31:0]$2686 65280
       case 
     end
-    attribute \src "ls180.v:10064.2-10065.69"
+    attribute \src "ls180.v:10052.2-10053.69"
     switch \main_libresocsim_we [2]
-      attribute \src "ls180.v:10064.6-10064.28"
+      attribute \src "ls180.v:10052.6-10052.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10065$3_ADDR[6:0]$2699 \main_libresocsim_adr
-        assign $0$memwr$\mem$ls180.v:10065$3_DATA[31:0]$2700 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
-        assign $0$memwr$\mem$ls180.v:10065$3_EN[31:0]$2701 16711680
+        assign $0$memwr$\mem$ls180.v:10053$3_ADDR[6:0]$2687 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10053$3_DATA[31:0]$2688 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
+        assign $0$memwr$\mem$ls180.v:10053$3_EN[31:0]$2689 16711680
       case 
     end
-    attribute \src "ls180.v:10066.2-10067.69"
+    attribute \src "ls180.v:10054.2-10055.69"
     switch \main_libresocsim_we [3]
-      attribute \src "ls180.v:10066.6-10066.28"
+      attribute \src "ls180.v:10054.6-10054.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10067$4_ADDR[6:0]$2702 \main_libresocsim_adr
-        assign $0$memwr$\mem$ls180.v:10067$4_DATA[31:0]$2703 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
-        assign $0$memwr$\mem$ls180.v:10067$4_EN[31:0]$2704 32'11111111000000000000000000000000
+        assign $0$memwr$\mem$ls180.v:10055$4_ADDR[6:0]$2690 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10055$4_DATA[31:0]$2691 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
+        assign $0$memwr$\mem$ls180.v:10055$4_EN[31:0]$2692 32'11111111000000000000000000000000
       case 
     end
     sync posedge \sys_clk_1
       update \memadr $0\memadr[6:0]
-      update $memwr$\mem$ls180.v:10061$1_ADDR $0$memwr$\mem$ls180.v:10061$1_ADDR[6:0]$2693
-      update $memwr$\mem$ls180.v:10061$1_DATA $0$memwr$\mem$ls180.v:10061$1_DATA[31:0]$2694
-      update $memwr$\mem$ls180.v:10061$1_EN $0$memwr$\mem$ls180.v:10061$1_EN[31:0]$2695
-      update $memwr$\mem$ls180.v:10063$2_ADDR $0$memwr$\mem$ls180.v:10063$2_ADDR[6:0]$2696
-      update $memwr$\mem$ls180.v:10063$2_DATA $0$memwr$\mem$ls180.v:10063$2_DATA[31:0]$2697
-      update $memwr$\mem$ls180.v:10063$2_EN $0$memwr$\mem$ls180.v:10063$2_EN[31:0]$2698
-      update $memwr$\mem$ls180.v:10065$3_ADDR $0$memwr$\mem$ls180.v:10065$3_ADDR[6:0]$2699
-      update $memwr$\mem$ls180.v:10065$3_DATA $0$memwr$\mem$ls180.v:10065$3_DATA[31:0]$2700
-      update $memwr$\mem$ls180.v:10065$3_EN $0$memwr$\mem$ls180.v:10065$3_EN[31:0]$2701
-      update $memwr$\mem$ls180.v:10067$4_ADDR $0$memwr$\mem$ls180.v:10067$4_ADDR[6:0]$2702
-      update $memwr$\mem$ls180.v:10067$4_DATA $0$memwr$\mem$ls180.v:10067$4_DATA[31:0]$2703
-      update $memwr$\mem$ls180.v:10067$4_EN $0$memwr$\mem$ls180.v:10067$4_EN[31:0]$2704
-  end
-  attribute \src "ls180.v:10079.1-10083.4"
-  process $proc$ls180.v:10079$2706
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign $0$memwr$\storage$ls180.v:10081$5_ADDR[2:0]$2707 3'xxx
-    assign $0$memwr$\storage$ls180.v:10081$5_DATA[24:0]$2708 25'xxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\storage$ls180.v:10081$5_EN[24:0]$2709 25'0000000000000000000000000
-    assign $0\memdat[24:0] $memrd$\storage$ls180.v:10082$2710_DATA
-    attribute \src "ls180.v:10080.2-10081.129"
+      update $memwr$\mem$ls180.v:10049$1_ADDR $0$memwr$\mem$ls180.v:10049$1_ADDR[6:0]$2681
+      update $memwr$\mem$ls180.v:10049$1_DATA $0$memwr$\mem$ls180.v:10049$1_DATA[31:0]$2682
+      update $memwr$\mem$ls180.v:10049$1_EN $0$memwr$\mem$ls180.v:10049$1_EN[31:0]$2683
+      update $memwr$\mem$ls180.v:10051$2_ADDR $0$memwr$\mem$ls180.v:10051$2_ADDR[6:0]$2684
+      update $memwr$\mem$ls180.v:10051$2_DATA $0$memwr$\mem$ls180.v:10051$2_DATA[31:0]$2685
+      update $memwr$\mem$ls180.v:10051$2_EN $0$memwr$\mem$ls180.v:10051$2_EN[31:0]$2686
+      update $memwr$\mem$ls180.v:10053$3_ADDR $0$memwr$\mem$ls180.v:10053$3_ADDR[6:0]$2687
+      update $memwr$\mem$ls180.v:10053$3_DATA $0$memwr$\mem$ls180.v:10053$3_DATA[31:0]$2688
+      update $memwr$\mem$ls180.v:10053$3_EN $0$memwr$\mem$ls180.v:10053$3_EN[31:0]$2689
+      update $memwr$\mem$ls180.v:10055$4_ADDR $0$memwr$\mem$ls180.v:10055$4_ADDR[6:0]$2690
+      update $memwr$\mem$ls180.v:10055$4_DATA $0$memwr$\mem$ls180.v:10055$4_DATA[31:0]$2691
+      update $memwr$\mem$ls180.v:10055$4_EN $0$memwr$\mem$ls180.v:10055$4_EN[31:0]$2692
+  end
+  attribute \src "ls180.v:10067.1-10071.4"
+  process $proc$ls180.v:10067$2694
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign { } { }
+    assign $0$memwr$\storage$ls180.v:10069$5_ADDR[2:0]$2695 3'xxx
+    assign $0$memwr$\storage$ls180.v:10069$5_DATA[24:0]$2696 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\storage$ls180.v:10069$5_EN[24:0]$2697 25'0000000000000000000000000
+    assign $0\memdat[24:0] $memrd$\storage$ls180.v:10070$2698_DATA
+    attribute \src "ls180.v:10068.2-10069.129"
     switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
-      attribute \src "ls180.v:10080.6-10080.60"
+      attribute \src "ls180.v:10068.6-10068.60"
       case 1'1
-        assign $0$memwr$\storage$ls180.v:10081$5_ADDR[2:0]$2707 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
-        assign $0$memwr$\storage$ls180.v:10081$5_DATA[24:0]$2708 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
-        assign $0$memwr$\storage$ls180.v:10081$5_EN[24:0]$2709 25'1111111111111111111111111
+        assign $0$memwr$\storage$ls180.v:10069$5_ADDR[2:0]$2695 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
+        assign $0$memwr$\storage$ls180.v:10069$5_DATA[24:0]$2696 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
+        assign $0$memwr$\storage$ls180.v:10069$5_EN[24:0]$2697 25'1111111111111111111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat $0\memdat[24:0]
-      update $memwr$\storage$ls180.v:10081$5_ADDR $0$memwr$\storage$ls180.v:10081$5_ADDR[2:0]$2707
-      update $memwr$\storage$ls180.v:10081$5_DATA $0$memwr$\storage$ls180.v:10081$5_DATA[24:0]$2708
-      update $memwr$\storage$ls180.v:10081$5_EN $0$memwr$\storage$ls180.v:10081$5_EN[24:0]$2709
+      update $memwr$\storage$ls180.v:10069$5_ADDR $0$memwr$\storage$ls180.v:10069$5_ADDR[2:0]$2695
+      update $memwr$\storage$ls180.v:10069$5_DATA $0$memwr$\storage$ls180.v:10069$5_DATA[24:0]$2696
+      update $memwr$\storage$ls180.v:10069$5_EN $0$memwr$\storage$ls180.v:10069$5_EN[24:0]$2697
+  end
+  attribute \src "ls180.v:10073.1-10074.4"
+  process $proc$ls180.v:10073$2699
+    sync posedge \sys_clk_1
   end
   attribute \src "ls180.v:1008.11-1008.42"
-  process $proc$ls180.v:1008$3150
+  process $proc$ls180.v:1008$3138
     assign { } { }
     assign $1\main_spimaster16_storage[7:0] 8'00000000
     sync always
     sync init
       update \main_spimaster16_storage $1\main_spimaster16_storage[7:0]
   end
-  attribute \src "ls180.v:10085.1-10086.4"
-  process $proc$ls180.v:10085$2711
-    sync posedge \sys_clk_1
-  end
-  attribute \src "ls180.v:1009.5-1009.31"
-  process $proc$ls180.v:1009$3151
-    assign { } { }
-    assign $1\main_spimaster17_re[0:0] 1'0
-    sync always
-    sync init
-      update \main_spimaster17_re $1\main_spimaster17_re[0:0]
-  end
-  attribute \src "ls180.v:10093.1-10097.4"
-  process $proc$ls180.v:10093$2713
+  attribute \src "ls180.v:10081.1-10085.4"
+  process $proc$ls180.v:10081$2701
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_1$ls180.v:10095$6_ADDR[2:0]$2714 3'xxx
-    assign $0$memwr$\storage_1$ls180.v:10095$6_DATA[24:0]$2715 25'xxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\storage_1$ls180.v:10095$6_EN[24:0]$2716 25'0000000000000000000000000
-    assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10096$2717_DATA
-    attribute \src "ls180.v:10094.2-10095.131"
+    assign $0$memwr$\storage_1$ls180.v:10083$6_ADDR[2:0]$2702 3'xxx
+    assign $0$memwr$\storage_1$ls180.v:10083$6_DATA[24:0]$2703 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\storage_1$ls180.v:10083$6_EN[24:0]$2704 25'0000000000000000000000000
+    assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10084$2705_DATA
+    attribute \src "ls180.v:10082.2-10083.131"
     switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
-      attribute \src "ls180.v:10094.6-10094.60"
+      attribute \src "ls180.v:10082.6-10082.60"
       case 1'1
-        assign $0$memwr$\storage_1$ls180.v:10095$6_ADDR[2:0]$2714 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
-        assign $0$memwr$\storage_1$ls180.v:10095$6_DATA[24:0]$2715 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
-        assign $0$memwr$\storage_1$ls180.v:10095$6_EN[24:0]$2716 25'1111111111111111111111111
+        assign $0$memwr$\storage_1$ls180.v:10083$6_ADDR[2:0]$2702 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
+        assign $0$memwr$\storage_1$ls180.v:10083$6_DATA[24:0]$2703 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
+        assign $0$memwr$\storage_1$ls180.v:10083$6_EN[24:0]$2704 25'1111111111111111111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_1 $0\memdat_1[24:0]
-      update $memwr$\storage_1$ls180.v:10095$6_ADDR $0$memwr$\storage_1$ls180.v:10095$6_ADDR[2:0]$2714
-      update $memwr$\storage_1$ls180.v:10095$6_DATA $0$memwr$\storage_1$ls180.v:10095$6_DATA[24:0]$2715
-      update $memwr$\storage_1$ls180.v:10095$6_EN $0$memwr$\storage_1$ls180.v:10095$6_EN[24:0]$2716
+      update $memwr$\storage_1$ls180.v:10083$6_ADDR $0$memwr$\storage_1$ls180.v:10083$6_ADDR[2:0]$2702
+      update $memwr$\storage_1$ls180.v:10083$6_DATA $0$memwr$\storage_1$ls180.v:10083$6_DATA[24:0]$2703
+      update $memwr$\storage_1$ls180.v:10083$6_EN $0$memwr$\storage_1$ls180.v:10083$6_EN[24:0]$2704
   end
-  attribute \src "ls180.v:10099.1-10100.4"
-  process $proc$ls180.v:10099$2718
+  attribute \src "ls180.v:10087.1-10088.4"
+  process $proc$ls180.v:10087$2706
     sync posedge \sys_clk_1
   end
-  attribute \src "ls180.v:10107.1-10111.4"
-  process $proc$ls180.v:10107$2720
+  attribute \src "ls180.v:1009.5-1009.31"
+  process $proc$ls180.v:1009$3139
+    assign { } { }
+    assign $1\main_spimaster17_re[0:0] 1'0
+    sync always
+    sync init
+      update \main_spimaster17_re $1\main_spimaster17_re[0:0]
+  end
+  attribute \src "ls180.v:10095.1-10099.4"
+  process $proc$ls180.v:10095$2708
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_2$ls180.v:10109$7_ADDR[2:0]$2721 3'xxx
-    assign $0$memwr$\storage_2$ls180.v:10109$7_DATA[24:0]$2722 25'xxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\storage_2$ls180.v:10109$7_EN[24:0]$2723 25'0000000000000000000000000
-    assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10110$2724_DATA
-    attribute \src "ls180.v:10108.2-10109.131"
+    assign $0$memwr$\storage_2$ls180.v:10097$7_ADDR[2:0]$2709 3'xxx
+    assign $0$memwr$\storage_2$ls180.v:10097$7_DATA[24:0]$2710 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\storage_2$ls180.v:10097$7_EN[24:0]$2711 25'0000000000000000000000000
+    assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10098$2712_DATA
+    attribute \src "ls180.v:10096.2-10097.131"
     switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we
-      attribute \src "ls180.v:10108.6-10108.60"
+      attribute \src "ls180.v:10096.6-10096.60"
       case 1'1
-        assign $0$memwr$\storage_2$ls180.v:10109$7_ADDR[2:0]$2721 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
-        assign $0$memwr$\storage_2$ls180.v:10109$7_DATA[24:0]$2722 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
-        assign $0$memwr$\storage_2$ls180.v:10109$7_EN[24:0]$2723 25'1111111111111111111111111
+        assign $0$memwr$\storage_2$ls180.v:10097$7_ADDR[2:0]$2709 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
+        assign $0$memwr$\storage_2$ls180.v:10097$7_DATA[24:0]$2710 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
+        assign $0$memwr$\storage_2$ls180.v:10097$7_EN[24:0]$2711 25'1111111111111111111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_2 $0\memdat_2[24:0]
-      update $memwr$\storage_2$ls180.v:10109$7_ADDR $0$memwr$\storage_2$ls180.v:10109$7_ADDR[2:0]$2721
-      update $memwr$\storage_2$ls180.v:10109$7_DATA $0$memwr$\storage_2$ls180.v:10109$7_DATA[24:0]$2722
-      update $memwr$\storage_2$ls180.v:10109$7_EN $0$memwr$\storage_2$ls180.v:10109$7_EN[24:0]$2723
+      update $memwr$\storage_2$ls180.v:10097$7_ADDR $0$memwr$\storage_2$ls180.v:10097$7_ADDR[2:0]$2709
+      update $memwr$\storage_2$ls180.v:10097$7_DATA $0$memwr$\storage_2$ls180.v:10097$7_DATA[24:0]$2710
+      update $memwr$\storage_2$ls180.v:10097$7_EN $0$memwr$\storage_2$ls180.v:10097$7_EN[24:0]$2711
   end
-  attribute \src "ls180.v:10113.1-10114.4"
-  process $proc$ls180.v:10113$2725
+  attribute \src "ls180.v:10101.1-10102.4"
+  process $proc$ls180.v:10101$2713
     sync posedge \sys_clk_1
   end
-  attribute \src "ls180.v:10121.1-10125.4"
-  process $proc$ls180.v:10121$2727
+  attribute \src "ls180.v:10109.1-10113.4"
+  process $proc$ls180.v:10109$2715
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_3$ls180.v:10123$8_ADDR[2:0]$2728 3'xxx
-    assign $0$memwr$\storage_3$ls180.v:10123$8_DATA[24:0]$2729 25'xxxxxxxxxxxxxxxxxxxxxxxxx
-    assign $0$memwr$\storage_3$ls180.v:10123$8_EN[24:0]$2730 25'0000000000000000000000000
-    assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10124$2731_DATA
-    attribute \src "ls180.v:10122.2-10123.131"
+    assign $0$memwr$\storage_3$ls180.v:10111$8_ADDR[2:0]$2716 3'xxx
+    assign $0$memwr$\storage_3$ls180.v:10111$8_DATA[24:0]$2717 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+    assign $0$memwr$\storage_3$ls180.v:10111$8_EN[24:0]$2718 25'0000000000000000000000000
+    assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10112$2719_DATA
+    attribute \src "ls180.v:10110.2-10111.131"
     switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we
-      attribute \src "ls180.v:10122.6-10122.60"
+      attribute \src "ls180.v:10110.6-10110.60"
       case 1'1
-        assign $0$memwr$\storage_3$ls180.v:10123$8_ADDR[2:0]$2728 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
-        assign $0$memwr$\storage_3$ls180.v:10123$8_DATA[24:0]$2729 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
-        assign $0$memwr$\storage_3$ls180.v:10123$8_EN[24:0]$2730 25'1111111111111111111111111
+        assign $0$memwr$\storage_3$ls180.v:10111$8_ADDR[2:0]$2716 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
+        assign $0$memwr$\storage_3$ls180.v:10111$8_DATA[24:0]$2717 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
+        assign $0$memwr$\storage_3$ls180.v:10111$8_EN[24:0]$2718 25'1111111111111111111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_3 $0\memdat_3[24:0]
-      update $memwr$\storage_3$ls180.v:10123$8_ADDR $0$memwr$\storage_3$ls180.v:10123$8_ADDR[2:0]$2728
-      update $memwr$\storage_3$ls180.v:10123$8_DATA $0$memwr$\storage_3$ls180.v:10123$8_DATA[24:0]$2729
-      update $memwr$\storage_3$ls180.v:10123$8_EN $0$memwr$\storage_3$ls180.v:10123$8_EN[24:0]$2730
+      update $memwr$\storage_3$ls180.v:10111$8_ADDR $0$memwr$\storage_3$ls180.v:10111$8_ADDR[2:0]$2716
+      update $memwr$\storage_3$ls180.v:10111$8_DATA $0$memwr$\storage_3$ls180.v:10111$8_DATA[24:0]$2717
+      update $memwr$\storage_3$ls180.v:10111$8_EN $0$memwr$\storage_3$ls180.v:10111$8_EN[24:0]$2718
   end
-  attribute \src "ls180.v:10127.1-10128.4"
-  process $proc$ls180.v:10127$2732
+  attribute \src "ls180.v:10115.1-10116.4"
+  process $proc$ls180.v:10115$2720
     sync posedge \sys_clk_1
   end
-  attribute \src "ls180.v:1013.5-1013.36"
-  process $proc$ls180.v:1013$3152
-    assign { } { }
-    assign $1\main_spimaster21_storage[0:0] 1'1
-    sync always
-    sync init
-      update \main_spimaster21_storage $1\main_spimaster21_storage[0:0]
-  end
-  attribute \src "ls180.v:10136.1-10140.4"
-  process $proc$ls180.v:10136$2734
+  attribute \src "ls180.v:10124.1-10128.4"
+  process $proc$ls180.v:10124$2722
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_4$ls180.v:10138$9_ADDR[3:0]$2735 4'xxxx
-    assign $0$memwr$\storage_4$ls180.v:10138$9_DATA[9:0]$2736 10'xxxxxxxxxx
-    assign $0$memwr$\storage_4$ls180.v:10138$9_EN[9:0]$2737 10'0000000000
-    assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10139$2738_DATA
-    attribute \src "ls180.v:10137.2-10138.77"
+    assign $0$memwr$\storage_4$ls180.v:10126$9_ADDR[3:0]$2723 4'xxxx
+    assign $0$memwr$\storage_4$ls180.v:10126$9_DATA[9:0]$2724 10'xxxxxxxxxx
+    assign $0$memwr$\storage_4$ls180.v:10126$9_EN[9:0]$2725 10'0000000000
+    assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10127$2726_DATA
+    attribute \src "ls180.v:10125.2-10126.77"
     switch \main_uart_tx_fifo_wrport_we
-      attribute \src "ls180.v:10137.6-10137.33"
+      attribute \src "ls180.v:10125.6-10125.33"
       case 1'1
-        assign $0$memwr$\storage_4$ls180.v:10138$9_ADDR[3:0]$2735 \main_uart_tx_fifo_wrport_adr
-        assign $0$memwr$\storage_4$ls180.v:10138$9_DATA[9:0]$2736 \main_uart_tx_fifo_wrport_dat_w
-        assign $0$memwr$\storage_4$ls180.v:10138$9_EN[9:0]$2737 10'1111111111
+        assign $0$memwr$\storage_4$ls180.v:10126$9_ADDR[3:0]$2723 \main_uart_tx_fifo_wrport_adr
+        assign $0$memwr$\storage_4$ls180.v:10126$9_DATA[9:0]$2724 \main_uart_tx_fifo_wrport_dat_w
+        assign $0$memwr$\storage_4$ls180.v:10126$9_EN[9:0]$2725 10'1111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_4 $0\memdat_4[9:0]
-      update $memwr$\storage_4$ls180.v:10138$9_ADDR $0$memwr$\storage_4$ls180.v:10138$9_ADDR[3:0]$2735
-      update $memwr$\storage_4$ls180.v:10138$9_DATA $0$memwr$\storage_4$ls180.v:10138$9_DATA[9:0]$2736
-      update $memwr$\storage_4$ls180.v:10138$9_EN $0$memwr$\storage_4$ls180.v:10138$9_EN[9:0]$2737
+      update $memwr$\storage_4$ls180.v:10126$9_ADDR $0$memwr$\storage_4$ls180.v:10126$9_ADDR[3:0]$2723
+      update $memwr$\storage_4$ls180.v:10126$9_DATA $0$memwr$\storage_4$ls180.v:10126$9_DATA[9:0]$2724
+      update $memwr$\storage_4$ls180.v:10126$9_EN $0$memwr$\storage_4$ls180.v:10126$9_EN[9:0]$2725
   end
-  attribute \src "ls180.v:1014.5-1014.31"
-  process $proc$ls180.v:1014$3153
+  attribute \src "ls180.v:1013.5-1013.36"
+  process $proc$ls180.v:1013$3140
     assign { } { }
-    assign $1\main_spimaster22_re[0:0] 1'0
+    assign $1\main_spimaster21_storage[0:0] 1'1
     sync always
     sync init
-      update \main_spimaster22_re $1\main_spimaster22_re[0:0]
+      update \main_spimaster21_storage $1\main_spimaster21_storage[0:0]
   end
-  attribute \src "ls180.v:10142.1-10145.4"
-  process $proc$ls180.v:10142$2739
+  attribute \src "ls180.v:10130.1-10133.4"
+  process $proc$ls180.v:10130$2727
     assign $0\memdat_5[9:0] \memdat_5
-    attribute \src "ls180.v:10143.2-10144.55"
+    attribute \src "ls180.v:10131.2-10132.55"
     switch \main_uart_tx_fifo_rdport_re
-      attribute \src "ls180.v:10143.6-10143.33"
+      attribute \src "ls180.v:10131.6-10131.33"
       case 1'1
-        assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10144$2740_DATA
+        assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10132$2728_DATA
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_5 $0\memdat_5[9:0]
   end
-  attribute \src "ls180.v:1015.5-1015.36"
-  process $proc$ls180.v:1015$3154
+  attribute \src "ls180.v:1014.5-1014.31"
+  process $proc$ls180.v:1014$3141
     assign { } { }
-    assign $1\main_spimaster23_storage[0:0] 1'0
+    assign $1\main_spimaster22_re[0:0] 1'0
     sync always
     sync init
-      update \main_spimaster23_storage $1\main_spimaster23_storage[0:0]
+      update \main_spimaster22_re $1\main_spimaster22_re[0:0]
   end
-  attribute \src "ls180.v:10153.1-10157.4"
-  process $proc$ls180.v:10153$2741
+  attribute \src "ls180.v:10141.1-10145.4"
+  process $proc$ls180.v:10141$2729
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_5$ls180.v:10155$10_ADDR[3:0]$2742 4'xxxx
-    assign $0$memwr$\storage_5$ls180.v:10155$10_DATA[9:0]$2743 10'xxxxxxxxxx
-    assign $0$memwr$\storage_5$ls180.v:10155$10_EN[9:0]$2744 10'0000000000
-    assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10156$2745_DATA
-    attribute \src "ls180.v:10154.2-10155.77"
+    assign $0$memwr$\storage_5$ls180.v:10143$10_ADDR[3:0]$2730 4'xxxx
+    assign $0$memwr$\storage_5$ls180.v:10143$10_DATA[9:0]$2731 10'xxxxxxxxxx
+    assign $0$memwr$\storage_5$ls180.v:10143$10_EN[9:0]$2732 10'0000000000
+    assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10144$2733_DATA
+    attribute \src "ls180.v:10142.2-10143.77"
     switch \main_uart_rx_fifo_wrport_we
-      attribute \src "ls180.v:10154.6-10154.33"
+      attribute \src "ls180.v:10142.6-10142.33"
       case 1'1
-        assign $0$memwr$\storage_5$ls180.v:10155$10_ADDR[3:0]$2742 \main_uart_rx_fifo_wrport_adr
-        assign $0$memwr$\storage_5$ls180.v:10155$10_DATA[9:0]$2743 \main_uart_rx_fifo_wrport_dat_w
-        assign $0$memwr$\storage_5$ls180.v:10155$10_EN[9:0]$2744 10'1111111111
+        assign $0$memwr$\storage_5$ls180.v:10143$10_ADDR[3:0]$2730 \main_uart_rx_fifo_wrport_adr
+        assign $0$memwr$\storage_5$ls180.v:10143$10_DATA[9:0]$2731 \main_uart_rx_fifo_wrport_dat_w
+        assign $0$memwr$\storage_5$ls180.v:10143$10_EN[9:0]$2732 10'1111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_6 $0\memdat_6[9:0]
-      update $memwr$\storage_5$ls180.v:10155$10_ADDR $0$memwr$\storage_5$ls180.v:10155$10_ADDR[3:0]$2742
-      update $memwr$\storage_5$ls180.v:10155$10_DATA $0$memwr$\storage_5$ls180.v:10155$10_DATA[9:0]$2743
-      update $memwr$\storage_5$ls180.v:10155$10_EN $0$memwr$\storage_5$ls180.v:10155$10_EN[9:0]$2744
+      update $memwr$\storage_5$ls180.v:10143$10_ADDR $0$memwr$\storage_5$ls180.v:10143$10_ADDR[3:0]$2730
+      update $memwr$\storage_5$ls180.v:10143$10_DATA $0$memwr$\storage_5$ls180.v:10143$10_DATA[9:0]$2731
+      update $memwr$\storage_5$ls180.v:10143$10_EN $0$memwr$\storage_5$ls180.v:10143$10_EN[9:0]$2732
   end
-  attribute \src "ls180.v:10159.1-10162.4"
-  process $proc$ls180.v:10159$2746
+  attribute \src "ls180.v:10147.1-10150.4"
+  process $proc$ls180.v:10147$2734
     assign $0\memdat_7[9:0] \memdat_7
-    attribute \src "ls180.v:10160.2-10161.55"
+    attribute \src "ls180.v:10148.2-10149.55"
     switch \main_uart_rx_fifo_rdport_re
-      attribute \src "ls180.v:10160.6-10160.33"
+      attribute \src "ls180.v:10148.6-10148.33"
       case 1'1
-        assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10161$2747_DATA
+        assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10149$2735_DATA
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_7 $0\memdat_7[9:0]
   end
-  attribute \src "ls180.v:1016.5-1016.31"
-  process $proc$ls180.v:1016$3155
+  attribute \src "ls180.v:1015.5-1015.36"
+  process $proc$ls180.v:1015$3142
     assign { } { }
-    assign $1\main_spimaster24_re[0:0] 1'0
+    assign $1\main_spimaster23_storage[0:0] 1'0
     sync always
     sync init
-      update \main_spimaster24_re $1\main_spimaster24_re[0:0]
+      update \main_spimaster23_storage $1\main_spimaster23_storage[0:0]
   end
-  attribute \src "ls180.v:10169.1-10173.4"
-  process $proc$ls180.v:10169$2748
+  attribute \src "ls180.v:10157.1-10161.4"
+  process $proc$ls180.v:10157$2736
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_6$ls180.v:10171$11_ADDR[4:0]$2749 5'xxxxx
-    assign $0$memwr$\storage_6$ls180.v:10171$11_DATA[9:0]$2750 10'xxxxxxxxxx
-    assign $0$memwr$\storage_6$ls180.v:10171$11_EN[9:0]$2751 10'0000000000
-    assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10172$2752_DATA
-    attribute \src "ls180.v:10170.2-10171.85"
+    assign $0$memwr$\storage_6$ls180.v:10159$11_ADDR[4:0]$2737 5'xxxxx
+    assign $0$memwr$\storage_6$ls180.v:10159$11_DATA[9:0]$2738 10'xxxxxxxxxx
+    assign $0$memwr$\storage_6$ls180.v:10159$11_EN[9:0]$2739 10'0000000000
+    assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10160$2740_DATA
+    attribute \src "ls180.v:10158.2-10159.85"
     switch \main_sdblock2mem_fifo_wrport_we
-      attribute \src "ls180.v:10170.6-10170.37"
+      attribute \src "ls180.v:10158.6-10158.37"
       case 1'1
-        assign $0$memwr$\storage_6$ls180.v:10171$11_ADDR[4:0]$2749 \main_sdblock2mem_fifo_wrport_adr
-        assign $0$memwr$\storage_6$ls180.v:10171$11_DATA[9:0]$2750 \main_sdblock2mem_fifo_wrport_dat_w
-        assign $0$memwr$\storage_6$ls180.v:10171$11_EN[9:0]$2751 10'1111111111
+        assign $0$memwr$\storage_6$ls180.v:10159$11_ADDR[4:0]$2737 \main_sdblock2mem_fifo_wrport_adr
+        assign $0$memwr$\storage_6$ls180.v:10159$11_DATA[9:0]$2738 \main_sdblock2mem_fifo_wrport_dat_w
+        assign $0$memwr$\storage_6$ls180.v:10159$11_EN[9:0]$2739 10'1111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_8 $0\memdat_8[9:0]
-      update $memwr$\storage_6$ls180.v:10171$11_ADDR $0$memwr$\storage_6$ls180.v:10171$11_ADDR[4:0]$2749
-      update $memwr$\storage_6$ls180.v:10171$11_DATA $0$memwr$\storage_6$ls180.v:10171$11_DATA[9:0]$2750
-      update $memwr$\storage_6$ls180.v:10171$11_EN $0$memwr$\storage_6$ls180.v:10171$11_EN[9:0]$2751
+      update $memwr$\storage_6$ls180.v:10159$11_ADDR $0$memwr$\storage_6$ls180.v:10159$11_ADDR[4:0]$2737
+      update $memwr$\storage_6$ls180.v:10159$11_DATA $0$memwr$\storage_6$ls180.v:10159$11_DATA[9:0]$2738
+      update $memwr$\storage_6$ls180.v:10159$11_EN $0$memwr$\storage_6$ls180.v:10159$11_EN[9:0]$2739
   end
-  attribute \src "ls180.v:1017.5-1017.39"
-  process $proc$ls180.v:1017$3156
+  attribute \src "ls180.v:1016.5-1016.31"
+  process $proc$ls180.v:1016$3143
     assign { } { }
-    assign $1\main_spimaster25_clk_enable[0:0] 1'0
+    assign $1\main_spimaster24_re[0:0] 1'0
     sync always
     sync init
-      update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0]
+      update \main_spimaster24_re $1\main_spimaster24_re[0:0]
   end
-  attribute \src "ls180.v:10175.1-10176.4"
-  process $proc$ls180.v:10175$2753
+  attribute \src "ls180.v:10163.1-10164.4"
+  process $proc$ls180.v:10163$2741
     sync posedge \sys_clk_1
   end
-  attribute \src "ls180.v:1018.5-1018.38"
-  process $proc$ls180.v:1018$3157
+  attribute \src "ls180.v:1017.5-1017.39"
+  process $proc$ls180.v:1017$3144
     assign { } { }
-    assign $1\main_spimaster26_cs_enable[0:0] 1'0
+    assign $1\main_spimaster25_clk_enable[0:0] 1'0
     sync always
     sync init
-      update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0]
+      update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0]
   end
-  attribute \src "ls180.v:10183.1-10187.4"
-  process $proc$ls180.v:10183$2755
+  attribute \src "ls180.v:10171.1-10175.4"
+  process $proc$ls180.v:10171$2743
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_7$ls180.v:10185$12_ADDR[4:0]$2756 5'xxxxx
-    assign $0$memwr$\storage_7$ls180.v:10185$12_DATA[9:0]$2757 10'xxxxxxxxxx
-    assign $0$memwr$\storage_7$ls180.v:10185$12_EN[9:0]$2758 10'0000000000
-    assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10186$2759_DATA
-    attribute \src "ls180.v:10184.2-10185.85"
+    assign $0$memwr$\storage_7$ls180.v:10173$12_ADDR[4:0]$2744 5'xxxxx
+    assign $0$memwr$\storage_7$ls180.v:10173$12_DATA[9:0]$2745 10'xxxxxxxxxx
+    assign $0$memwr$\storage_7$ls180.v:10173$12_EN[9:0]$2746 10'0000000000
+    assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10174$2747_DATA
+    attribute \src "ls180.v:10172.2-10173.85"
     switch \main_sdmem2block_fifo_wrport_we
-      attribute \src "ls180.v:10184.6-10184.37"
+      attribute \src "ls180.v:10172.6-10172.37"
       case 1'1
-        assign $0$memwr$\storage_7$ls180.v:10185$12_ADDR[4:0]$2756 \main_sdmem2block_fifo_wrport_adr
-        assign $0$memwr$\storage_7$ls180.v:10185$12_DATA[9:0]$2757 \main_sdmem2block_fifo_wrport_dat_w
-        assign $0$memwr$\storage_7$ls180.v:10185$12_EN[9:0]$2758 10'1111111111
+        assign $0$memwr$\storage_7$ls180.v:10173$12_ADDR[4:0]$2744 \main_sdmem2block_fifo_wrport_adr
+        assign $0$memwr$\storage_7$ls180.v:10173$12_DATA[9:0]$2745 \main_sdmem2block_fifo_wrport_dat_w
+        assign $0$memwr$\storage_7$ls180.v:10173$12_EN[9:0]$2746 10'1111111111
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_9 $0\memdat_9[9:0]
-      update $memwr$\storage_7$ls180.v:10185$12_ADDR $0$memwr$\storage_7$ls180.v:10185$12_ADDR[4:0]$2756
-      update $memwr$\storage_7$ls180.v:10185$12_DATA $0$memwr$\storage_7$ls180.v:10185$12_DATA[9:0]$2757
-      update $memwr$\storage_7$ls180.v:10185$12_EN $0$memwr$\storage_7$ls180.v:10185$12_EN[9:0]$2758
+      update $memwr$\storage_7$ls180.v:10173$12_ADDR $0$memwr$\storage_7$ls180.v:10173$12_ADDR[4:0]$2744
+      update $memwr$\storage_7$ls180.v:10173$12_DATA $0$memwr$\storage_7$ls180.v:10173$12_DATA[9:0]$2745
+      update $memwr$\storage_7$ls180.v:10173$12_EN $0$memwr$\storage_7$ls180.v:10173$12_EN[9:0]$2746
   end
-  attribute \src "ls180.v:10189.1-10190.4"
-  process $proc$ls180.v:10189$2760
+  attribute \src "ls180.v:10177.1-10178.4"
+  process $proc$ls180.v:10177$2748
     sync posedge \sys_clk_1
   end
+  attribute \src "ls180.v:1018.5-1018.38"
+  process $proc$ls180.v:1018$3145
+    assign { } { }
+    assign $1\main_spimaster26_cs_enable[0:0] 1'0
+    sync always
+    sync init
+      update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0]
+  end
   attribute \src "ls180.v:1019.11-1019.40"
-  process $proc$ls180.v:1019$3158
+  process $proc$ls180.v:1019$3146
     assign { } { }
     assign $1\main_spimaster27_count[2:0] 3'000
     sync always
@@ -114644,7 +114488,7 @@ module \ls180
       update \main_spimaster27_count $1\main_spimaster27_count[2:0]
   end
   attribute \src "ls180.v:1020.5-1020.39"
-  process $proc$ls180.v:1020$3159
+  process $proc$ls180.v:1020$3147
     assign { } { }
     assign $1\main_spimaster28_mosi_latch[0:0] 1'0
     sync always
@@ -114652,7 +114496,7 @@ module \ls180
       update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0]
   end
   attribute \src "ls180.v:1021.5-1021.39"
-  process $proc$ls180.v:1021$3160
+  process $proc$ls180.v:1021$3148
     assign { } { }
     assign $1\main_spimaster29_miso_latch[0:0] 1'0
     sync always
@@ -114660,7 +114504,7 @@ module \ls180
       update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0]
   end
   attribute \src "ls180.v:1022.12-1022.48"
-  process $proc$ls180.v:1022$3161
+  process $proc$ls180.v:1022$3149
     assign { } { }
     assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000
     sync always
@@ -114668,7 +114512,7 @@ module \ls180
       update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0]
   end
   attribute \src "ls180.v:1025.11-1025.44"
-  process $proc$ls180.v:1025$3162
+  process $proc$ls180.v:1025$3150
     assign { } { }
     assign $1\main_spimaster33_mosi_data[7:0] 8'00000000
     sync always
@@ -114676,7 +114520,7 @@ module \ls180
       update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0]
   end
   attribute \src "ls180.v:1026.11-1026.43"
-  process $proc$ls180.v:1026$3163
+  process $proc$ls180.v:1026$3151
     assign { } { }
     assign $1\main_spimaster34_mosi_sel[2:0] 3'000
     sync always
@@ -114684,7 +114528,7 @@ module \ls180
       update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0]
   end
   attribute \src "ls180.v:1027.11-1027.44"
-  process $proc$ls180.v:1027$3164
+  process $proc$ls180.v:1027$3152
     assign { } { }
     assign $1\main_spimaster35_miso_data[7:0] 8'00000000
     sync always
@@ -114692,7 +114536,7 @@ module \ls180
       update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0]
   end
   attribute \src "ls180.v:1030.5-1030.32"
-  process $proc$ls180.v:1030$3165
+  process $proc$ls180.v:1030$3153
     assign { } { }
     assign $1\main_spisdcard_done0[0:0] 1'0
     sync always
@@ -114700,7 +114544,7 @@ module \ls180
       update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0]
   end
   attribute \src "ls180.v:1031.5-1031.30"
-  process $proc$ls180.v:1031$3166
+  process $proc$ls180.v:1031$3154
     assign { } { }
     assign $1\main_spisdcard_irq[0:0] 1'0
     sync always
@@ -114708,7 +114552,7 @@ module \ls180
       update \main_spisdcard_irq $1\main_spisdcard_irq[0:0]
   end
   attribute \src "ls180.v:1033.11-1033.37"
-  process $proc$ls180.v:1033$3167
+  process $proc$ls180.v:1033$3155
     assign { } { }
     assign $1\main_spisdcard_miso[7:0] 8'00000000
     sync always
@@ -114716,7 +114560,7 @@ module \ls180
       update \main_spisdcard_miso $1\main_spisdcard_miso[7:0]
   end
   attribute \src "ls180.v:1037.5-1037.33"
-  process $proc$ls180.v:1037$3168
+  process $proc$ls180.v:1037$3156
     assign { } { }
     assign $1\main_spisdcard_start1[0:0] 1'0
     sync always
@@ -114724,7 +114568,7 @@ module \ls180
       update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0]
   end
   attribute \src "ls180.v:1039.12-1039.50"
-  process $proc$ls180.v:1039$3169
+  process $proc$ls180.v:1039$3157
     assign { } { }
     assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000
     sync always
@@ -114732,7 +114576,7 @@ module \ls180
       update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0]
   end
   attribute \src "ls180.v:1040.5-1040.37"
-  process $proc$ls180.v:1040$3170
+  process $proc$ls180.v:1040$3158
     assign { } { }
     assign $1\main_spisdcard_control_re[0:0] 1'0
     sync always
@@ -114740,7 +114584,7 @@ module \ls180
       update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0]
   end
   attribute \src "ls180.v:1044.11-1044.45"
-  process $proc$ls180.v:1044$3171
+  process $proc$ls180.v:1044$3159
     assign { } { }
     assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000
     sync always
@@ -114748,7 +114592,7 @@ module \ls180
       update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0]
   end
   attribute \src "ls180.v:1045.5-1045.34"
-  process $proc$ls180.v:1045$3172
+  process $proc$ls180.v:1045$3160
     assign { } { }
     assign $1\main_spisdcard_mosi_re[0:0] 1'0
     sync always
@@ -114756,7 +114600,7 @@ module \ls180
       update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0]
   end
   attribute \src "ls180.v:1049.5-1049.37"
-  process $proc$ls180.v:1049$3173
+  process $proc$ls180.v:1049$3161
     assign { } { }
     assign $1\main_spisdcard_cs_storage[0:0] 1'1
     sync always
@@ -114764,7 +114608,7 @@ module \ls180
       update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0]
   end
   attribute \src "ls180.v:1050.5-1050.32"
-  process $proc$ls180.v:1050$3174
+  process $proc$ls180.v:1050$3162
     assign { } { }
     assign $1\main_spisdcard_cs_re[0:0] 1'0
     sync always
@@ -114772,7 +114616,7 @@ module \ls180
       update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0]
   end
   attribute \src "ls180.v:1051.5-1051.43"
-  process $proc$ls180.v:1051$3175
+  process $proc$ls180.v:1051$3163
     assign { } { }
     assign $1\main_spisdcard_loopback_storage[0:0] 1'0
     sync always
@@ -114780,7 +114624,7 @@ module \ls180
       update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0]
   end
   attribute \src "ls180.v:1052.5-1052.38"
-  process $proc$ls180.v:1052$3176
+  process $proc$ls180.v:1052$3164
     assign { } { }
     assign $1\main_spisdcard_loopback_re[0:0] 1'0
     sync always
@@ -114788,7 +114632,7 @@ module \ls180
       update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0]
   end
   attribute \src "ls180.v:1053.5-1053.37"
-  process $proc$ls180.v:1053$3177
+  process $proc$ls180.v:1053$3165
     assign { } { }
     assign $1\main_spisdcard_clk_enable[0:0] 1'0
     sync always
@@ -114796,7 +114640,7 @@ module \ls180
       update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0]
   end
   attribute \src "ls180.v:1054.5-1054.36"
-  process $proc$ls180.v:1054$3178
+  process $proc$ls180.v:1054$3166
     assign { } { }
     assign $1\main_spisdcard_cs_enable[0:0] 1'0
     sync always
@@ -114804,7 +114648,7 @@ module \ls180
       update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0]
   end
   attribute \src "ls180.v:1055.11-1055.38"
-  process $proc$ls180.v:1055$3179
+  process $proc$ls180.v:1055$3167
     assign { } { }
     assign $1\main_spisdcard_count[2:0] 3'000
     sync always
@@ -114812,7 +114656,7 @@ module \ls180
       update \main_spisdcard_count $1\main_spisdcard_count[2:0]
   end
   attribute \src "ls180.v:1056.5-1056.37"
-  process $proc$ls180.v:1056$3180
+  process $proc$ls180.v:1056$3168
     assign { } { }
     assign $1\main_spisdcard_mosi_latch[0:0] 1'0
     sync always
@@ -114820,7 +114664,7 @@ module \ls180
       update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0]
   end
   attribute \src "ls180.v:1057.5-1057.37"
-  process $proc$ls180.v:1057$3181
+  process $proc$ls180.v:1057$3169
     assign { } { }
     assign $1\main_spisdcard_miso_latch[0:0] 1'0
     sync always
@@ -114828,7 +114672,7 @@ module \ls180
       update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0]
   end
   attribute \src "ls180.v:1058.12-1058.47"
-  process $proc$ls180.v:1058$3182
+  process $proc$ls180.v:1058$3170
     assign { } { }
     assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000
     sync always
@@ -114836,7 +114680,7 @@ module \ls180
       update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0]
   end
   attribute \src "ls180.v:1061.11-1061.42"
-  process $proc$ls180.v:1061$3183
+  process $proc$ls180.v:1061$3171
     assign { } { }
     assign $1\main_spisdcard_mosi_data[7:0] 8'00000000
     sync always
@@ -114844,7 +114688,7 @@ module \ls180
       update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0]
   end
   attribute \src "ls180.v:1062.11-1062.41"
-  process $proc$ls180.v:1062$3184
+  process $proc$ls180.v:1062$3172
     assign { } { }
     assign $1\main_spisdcard_mosi_sel[2:0] 3'000
     sync always
@@ -114852,7 +114696,7 @@ module \ls180
       update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0]
   end
   attribute \src "ls180.v:1063.11-1063.42"
-  process $proc$ls180.v:1063$3185
+  process $proc$ls180.v:1063$3173
     assign { } { }
     assign $1\main_spisdcard_miso_data[7:0] 8'00000000
     sync always
@@ -114860,7 +114704,7 @@ module \ls180
       update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0]
   end
   attribute \src "ls180.v:1064.12-1064.45"
-  process $proc$ls180.v:1064$3186
+  process $proc$ls180.v:1064$3174
     assign { } { }
     assign $1\main_spimaster1_storage[15:0] 16'0000000001111101
     sync always
@@ -114868,7 +114712,7 @@ module \ls180
       update \main_spimaster1_storage $1\main_spimaster1_storage[15:0]
   end
   attribute \src "ls180.v:1065.5-1065.30"
-  process $proc$ls180.v:1065$3187
+  process $proc$ls180.v:1065$3175
     assign { } { }
     assign $1\main_spimaster1_re[0:0] 1'0
     sync always
@@ -114876,15 +114720,15 @@ module \ls180
       update \main_spimaster1_re $1\main_spimaster1_re[0:0]
   end
   attribute \src "ls180.v:1067.12-1067.30"
-  process $proc$ls180.v:1067$3188
+  process $proc$ls180.v:1067$3176
     assign { } { }
-    assign $1\main_dummy[35:0] 36'000000000000000000000000000000000000
+    assign $1\main_dummy[23:0] 24'000000000000000000000000
     sync always
     sync init
-      update \main_dummy $1\main_dummy[35:0]
+      update \main_dummy $1\main_dummy[23:0]
   end
   attribute \src "ls180.v:1071.12-1071.37"
-  process $proc$ls180.v:1071$3189
+  process $proc$ls180.v:1071$3177
     assign { } { }
     assign $1\main_pwm0_counter[31:0] 0
     sync always
@@ -114892,7 +114736,7 @@ module \ls180
       update \main_pwm0_counter $1\main_pwm0_counter[31:0]
   end
   attribute \src "ls180.v:1072.5-1072.36"
-  process $proc$ls180.v:1072$3190
+  process $proc$ls180.v:1072$3178
     assign { } { }
     assign $1\main_pwm0_enable_storage[0:0] 1'0
     sync always
@@ -114900,7 +114744,7 @@ module \ls180
       update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0]
   end
   attribute \src "ls180.v:1073.5-1073.31"
-  process $proc$ls180.v:1073$3191
+  process $proc$ls180.v:1073$3179
     assign { } { }
     assign $1\main_pwm0_enable_re[0:0] 1'0
     sync always
@@ -114908,7 +114752,7 @@ module \ls180
       update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0]
   end
   attribute \src "ls180.v:1074.12-1074.43"
-  process $proc$ls180.v:1074$3192
+  process $proc$ls180.v:1074$3180
     assign { } { }
     assign $1\main_pwm0_width_storage[31:0] 0
     sync always
@@ -114916,7 +114760,7 @@ module \ls180
       update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0]
   end
   attribute \src "ls180.v:1075.5-1075.30"
-  process $proc$ls180.v:1075$3193
+  process $proc$ls180.v:1075$3181
     assign { } { }
     assign $1\main_pwm0_width_re[0:0] 1'0
     sync always
@@ -114924,7 +114768,7 @@ module \ls180
       update \main_pwm0_width_re $1\main_pwm0_width_re[0:0]
   end
   attribute \src "ls180.v:1076.12-1076.44"
-  process $proc$ls180.v:1076$3194
+  process $proc$ls180.v:1076$3182
     assign { } { }
     assign $1\main_pwm0_period_storage[31:0] 0
     sync always
@@ -114932,7 +114776,7 @@ module \ls180
       update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0]
   end
   attribute \src "ls180.v:1077.5-1077.31"
-  process $proc$ls180.v:1077$3195
+  process $proc$ls180.v:1077$3183
     assign { } { }
     assign $1\main_pwm0_period_re[0:0] 1'0
     sync always
@@ -114940,7 +114784,7 @@ module \ls180
       update \main_pwm0_period_re $1\main_pwm0_period_re[0:0]
   end
   attribute \src "ls180.v:1081.12-1081.37"
-  process $proc$ls180.v:1081$3196
+  process $proc$ls180.v:1081$3184
     assign { } { }
     assign $1\main_pwm1_counter[31:0] 0
     sync always
@@ -114948,7 +114792,7 @@ module \ls180
       update \main_pwm1_counter $1\main_pwm1_counter[31:0]
   end
   attribute \src "ls180.v:1082.5-1082.36"
-  process $proc$ls180.v:1082$3197
+  process $proc$ls180.v:1082$3185
     assign { } { }
     assign $1\main_pwm1_enable_storage[0:0] 1'0
     sync always
@@ -114956,7 +114800,7 @@ module \ls180
       update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0]
   end
   attribute \src "ls180.v:1083.5-1083.31"
-  process $proc$ls180.v:1083$3198
+  process $proc$ls180.v:1083$3186
     assign { } { }
     assign $1\main_pwm1_enable_re[0:0] 1'0
     sync always
@@ -114964,7 +114808,7 @@ module \ls180
       update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0]
   end
   attribute \src "ls180.v:1084.12-1084.43"
-  process $proc$ls180.v:1084$3199
+  process $proc$ls180.v:1084$3187
     assign { } { }
     assign $1\main_pwm1_width_storage[31:0] 0
     sync always
@@ -114972,7 +114816,7 @@ module \ls180
       update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0]
   end
   attribute \src "ls180.v:1085.5-1085.30"
-  process $proc$ls180.v:1085$3200
+  process $proc$ls180.v:1085$3188
     assign { } { }
     assign $1\main_pwm1_width_re[0:0] 1'0
     sync always
@@ -114980,7 +114824,7 @@ module \ls180
       update \main_pwm1_width_re $1\main_pwm1_width_re[0:0]
   end
   attribute \src "ls180.v:1086.12-1086.44"
-  process $proc$ls180.v:1086$3201
+  process $proc$ls180.v:1086$3189
     assign { } { }
     assign $1\main_pwm1_period_storage[31:0] 0
     sync always
@@ -114988,7 +114832,7 @@ module \ls180
       update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0]
   end
   attribute \src "ls180.v:1087.5-1087.31"
-  process $proc$ls180.v:1087$3202
+  process $proc$ls180.v:1087$3190
     assign { } { }
     assign $1\main_pwm1_period_re[0:0] 1'0
     sync always
@@ -114996,7 +114840,7 @@ module \ls180
       update \main_pwm1_period_re $1\main_pwm1_period_re[0:0]
   end
   attribute \src "ls180.v:1091.11-1091.34"
-  process $proc$ls180.v:1091$3203
+  process $proc$ls180.v:1091$3191
     assign { } { }
     assign $1\main_i2c_storage[2:0] 3'000
     sync always
@@ -115004,7 +114848,7 @@ module \ls180
       update \main_i2c_storage $1\main_i2c_storage[2:0]
   end
   attribute \src "ls180.v:1092.5-1092.23"
-  process $proc$ls180.v:1092$3204
+  process $proc$ls180.v:1092$3192
     assign { } { }
     assign $1\main_i2c_re[0:0] 1'0
     sync always
@@ -115012,7 +114856,7 @@ module \ls180
       update \main_i2c_re $1\main_i2c_re[0:0]
   end
   attribute \src "ls180.v:1098.11-1098.46"
-  process $proc$ls180.v:1098$3205
+  process $proc$ls180.v:1098$3193
     assign { } { }
     assign $1\main_sdphy_clocker_storage[8:0] 9'100000000
     sync always
@@ -115020,7 +114864,7 @@ module \ls180
       update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0]
   end
   attribute \src "ls180.v:1099.5-1099.33"
-  process $proc$ls180.v:1099$3206
+  process $proc$ls180.v:1099$3194
     assign { } { }
     assign $1\main_sdphy_clocker_re[0:0] 1'0
     sync always
@@ -115028,7 +114872,7 @@ module \ls180
       update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0]
   end
   attribute \src "ls180.v:1101.5-1101.35"
-  process $proc$ls180.v:1101$3207
+  process $proc$ls180.v:1101$3195
     assign { } { }
     assign $1\main_sdphy_clocker_clk0[0:0] 1'0
     sync always
@@ -115036,7 +114880,7 @@ module \ls180
       update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0]
   end
   attribute \src "ls180.v:1103.11-1103.41"
-  process $proc$ls180.v:1103$3208
+  process $proc$ls180.v:1103$3196
     assign { } { }
     assign $1\main_sdphy_clocker_clks[8:0] 9'000000000
     sync always
@@ -115044,7 +114888,7 @@ module \ls180
       update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0]
   end
   attribute \src "ls180.v:1104.5-1104.35"
-  process $proc$ls180.v:1104$3209
+  process $proc$ls180.v:1104$3197
     assign { } { }
     assign $1\main_sdphy_clocker_clk1[0:0] 1'0
     sync always
@@ -115052,7 +114896,7 @@ module \ls180
       update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0]
   end
   attribute \src "ls180.v:1105.5-1105.36"
-  process $proc$ls180.v:1105$3210
+  process $proc$ls180.v:1105$3198
     assign { } { }
     assign $1\main_sdphy_clocker_clk_d[0:0] 1'0
     sync always
@@ -115060,7 +114904,7 @@ module \ls180
       update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0]
   end
   attribute \src "ls180.v:1109.5-1109.40"
-  process $proc$ls180.v:1109$3211
+  process $proc$ls180.v:1109$3199
     assign { } { }
     assign $0\main_sdphy_init_initialize_w[0:0] 1'0
     sync always
@@ -115068,7 +114912,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1114.5-1114.48"
-  process $proc$ls180.v:1114$3212
+  process $proc$ls180.v:1114$3200
     assign { } { }
     assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0
     sync always
@@ -115076,7 +114920,7 @@ module \ls180
       update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0]
   end
   attribute \src "ls180.v:1115.5-1115.50"
-  process $proc$ls180.v:1115$3213
+  process $proc$ls180.v:1115$3201
     assign { } { }
     assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
     sync always
@@ -115084,7 +114928,7 @@ module \ls180
       update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0]
   end
   attribute \src "ls180.v:1116.5-1116.51"
-  process $proc$ls180.v:1116$3214
+  process $proc$ls180.v:1116$3202
     assign { } { }
     assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
     sync always
@@ -115092,7 +114936,7 @@ module \ls180
       update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
   end
   attribute \src "ls180.v:1117.11-1117.57"
-  process $proc$ls180.v:1117$3215
+  process $proc$ls180.v:1117$3203
     assign { } { }
     assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
     sync always
@@ -115100,7 +114944,7 @@ module \ls180
       update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0]
   end
   attribute \src "ls180.v:1118.5-1118.52"
-  process $proc$ls180.v:1118$3216
+  process $proc$ls180.v:1118$3204
     assign { } { }
     assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
     sync always
@@ -115108,7 +114952,7 @@ module \ls180
       update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0]
   end
   attribute \src "ls180.v:1119.11-1119.39"
-  process $proc$ls180.v:1119$3217
+  process $proc$ls180.v:1119$3205
     assign { } { }
     assign $1\main_sdphy_init_count[7:0] 8'00000000
     sync always
@@ -115116,7 +114960,7 @@ module \ls180
       update \main_sdphy_init_count $1\main_sdphy_init_count[7:0]
   end
   attribute \src "ls180.v:1124.5-1124.48"
-  process $proc$ls180.v:1124$3218
+  process $proc$ls180.v:1124$3206
     assign { } { }
     assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
     sync always
@@ -115124,7 +114968,7 @@ module \ls180
       update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0]
   end
   attribute \src "ls180.v:1125.5-1125.50"
-  process $proc$ls180.v:1125$3219
+  process $proc$ls180.v:1125$3207
     assign { } { }
     assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
     sync always
@@ -115132,7 +114976,7 @@ module \ls180
       update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
   end
   attribute \src "ls180.v:1126.5-1126.51"
-  process $proc$ls180.v:1126$3220
+  process $proc$ls180.v:1126$3208
     assign { } { }
     assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
     sync always
@@ -115140,7 +114984,7 @@ module \ls180
       update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
   end
   attribute \src "ls180.v:1127.11-1127.57"
-  process $proc$ls180.v:1127$3221
+  process $proc$ls180.v:1127$3209
     assign { } { }
     assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000
     sync always
@@ -115148,7 +114992,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1128.5-1128.52"
-  process $proc$ls180.v:1128$3222
+  process $proc$ls180.v:1128$3210
     assign { } { }
     assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0
     sync always
@@ -115156,7 +115000,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1129.5-1129.38"
-  process $proc$ls180.v:1129$3223
+  process $proc$ls180.v:1129$3211
     assign { } { }
     assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0
     sync always
@@ -115164,7 +115008,7 @@ module \ls180
       update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0]
   end
   attribute \src "ls180.v:1130.5-1130.38"
-  process $proc$ls180.v:1130$3224
+  process $proc$ls180.v:1130$3212
     assign { } { }
     assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0
     sync always
@@ -115172,7 +115016,7 @@ module \ls180
       update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0]
   end
   attribute \src "ls180.v:1131.5-1131.37"
-  process $proc$ls180.v:1131$3225
+  process $proc$ls180.v:1131$3213
     assign { } { }
     assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0
     sync always
@@ -115180,7 +115024,7 @@ module \ls180
       update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0]
   end
   attribute \src "ls180.v:1132.11-1132.51"
-  process $proc$ls180.v:1132$3226
+  process $proc$ls180.v:1132$3214
     assign { } { }
     assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000
     sync always
@@ -115188,7 +115032,7 @@ module \ls180
       update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0]
   end
   attribute \src "ls180.v:1133.5-1133.32"
-  process $proc$ls180.v:1133$3227
+  process $proc$ls180.v:1133$3215
     assign { } { }
     assign $1\main_sdphy_cmdw_done[0:0] 1'0
     sync always
@@ -115196,7 +115040,7 @@ module \ls180
       update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0]
   end
   attribute \src "ls180.v:1134.11-1134.39"
-  process $proc$ls180.v:1134$3228
+  process $proc$ls180.v:1134$3216
     assign { } { }
     assign $1\main_sdphy_cmdw_count[7:0] 8'00000000
     sync always
@@ -115204,7 +115048,7 @@ module \ls180
       update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0]
   end
   attribute \src "ls180.v:1137.5-1137.49"
-  process $proc$ls180.v:1137$3229
+  process $proc$ls180.v:1137$3217
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0
     sync always
@@ -115212,7 +115056,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1138.5-1138.48"
-  process $proc$ls180.v:1138$3230
+  process $proc$ls180.v:1138$3218
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0
     sync always
@@ -115220,7 +115064,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1139.5-1139.55"
-  process $proc$ls180.v:1139$3231
+  process $proc$ls180.v:1139$3219
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0
     sync always
@@ -115228,7 +115072,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1141.5-1141.57"
-  process $proc$ls180.v:1141$3232
+  process $proc$ls180.v:1141$3220
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0
     sync always
@@ -115236,7 +115080,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1142.5-1142.58"
-  process $proc$ls180.v:1142$3233
+  process $proc$ls180.v:1142$3221
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
     sync always
@@ -115244,7 +115088,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1144.11-1144.64"
-  process $proc$ls180.v:1144$3234
+  process $proc$ls180.v:1144$3222
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000
     sync always
@@ -115252,7 +115096,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1145.5-1145.59"
-  process $proc$ls180.v:1145$3235
+  process $proc$ls180.v:1145$3223
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0
     sync always
@@ -115260,7 +115104,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1147.5-1147.48"
-  process $proc$ls180.v:1147$3236
+  process $proc$ls180.v:1147$3224
     assign { } { }
     assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0
     sync always
@@ -115268,7 +115112,7 @@ module \ls180
       update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0]
   end
   attribute \src "ls180.v:1148.5-1148.50"
-  process $proc$ls180.v:1148$3237
+  process $proc$ls180.v:1148$3225
     assign { } { }
     assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0
     sync always
@@ -115276,7 +115120,7 @@ module \ls180
       update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
   end
   attribute \src "ls180.v:1149.5-1149.51"
-  process $proc$ls180.v:1149$3238
+  process $proc$ls180.v:1149$3226
     assign { } { }
     assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0
     sync always
@@ -115284,7 +115128,7 @@ module \ls180
       update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
   end
   attribute \src "ls180.v:1150.11-1150.57"
-  process $proc$ls180.v:1150$3239
+  process $proc$ls180.v:1150$3227
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000
     sync always
@@ -115292,7 +115136,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1151.5-1151.52"
-  process $proc$ls180.v:1151$3240
+  process $proc$ls180.v:1151$3228
     assign { } { }
     assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0
     sync always
@@ -115300,7 +115144,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1152.5-1152.38"
-  process $proc$ls180.v:1152$3241
+  process $proc$ls180.v:1152$3229
     assign { } { }
     assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0
     sync always
@@ -115308,7 +115152,7 @@ module \ls180
       update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0]
   end
   attribute \src "ls180.v:1153.5-1153.38"
-  process $proc$ls180.v:1153$3242
+  process $proc$ls180.v:1153$3230
     assign { } { }
     assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0
     sync always
@@ -115316,7 +115160,7 @@ module \ls180
       update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0]
   end
   attribute \src "ls180.v:1154.5-1154.37"
-  process $proc$ls180.v:1154$3243
+  process $proc$ls180.v:1154$3231
     assign { } { }
     assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0
     sync always
@@ -115324,7 +115168,7 @@ module \ls180
       update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0]
   end
   attribute \src "ls180.v:1155.11-1155.53"
-  process $proc$ls180.v:1155$3244
+  process $proc$ls180.v:1155$3232
     assign { } { }
     assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000
     sync always
@@ -115332,7 +115176,7 @@ module \ls180
       update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0]
   end
   attribute \src "ls180.v:1156.5-1156.40"
-  process $proc$ls180.v:1156$3245
+  process $proc$ls180.v:1156$3233
     assign { } { }
     assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0
     sync always
@@ -115340,7 +115184,7 @@ module \ls180
       update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0]
   end
   attribute \src "ls180.v:1157.5-1157.40"
-  process $proc$ls180.v:1157$3246
+  process $proc$ls180.v:1157$3234
     assign { } { }
     assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0
     sync always
@@ -115348,7 +115192,7 @@ module \ls180
       update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0]
   end
   attribute \src "ls180.v:1158.5-1158.39"
-  process $proc$ls180.v:1158$3247
+  process $proc$ls180.v:1158$3235
     assign { } { }
     assign $1\main_sdphy_cmdr_source_last[0:0] 1'0
     sync always
@@ -115356,7 +115200,7 @@ module \ls180
       update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0]
   end
   attribute \src "ls180.v:1159.11-1159.53"
-  process $proc$ls180.v:1159$3248
+  process $proc$ls180.v:1159$3236
     assign { } { }
     assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
     sync always
@@ -115364,7 +115208,7 @@ module \ls180
       update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0]
   end
   attribute \src "ls180.v:116.5-116.49"
-  process $proc$ls180.v:116$2785
+  process $proc$ls180.v:116$2773
     assign { } { }
     assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
     sync always
@@ -115372,7 +115216,7 @@ module \ls180
       update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0]
   end
   attribute \src "ls180.v:1160.11-1160.55"
-  process $proc$ls180.v:1160$3249
+  process $proc$ls180.v:1160$3237
     assign { } { }
     assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000
     sync always
@@ -115380,7 +115224,7 @@ module \ls180
       update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0]
   end
   attribute \src "ls180.v:1161.12-1161.48"
-  process $proc$ls180.v:1161$3250
+  process $proc$ls180.v:1161$3238
     assign { } { }
     assign $1\main_sdphy_cmdr_timeout[31:0] 500000
     sync always
@@ -115388,7 +115232,7 @@ module \ls180
       update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0]
   end
   attribute \src "ls180.v:1162.11-1162.39"
-  process $proc$ls180.v:1162$3251
+  process $proc$ls180.v:1162$3239
     assign { } { }
     assign $1\main_sdphy_cmdr_count[7:0] 8'00000000
     sync always
@@ -115396,7 +115240,7 @@ module \ls180
       update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0]
   end
   attribute \src "ls180.v:1164.5-1164.46"
-  process $proc$ls180.v:1164$3252
+  process $proc$ls180.v:1164$3240
     assign { } { }
     assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0
     sync always
@@ -115404,7 +115248,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1175.5-1175.53"
-  process $proc$ls180.v:1175$3253
+  process $proc$ls180.v:1175$3241
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0
     sync always
@@ -115412,7 +115256,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
   end
   attribute \src "ls180.v:118.5-118.49"
-  process $proc$ls180.v:118$2786
+  process $proc$ls180.v:118$2774
     assign { } { }
     assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0
     sync always
@@ -115420,7 +115264,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1180.5-1180.36"
-  process $proc$ls180.v:1180$3254
+  process $proc$ls180.v:1180$3242
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0
     sync always
@@ -115428,7 +115272,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0]
   end
   attribute \src "ls180.v:1183.5-1183.53"
-  process $proc$ls180.v:1183$3255
+  process $proc$ls180.v:1183$3243
     assign { } { }
     assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0
     sync always
@@ -115436,7 +115280,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1184.5-1184.52"
-  process $proc$ls180.v:1184$3256
+  process $proc$ls180.v:1184$3244
     assign { } { }
     assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0
     sync always
@@ -115444,7 +115288,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1188.5-1188.55"
-  process $proc$ls180.v:1188$3257
+  process $proc$ls180.v:1188$3245
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0
     sync always
@@ -115452,7 +115296,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
   end
   attribute \src "ls180.v:1189.5-1189.54"
-  process $proc$ls180.v:1189$3258
+  process $proc$ls180.v:1189$3246
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0
     sync always
@@ -115460,7 +115304,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
   end
   attribute \src "ls180.v:1190.11-1190.68"
-  process $proc$ls180.v:1190$3259
+  process $proc$ls180.v:1190$3247
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000
     sync always
@@ -115468,7 +115312,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
   end
   attribute \src "ls180.v:1191.11-1191.81"
-  process $proc$ls180.v:1191$3260
+  process $proc$ls180.v:1191$3248
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000
     sync always
@@ -115476,7 +115320,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
   end
   attribute \src "ls180.v:1192.11-1192.54"
-  process $proc$ls180.v:1192$3261
+  process $proc$ls180.v:1192$3249
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
     sync always
@@ -115484,7 +115328,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0]
   end
   attribute \src "ls180.v:1194.5-1194.53"
-  process $proc$ls180.v:1194$3262
+  process $proc$ls180.v:1194$3250
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
     sync always
@@ -115492,7 +115336,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
   end
   attribute \src "ls180.v:1205.5-1205.49"
-  process $proc$ls180.v:1205$3263
+  process $proc$ls180.v:1205$3251
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0
     sync always
@@ -115500,7 +115344,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
   end
   attribute \src "ls180.v:1207.5-1207.49"
-  process $proc$ls180.v:1207$3264
+  process $proc$ls180.v:1207$3252
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0
     sync always
@@ -115508,7 +115352,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
   end
   attribute \src "ls180.v:1208.5-1208.48"
-  process $proc$ls180.v:1208$3265
+  process $proc$ls180.v:1208$3253
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0
     sync always
@@ -115516,7 +115360,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
   end
   attribute \src "ls180.v:1209.11-1209.62"
-  process $proc$ls180.v:1209$3266
+  process $proc$ls180.v:1209$3254
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000
     sync always
@@ -115524,7 +115368,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
   end
   attribute \src "ls180.v:1210.5-1210.38"
-  process $proc$ls180.v:1210$3267
+  process $proc$ls180.v:1210$3255
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0
     sync always
@@ -115532,7 +115376,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0]
   end
   attribute \src "ls180.v:1215.5-1215.49"
-  process $proc$ls180.v:1215$3268
+  process $proc$ls180.v:1215$3256
     assign { } { }
     assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
     sync always
@@ -115540,7 +115384,7 @@ module \ls180
       update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0]
   end
   attribute \src "ls180.v:1216.5-1216.51"
-  process $proc$ls180.v:1216$3269
+  process $proc$ls180.v:1216$3257
     assign { } { }
     assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0
     sync always
@@ -115548,7 +115392,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1217.5-1217.52"
-  process $proc$ls180.v:1217$3270
+  process $proc$ls180.v:1217$3258
     assign { } { }
     assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0
     sync always
@@ -115556,7 +115400,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1218.11-1218.58"
-  process $proc$ls180.v:1218$3271
+  process $proc$ls180.v:1218$3259
     assign { } { }
     assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
     sync always
@@ -115564,7 +115408,7 @@ module \ls180
       update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0]
   end
   attribute \src "ls180.v:1219.5-1219.53"
-  process $proc$ls180.v:1219$3272
+  process $proc$ls180.v:1219$3260
     assign { } { }
     assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0
     sync always
@@ -115572,7 +115416,7 @@ module \ls180
       update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
   end
   attribute \src "ls180.v:1220.5-1220.39"
-  process $proc$ls180.v:1220$3273
+  process $proc$ls180.v:1220$3261
     assign { } { }
     assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0
     sync always
@@ -115580,7 +115424,7 @@ module \ls180
       update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0]
   end
   attribute \src "ls180.v:1221.5-1221.39"
-  process $proc$ls180.v:1221$3274
+  process $proc$ls180.v:1221$3262
     assign { } { }
     assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0
     sync always
@@ -115588,7 +115432,7 @@ module \ls180
       update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0]
   end
   attribute \src "ls180.v:1222.5-1222.39"
-  process $proc$ls180.v:1222$3275
+  process $proc$ls180.v:1222$3263
     assign { } { }
     assign $1\main_sdphy_dataw_sink_first[0:0] 1'0
     sync always
@@ -115596,7 +115440,7 @@ module \ls180
       update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0]
   end
   attribute \src "ls180.v:1223.5-1223.38"
-  process $proc$ls180.v:1223$3276
+  process $proc$ls180.v:1223$3264
     assign { } { }
     assign $1\main_sdphy_dataw_sink_last[0:0] 1'0
     sync always
@@ -115604,7 +115448,7 @@ module \ls180
       update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0]
   end
   attribute \src "ls180.v:1224.11-1224.52"
-  process $proc$ls180.v:1224$3277
+  process $proc$ls180.v:1224$3265
     assign { } { }
     assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000
     sync always
@@ -115612,7 +115456,7 @@ module \ls180
       update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0]
   end
   attribute \src "ls180.v:1225.5-1225.33"
-  process $proc$ls180.v:1225$3278
+  process $proc$ls180.v:1225$3266
     assign { } { }
     assign $1\main_sdphy_dataw_stop[0:0] 1'0
     sync always
@@ -115620,7 +115464,7 @@ module \ls180
       update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0]
   end
   attribute \src "ls180.v:1226.11-1226.40"
-  process $proc$ls180.v:1226$3279
+  process $proc$ls180.v:1226$3267
     assign { } { }
     assign $1\main_sdphy_dataw_count[7:0] 8'00000000
     sync always
@@ -115628,7 +115472,7 @@ module \ls180
       update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0]
   end
   attribute \src "ls180.v:1227.5-1227.50"
-  process $proc$ls180.v:1227$3280
+  process $proc$ls180.v:1227$3268
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0
     sync always
@@ -115636,7 +115480,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1229.5-1229.50"
-  process $proc$ls180.v:1229$3281
+  process $proc$ls180.v:1229$3269
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0
     sync always
@@ -115644,7 +115488,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1230.5-1230.49"
-  process $proc$ls180.v:1230$3282
+  process $proc$ls180.v:1230$3270
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0
     sync always
@@ -115652,7 +115496,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1231.5-1231.56"
-  process $proc$ls180.v:1231$3283
+  process $proc$ls180.v:1231$3271
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0
     sync always
@@ -115660,7 +115504,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1232.5-1232.58"
-  process $proc$ls180.v:1232$3284
+  process $proc$ls180.v:1232$3272
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0
     sync always
@@ -115668,7 +115512,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1233.5-1233.58"
-  process $proc$ls180.v:1233$3285
+  process $proc$ls180.v:1233$3273
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0
     sync always
@@ -115676,7 +115520,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1234.5-1234.59"
-  process $proc$ls180.v:1234$3286
+  process $proc$ls180.v:1234$3274
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
     sync always
@@ -115684,7 +115528,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1235.11-1235.65"
-  process $proc$ls180.v:1235$3287
+  process $proc$ls180.v:1235$3275
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000
     sync always
@@ -115692,7 +115536,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1236.11-1236.65"
-  process $proc$ls180.v:1236$3288
+  process $proc$ls180.v:1236$3276
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000
     sync always
@@ -115700,7 +115544,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1237.5-1237.60"
-  process $proc$ls180.v:1237$3289
+  process $proc$ls180.v:1237$3277
     assign { } { }
     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0
     sync always
@@ -115708,7 +115552,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1238.5-1238.34"
-  process $proc$ls180.v:1238$3290
+  process $proc$ls180.v:1238$3278
     assign { } { }
     assign $1\main_sdphy_dataw_start[0:0] 1'0
     sync always
@@ -115716,7 +115560,7 @@ module \ls180
       update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0]
   end
   attribute \src "ls180.v:1239.5-1239.34"
-  process $proc$ls180.v:1239$3291
+  process $proc$ls180.v:1239$3279
     assign { } { }
     assign $1\main_sdphy_dataw_valid[0:0] 1'0
     sync always
@@ -115724,7 +115568,7 @@ module \ls180
       update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0]
   end
   attribute \src "ls180.v:1240.5-1240.34"
-  process $proc$ls180.v:1240$3292
+  process $proc$ls180.v:1240$3280
     assign { } { }
     assign $1\main_sdphy_dataw_error[0:0] 1'0
     sync always
@@ -115732,7 +115576,7 @@ module \ls180
       update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0]
   end
   attribute \src "ls180.v:1242.5-1242.47"
-  process $proc$ls180.v:1242$3293
+  process $proc$ls180.v:1242$3281
     assign { } { }
     assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0
     sync always
@@ -115740,7 +115584,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1253.5-1253.54"
-  process $proc$ls180.v:1253$3294
+  process $proc$ls180.v:1253$3282
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
     sync always
@@ -115748,7 +115592,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0]
   end
   attribute \src "ls180.v:1258.5-1258.37"
-  process $proc$ls180.v:1258$3295
+  process $proc$ls180.v:1258$3283
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0
     sync always
@@ -115756,7 +115600,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0]
   end
   attribute \src "ls180.v:1261.5-1261.54"
-  process $proc$ls180.v:1261$3296
+  process $proc$ls180.v:1261$3284
     assign { } { }
     assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0
     sync always
@@ -115764,7 +115608,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1262.5-1262.53"
-  process $proc$ls180.v:1262$3297
+  process $proc$ls180.v:1262$3285
     assign { } { }
     assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0
     sync always
@@ -115772,7 +115616,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1266.5-1266.56"
-  process $proc$ls180.v:1266$3298
+  process $proc$ls180.v:1266$3286
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0
     sync always
@@ -115780,7 +115624,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0]
   end
   attribute \src "ls180.v:1267.5-1267.55"
-  process $proc$ls180.v:1267$3299
+  process $proc$ls180.v:1267$3287
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0
     sync always
@@ -115788,7 +115632,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0]
   end
   attribute \src "ls180.v:1268.11-1268.69"
-  process $proc$ls180.v:1268$3300
+  process $proc$ls180.v:1268$3288
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000
     sync always
@@ -115796,7 +115640,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
   end
   attribute \src "ls180.v:1269.11-1269.82"
-  process $proc$ls180.v:1269$3301
+  process $proc$ls180.v:1269$3289
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000
     sync always
@@ -115804,7 +115648,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
   end
   attribute \src "ls180.v:1270.11-1270.55"
-  process $proc$ls180.v:1270$3302
+  process $proc$ls180.v:1270$3290
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
     sync always
@@ -115812,7 +115656,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0]
   end
   attribute \src "ls180.v:1272.5-1272.54"
-  process $proc$ls180.v:1272$3303
+  process $proc$ls180.v:1272$3291
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
     sync always
@@ -115820,7 +115664,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
   end
   attribute \src "ls180.v:1283.5-1283.50"
-  process $proc$ls180.v:1283$3304
+  process $proc$ls180.v:1283$3292
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0
     sync always
@@ -115828,7 +115672,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0]
   end
   attribute \src "ls180.v:1285.5-1285.50"
-  process $proc$ls180.v:1285$3305
+  process $proc$ls180.v:1285$3293
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0
     sync always
@@ -115836,7 +115680,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0]
   end
   attribute \src "ls180.v:1286.5-1286.49"
-  process $proc$ls180.v:1286$3306
+  process $proc$ls180.v:1286$3294
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0
     sync always
@@ -115844,7 +115688,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0]
   end
   attribute \src "ls180.v:1287.11-1287.63"
-  process $proc$ls180.v:1287$3307
+  process $proc$ls180.v:1287$3295
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000
     sync always
@@ -115852,7 +115696,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
   end
   attribute \src "ls180.v:1288.5-1288.39"
-  process $proc$ls180.v:1288$3308
+  process $proc$ls180.v:1288$3296
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0
     sync always
@@ -115860,7 +115704,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0]
   end
   attribute \src "ls180.v:1291.5-1291.50"
-  process $proc$ls180.v:1291$3309
+  process $proc$ls180.v:1291$3297
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0
     sync always
@@ -115868,7 +115712,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1292.5-1292.49"
-  process $proc$ls180.v:1292$3310
+  process $proc$ls180.v:1292$3298
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0
     sync always
@@ -115876,7 +115720,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1293.5-1293.56"
-  process $proc$ls180.v:1293$3311
+  process $proc$ls180.v:1293$3299
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0
     sync always
@@ -115884,7 +115728,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1295.5-1295.58"
-  process $proc$ls180.v:1295$3312
+  process $proc$ls180.v:1295$3300
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0
     sync always
@@ -115892,7 +115736,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1296.5-1296.59"
-  process $proc$ls180.v:1296$3313
+  process $proc$ls180.v:1296$3301
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
     sync always
@@ -115900,7 +115744,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1298.11-1298.65"
-  process $proc$ls180.v:1298$3314
+  process $proc$ls180.v:1298$3302
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000
     sync always
@@ -115908,23 +115752,15 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1299.5-1299.60"
-  process $proc$ls180.v:1299$3315
+  process $proc$ls180.v:1299$3303
     assign { } { }
     assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0
     sync always
       update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0]
     sync init
   end
-  attribute \src "ls180.v:130.5-130.69"
-  process $proc$ls180.v:130$2787
-    assign { } { }
-    assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0
-    sync always
-      update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
-    sync init
-  end
   attribute \src "ls180.v:1301.5-1301.49"
-  process $proc$ls180.v:1301$3316
+  process $proc$ls180.v:1301$3304
     assign { } { }
     assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
     sync always
@@ -115932,7 +115768,7 @@ module \ls180
       update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0]
   end
   attribute \src "ls180.v:1302.5-1302.51"
-  process $proc$ls180.v:1302$3317
+  process $proc$ls180.v:1302$3305
     assign { } { }
     assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0
     sync always
@@ -115940,7 +115776,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1303.5-1303.52"
-  process $proc$ls180.v:1303$3318
+  process $proc$ls180.v:1303$3306
     assign { } { }
     assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0
     sync always
@@ -115948,7 +115784,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1304.11-1304.58"
-  process $proc$ls180.v:1304$3319
+  process $proc$ls180.v:1304$3307
     assign { } { }
     assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000
     sync always
@@ -115956,7 +115792,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1305.5-1305.53"
-  process $proc$ls180.v:1305$3320
+  process $proc$ls180.v:1305$3308
     assign { } { }
     assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0
     sync always
@@ -115964,7 +115800,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1306.5-1306.39"
-  process $proc$ls180.v:1306$3321
+  process $proc$ls180.v:1306$3309
     assign { } { }
     assign $1\main_sdphy_datar_sink_valid[0:0] 1'0
     sync always
@@ -115972,7 +115808,7 @@ module \ls180
       update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0]
   end
   attribute \src "ls180.v:1307.5-1307.39"
-  process $proc$ls180.v:1307$3322
+  process $proc$ls180.v:1307$3310
     assign { } { }
     assign $1\main_sdphy_datar_sink_ready[0:0] 1'0
     sync always
@@ -115980,7 +115816,7 @@ module \ls180
       update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0]
   end
   attribute \src "ls180.v:1308.5-1308.38"
-  process $proc$ls180.v:1308$3323
+  process $proc$ls180.v:1308$3311
     assign { } { }
     assign $1\main_sdphy_datar_sink_last[0:0] 1'0
     sync always
@@ -115988,7 +115824,7 @@ module \ls180
       update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0]
   end
   attribute \src "ls180.v:1309.11-1309.61"
-  process $proc$ls180.v:1309$3324
+  process $proc$ls180.v:1309$3312
     assign { } { }
     assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000
     sync always
@@ -115996,7 +115832,7 @@ module \ls180
       update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0]
   end
   attribute \src "ls180.v:1310.5-1310.41"
-  process $proc$ls180.v:1310$3325
+  process $proc$ls180.v:1310$3313
     assign { } { }
     assign $1\main_sdphy_datar_source_valid[0:0] 1'0
     sync always
@@ -116004,7 +115840,7 @@ module \ls180
       update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0]
   end
   attribute \src "ls180.v:1311.5-1311.41"
-  process $proc$ls180.v:1311$3326
+  process $proc$ls180.v:1311$3314
     assign { } { }
     assign $1\main_sdphy_datar_source_ready[0:0] 1'0
     sync always
@@ -116012,7 +115848,7 @@ module \ls180
       update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0]
   end
   attribute \src "ls180.v:1312.5-1312.41"
-  process $proc$ls180.v:1312$3327
+  process $proc$ls180.v:1312$3315
     assign { } { }
     assign $0\main_sdphy_datar_source_first[0:0] 1'0
     sync always
@@ -116020,7 +115856,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1313.5-1313.40"
-  process $proc$ls180.v:1313$3328
+  process $proc$ls180.v:1313$3316
     assign { } { }
     assign $1\main_sdphy_datar_source_last[0:0] 1'0
     sync always
@@ -116028,7 +115864,7 @@ module \ls180
       update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0]
   end
   attribute \src "ls180.v:1314.11-1314.54"
-  process $proc$ls180.v:1314$3329
+  process $proc$ls180.v:1314$3317
     assign { } { }
     assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000
     sync always
@@ -116036,7 +115872,7 @@ module \ls180
       update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0]
   end
   attribute \src "ls180.v:1315.11-1315.56"
-  process $proc$ls180.v:1315$3330
+  process $proc$ls180.v:1315$3318
     assign { } { }
     assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000
     sync always
@@ -116044,7 +115880,7 @@ module \ls180
       update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0]
   end
   attribute \src "ls180.v:1316.5-1316.33"
-  process $proc$ls180.v:1316$3331
+  process $proc$ls180.v:1316$3319
     assign { } { }
     assign $1\main_sdphy_datar_stop[0:0] 1'0
     sync always
@@ -116052,7 +115888,7 @@ module \ls180
       update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0]
   end
   attribute \src "ls180.v:1317.12-1317.49"
-  process $proc$ls180.v:1317$3332
+  process $proc$ls180.v:1317$3320
     assign { } { }
     assign $1\main_sdphy_datar_timeout[31:0] 500000
     sync always
@@ -116060,23 +115896,39 @@ module \ls180
       update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0]
   end
   attribute \src "ls180.v:1318.11-1318.41"
-  process $proc$ls180.v:1318$3333
+  process $proc$ls180.v:1318$3321
     assign { } { }
     assign $1\main_sdphy_datar_count[9:0] 10'0000000000
     sync always
     sync init
       update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0]
   end
+  attribute \src "ls180.v:132.5-132.74"
+  process $proc$ls180.v:132$2775
+    assign { } { }
+    assign $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] 1'0
+    sync always
+      update \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
+    sync init
+  end
   attribute \src "ls180.v:1320.5-1320.48"
-  process $proc$ls180.v:1320$3334
+  process $proc$ls180.v:1320$3322
     assign { } { }
     assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0
     sync always
       update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0]
     sync init
   end
+  attribute \src "ls180.v:133.11-133.24"
+  process $proc$ls180.v:133$2776
+    assign { } { }
+    assign $0\eint_1[2:0] 3'000
+    sync always
+      update \eint_1 $0\eint_1[2:0]
+    sync init
+  end
   attribute \src "ls180.v:1331.5-1331.55"
-  process $proc$ls180.v:1331$3335
+  process $proc$ls180.v:1331$3323
     assign { } { }
     assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0
     sync always
@@ -116084,7 +115936,7 @@ module \ls180
       update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0]
   end
   attribute \src "ls180.v:1336.5-1336.38"
-  process $proc$ls180.v:1336$3336
+  process $proc$ls180.v:1336$3324
     assign { } { }
     assign $1\main_sdphy_datar_datar_run[0:0] 1'0
     sync always
@@ -116092,23 +115944,15 @@ module \ls180
       update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0]
   end
   attribute \src "ls180.v:1339.5-1339.55"
-  process $proc$ls180.v:1339$3337
+  process $proc$ls180.v:1339$3325
     assign { } { }
     assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0
     sync always
       update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:134.5-134.72"
-  process $proc$ls180.v:134$2788
-    assign { } { }
-    assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0
-    sync always
-      update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
-    sync init
-  end
   attribute \src "ls180.v:1340.5-1340.54"
-  process $proc$ls180.v:1340$3338
+  process $proc$ls180.v:1340$3326
     assign { } { }
     assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0
     sync always
@@ -116116,7 +115960,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1344.5-1344.57"
-  process $proc$ls180.v:1344$3339
+  process $proc$ls180.v:1344$3327
     assign { } { }
     assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0
     sync always
@@ -116124,7 +115968,7 @@ module \ls180
       update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0]
   end
   attribute \src "ls180.v:1345.5-1345.56"
-  process $proc$ls180.v:1345$3340
+  process $proc$ls180.v:1345$3328
     assign { } { }
     assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0
     sync always
@@ -116132,7 +115976,7 @@ module \ls180
       update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0]
   end
   attribute \src "ls180.v:1346.11-1346.70"
-  process $proc$ls180.v:1346$3341
+  process $proc$ls180.v:1346$3329
     assign { } { }
     assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000
     sync always
@@ -116140,7 +115984,7 @@ module \ls180
       update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0]
   end
   attribute \src "ls180.v:1347.11-1347.83"
-  process $proc$ls180.v:1347$3342
+  process $proc$ls180.v:1347$3330
     assign { } { }
     assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00
     sync always
@@ -116148,15 +115992,23 @@ module \ls180
       update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
   end
   attribute \src "ls180.v:1348.5-1348.50"
-  process $proc$ls180.v:1348$3343
+  process $proc$ls180.v:1348$3331
     assign { } { }
     assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0
     sync always
     sync init
       update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0]
   end
+  attribute \src "ls180.v:135.5-135.69"
+  process $proc$ls180.v:135$2777
+    assign { } { }
+    assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0
+    sync always
+      update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
+    sync init
+  end
   attribute \src "ls180.v:1350.5-1350.55"
-  process $proc$ls180.v:1350$3344
+  process $proc$ls180.v:1350$3332
     assign { } { }
     assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
     sync always
@@ -116164,7 +116016,7 @@ module \ls180
       update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0]
   end
   attribute \src "ls180.v:1361.5-1361.51"
-  process $proc$ls180.v:1361$3345
+  process $proc$ls180.v:1361$3333
     assign { } { }
     assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0
     sync always
@@ -116172,7 +116024,7 @@ module \ls180
       update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0]
   end
   attribute \src "ls180.v:1363.5-1363.51"
-  process $proc$ls180.v:1363$3346
+  process $proc$ls180.v:1363$3334
     assign { } { }
     assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0
     sync always
@@ -116180,7 +116032,7 @@ module \ls180
       update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0]
   end
   attribute \src "ls180.v:1364.5-1364.50"
-  process $proc$ls180.v:1364$3347
+  process $proc$ls180.v:1364$3335
     assign { } { }
     assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0
     sync always
@@ -116188,7 +116040,7 @@ module \ls180
       update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0]
   end
   attribute \src "ls180.v:1365.11-1365.64"
-  process $proc$ls180.v:1365$3348
+  process $proc$ls180.v:1365$3336
     assign { } { }
     assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000
     sync always
@@ -116196,7 +116048,7 @@ module \ls180
       update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0]
   end
   attribute \src "ls180.v:1366.5-1366.40"
-  process $proc$ls180.v:1366$3349
+  process $proc$ls180.v:1366$3337
     assign { } { }
     assign $1\main_sdphy_datar_datar_reset[0:0] 1'0
     sync always
@@ -116204,7 +116056,7 @@ module \ls180
       update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0]
   end
   attribute \src "ls180.v:1368.5-1368.35"
-  process $proc$ls180.v:1368$3350
+  process $proc$ls180.v:1368$3338
     assign { } { }
     assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0
     sync always
@@ -116212,7 +116064,7 @@ module \ls180
       update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0]
   end
   attribute \src "ls180.v:1371.11-1371.42"
-  process $proc$ls180.v:1371$3351
+  process $proc$ls180.v:1371$3339
     assign { } { }
     assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000
     sync always
@@ -116220,7 +116072,7 @@ module \ls180
       update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0]
   end
   attribute \src "ls180.v:1384.12-1384.52"
-  process $proc$ls180.v:1384$3352
+  process $proc$ls180.v:1384$3340
     assign { } { }
     assign $1\main_sdcore_cmd_argument_storage[31:0] 0
     sync always
@@ -116228,7 +116080,7 @@ module \ls180
       update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0]
   end
   attribute \src "ls180.v:1385.5-1385.39"
-  process $proc$ls180.v:1385$3353
+  process $proc$ls180.v:1385$3341
     assign { } { }
     assign $1\main_sdcore_cmd_argument_re[0:0] 1'0
     sync always
@@ -116236,7 +116088,7 @@ module \ls180
       update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0]
   end
   attribute \src "ls180.v:1386.12-1386.51"
-  process $proc$ls180.v:1386$3354
+  process $proc$ls180.v:1386$3342
     assign { } { }
     assign $1\main_sdcore_cmd_command_storage[31:0] 0
     sync always
@@ -116244,7 +116096,7 @@ module \ls180
       update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0]
   end
   attribute \src "ls180.v:1387.5-1387.38"
-  process $proc$ls180.v:1387$3355
+  process $proc$ls180.v:1387$3343
     assign { } { }
     assign $1\main_sdcore_cmd_command_re[0:0] 1'0
     sync always
@@ -116252,7 +116104,7 @@ module \ls180
       update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0]
   end
   attribute \src "ls180.v:1391.5-1391.34"
-  process $proc$ls180.v:1391$3356
+  process $proc$ls180.v:1391$3344
     assign { } { }
     assign $0\main_sdcore_cmd_send_w[0:0] 1'0
     sync always
@@ -116260,7 +116112,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1392.13-1392.53"
-  process $proc$ls180.v:1392$3357
+  process $proc$ls180.v:1392$3345
     assign { } { }
     assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
     sync always
@@ -116268,7 +116120,7 @@ module \ls180
       update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0]
   end
   attribute \src "ls180.v:1398.11-1398.51"
-  process $proc$ls180.v:1398$3358
+  process $proc$ls180.v:1398$3346
     assign { } { }
     assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000
     sync always
@@ -116276,7 +116128,7 @@ module \ls180
       update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0]
   end
   attribute \src "ls180.v:1399.5-1399.39"
-  process $proc$ls180.v:1399$3359
+  process $proc$ls180.v:1399$3347
     assign { } { }
     assign $1\main_sdcore_block_length_re[0:0] 1'0
     sync always
@@ -116284,7 +116136,7 @@ module \ls180
       update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0]
   end
   attribute \src "ls180.v:1400.12-1400.51"
-  process $proc$ls180.v:1400$3360
+  process $proc$ls180.v:1400$3348
     assign { } { }
     assign $1\main_sdcore_block_count_storage[31:0] 0
     sync always
@@ -116292,7 +116144,7 @@ module \ls180
       update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0]
   end
   attribute \src "ls180.v:1401.5-1401.38"
-  process $proc$ls180.v:1401$3361
+  process $proc$ls180.v:1401$3349
     assign { } { }
     assign $1\main_sdcore_block_count_re[0:0] 1'0
     sync always
@@ -116300,31 +116152,31 @@ module \ls180
       update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0]
   end
   attribute \src "ls180.v:1402.11-1402.51"
-  process $proc$ls180.v:1402$3362
+  process $proc$ls180.v:1402$3350
     assign { } { }
     assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000
     sync always
     sync init
       update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0]
   end
-  attribute \src "ls180.v:141.5-141.74"
-  process $proc$ls180.v:141$2789
+  attribute \src "ls180.v:142.5-142.74"
+  process $proc$ls180.v:142$2778
     assign { } { }
     assign $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] 1'0
     sync always
       update \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
     sync init
   end
-  attribute \src "ls180.v:143.12-143.78"
-  process $proc$ls180.v:143$2790
+  attribute \src "ls180.v:144.5-144.72"
+  process $proc$ls180.v:144$2779
     assign { } { }
-    assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000
+    assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0
     sync always
-      update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
+      update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
     sync init
   end
   attribute \src "ls180.v:1444.11-1444.47"
-  process $proc$ls180.v:1444$3363
+  process $proc$ls180.v:1444$3351
     assign { } { }
     assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000
     sync always
@@ -116332,7 +116184,7 @@ module \ls180
       update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0]
   end
   attribute \src "ls180.v:1448.5-1448.49"
-  process $proc$ls180.v:1448$3364
+  process $proc$ls180.v:1448$3352
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
     sync always
@@ -116340,7 +116192,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0]
   end
   attribute \src "ls180.v:1452.5-1452.51"
-  process $proc$ls180.v:1452$3365
+  process $proc$ls180.v:1452$3353
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0
     sync always
@@ -116348,7 +116200,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0]
   end
   attribute \src "ls180.v:1453.5-1453.51"
-  process $proc$ls180.v:1453$3366
+  process $proc$ls180.v:1453$3354
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0
     sync always
@@ -116356,7 +116208,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0]
   end
   attribute \src "ls180.v:1454.5-1454.51"
-  process $proc$ls180.v:1454$3367
+  process $proc$ls180.v:1454$3355
     assign { } { }
     assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0
     sync always
@@ -116364,7 +116216,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1455.5-1455.50"
-  process $proc$ls180.v:1455$3368
+  process $proc$ls180.v:1455$3356
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0
     sync always
@@ -116372,7 +116224,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0]
   end
   attribute \src "ls180.v:1456.11-1456.64"
-  process $proc$ls180.v:1456$3369
+  process $proc$ls180.v:1456$3357
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000
     sync always
@@ -116380,7 +116232,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0]
   end
   attribute \src "ls180.v:1457.11-1457.48"
-  process $proc$ls180.v:1457$3370
+  process $proc$ls180.v:1457$3358
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000
     sync always
@@ -116388,7 +116240,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0]
   end
   attribute \src "ls180.v:1458.12-1458.59"
-  process $proc$ls180.v:1458$3371
+  process $proc$ls180.v:1458$3359
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000
     sync always
@@ -116396,7 +116248,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
   end
   attribute \src "ls180.v:1462.12-1462.55"
-  process $proc$ls180.v:1462$3372
+  process $proc$ls180.v:1462$3360
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000
     sync always
@@ -116404,7 +116256,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0]
   end
   attribute \src "ls180.v:1465.12-1465.59"
-  process $proc$ls180.v:1465$3373
+  process $proc$ls180.v:1465$3361
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000
     sync always
@@ -116412,7 +116264,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
   end
   attribute \src "ls180.v:1469.12-1469.55"
-  process $proc$ls180.v:1469$3374
+  process $proc$ls180.v:1469$3362
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000
     sync always
@@ -116420,7 +116272,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
   end
   attribute \src "ls180.v:1472.12-1472.59"
-  process $proc$ls180.v:1472$3375
+  process $proc$ls180.v:1472$3363
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000
     sync always
@@ -116428,7 +116280,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
   end
   attribute \src "ls180.v:1476.12-1476.55"
-  process $proc$ls180.v:1476$3376
+  process $proc$ls180.v:1476$3364
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000
     sync always
@@ -116436,15 +116288,23 @@ module \ls180
       update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0]
   end
   attribute \src "ls180.v:1479.12-1479.59"
-  process $proc$ls180.v:1479$3377
+  process $proc$ls180.v:1479$3365
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
   end
+  attribute \src "ls180.v:148.12-148.78"
+  process $proc$ls180.v:148$2780
+    assign { } { }
+    assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000
+    sync always
+      update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
+    sync init
+  end
   attribute \src "ls180.v:1483.12-1483.55"
-  process $proc$ls180.v:1483$3378
+  process $proc$ls180.v:1483$3366
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000
     sync always
@@ -116452,7 +116312,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0]
   end
   attribute \src "ls180.v:1486.12-1486.54"
-  process $proc$ls180.v:1486$3379
+  process $proc$ls180.v:1486$3367
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000
     sync always
@@ -116460,7 +116320,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0]
   end
   attribute \src "ls180.v:1487.12-1487.54"
-  process $proc$ls180.v:1487$3380
+  process $proc$ls180.v:1487$3368
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000
     sync always
@@ -116468,7 +116328,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0]
   end
   attribute \src "ls180.v:1488.12-1488.54"
-  process $proc$ls180.v:1488$3381
+  process $proc$ls180.v:1488$3369
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000
     sync always
@@ -116476,7 +116336,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0]
   end
   attribute \src "ls180.v:1489.12-1489.54"
-  process $proc$ls180.v:1489$3382
+  process $proc$ls180.v:1489$3370
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000
     sync always
@@ -116484,7 +116344,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0]
   end
   attribute \src "ls180.v:1490.5-1490.48"
-  process $proc$ls180.v:1490$3383
+  process $proc$ls180.v:1490$3371
     assign { } { }
     assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0
     sync always
@@ -116492,7 +116352,7 @@ module \ls180
       update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0]
   end
   attribute \src "ls180.v:1491.5-1491.48"
-  process $proc$ls180.v:1491$3384
+  process $proc$ls180.v:1491$3372
     assign { } { }
     assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0
     sync always
@@ -116500,7 +116360,7 @@ module \ls180
       update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0]
   end
   attribute \src "ls180.v:1492.5-1492.48"
-  process $proc$ls180.v:1492$3385
+  process $proc$ls180.v:1492$3373
     assign { } { }
     assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0
     sync always
@@ -116508,7 +116368,7 @@ module \ls180
       update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0]
   end
   attribute \src "ls180.v:1493.5-1493.47"
-  process $proc$ls180.v:1493$3386
+  process $proc$ls180.v:1493$3374
     assign { } { }
     assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0
     sync always
@@ -116516,7 +116376,7 @@ module \ls180
       update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0]
   end
   attribute \src "ls180.v:1494.11-1494.61"
-  process $proc$ls180.v:1494$3387
+  process $proc$ls180.v:1494$3375
     assign { } { }
     assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000
     sync always
@@ -116524,7 +116384,7 @@ module \ls180
       update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0]
   end
   attribute \src "ls180.v:1495.5-1495.50"
-  process $proc$ls180.v:1495$3388
+  process $proc$ls180.v:1495$3376
     assign { } { }
     assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0
     sync always
@@ -116532,7 +116392,7 @@ module \ls180
       update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0]
   end
   attribute \src "ls180.v:1497.5-1497.50"
-  process $proc$ls180.v:1497$3389
+  process $proc$ls180.v:1497$3377
     assign { } { }
     assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0
     sync always
@@ -116540,7 +116400,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1500.11-1500.47"
-  process $proc$ls180.v:1500$3390
+  process $proc$ls180.v:1500$3378
     assign { } { }
     assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000
     sync always
@@ -116548,7 +116408,7 @@ module \ls180
       update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0]
   end
   attribute \src "ls180.v:1501.11-1501.47"
-  process $proc$ls180.v:1501$3391
+  process $proc$ls180.v:1501$3379
     assign { } { }
     assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000
     sync always
@@ -116556,7 +116416,7 @@ module \ls180
       update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0]
   end
   attribute \src "ls180.v:1502.12-1502.58"
-  process $proc$ls180.v:1502$3392
+  process $proc$ls180.v:1502$3380
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000
     sync always
@@ -116564,7 +116424,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
   end
   attribute \src "ls180.v:1506.12-1506.54"
-  process $proc$ls180.v:1506$3393
+  process $proc$ls180.v:1506$3381
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000
     sync always
@@ -116572,7 +116432,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0]
   end
   attribute \src "ls180.v:1507.5-1507.46"
-  process $proc$ls180.v:1507$3394
+  process $proc$ls180.v:1507$3382
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
     sync always
@@ -116580,7 +116440,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0]
   end
   attribute \src "ls180.v:1509.12-1509.58"
-  process $proc$ls180.v:1509$3395
+  process $proc$ls180.v:1509$3383
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000
     sync always
@@ -116588,7 +116448,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
   end
   attribute \src "ls180.v:1513.12-1513.54"
-  process $proc$ls180.v:1513$3396
+  process $proc$ls180.v:1513$3384
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000
     sync always
@@ -116596,7 +116456,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0]
   end
   attribute \src "ls180.v:1514.5-1514.46"
-  process $proc$ls180.v:1514$3397
+  process $proc$ls180.v:1514$3385
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
     sync always
@@ -116604,7 +116464,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0]
   end
   attribute \src "ls180.v:1516.12-1516.58"
-  process $proc$ls180.v:1516$3398
+  process $proc$ls180.v:1516$3386
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000
     sync always
@@ -116612,7 +116472,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
   end
   attribute \src "ls180.v:1520.12-1520.54"
-  process $proc$ls180.v:1520$3399
+  process $proc$ls180.v:1520$3387
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000
     sync always
@@ -116620,7 +116480,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0]
   end
   attribute \src "ls180.v:1521.5-1521.46"
-  process $proc$ls180.v:1521$3400
+  process $proc$ls180.v:1521$3388
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
     sync always
@@ -116628,7 +116488,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0]
   end
   attribute \src "ls180.v:1523.12-1523.58"
-  process $proc$ls180.v:1523$3401
+  process $proc$ls180.v:1523$3389
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
     sync always
@@ -116636,7 +116496,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
   end
   attribute \src "ls180.v:1527.12-1527.54"
-  process $proc$ls180.v:1527$3402
+  process $proc$ls180.v:1527$3390
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000
     sync always
@@ -116644,7 +116504,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0]
   end
   attribute \src "ls180.v:1528.5-1528.46"
-  process $proc$ls180.v:1528$3403
+  process $proc$ls180.v:1528$3391
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
     sync always
@@ -116652,7 +116512,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0]
   end
   attribute \src "ls180.v:1530.12-1530.53"
-  process $proc$ls180.v:1530$3404
+  process $proc$ls180.v:1530$3392
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000
     sync always
@@ -116660,7 +116520,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0]
   end
   attribute \src "ls180.v:1531.12-1531.53"
-  process $proc$ls180.v:1531$3405
+  process $proc$ls180.v:1531$3393
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000
     sync always
@@ -116668,7 +116528,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0]
   end
   attribute \src "ls180.v:1532.12-1532.53"
-  process $proc$ls180.v:1532$3406
+  process $proc$ls180.v:1532$3394
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000
     sync always
@@ -116676,7 +116536,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0]
   end
   attribute \src "ls180.v:1533.12-1533.53"
-  process $proc$ls180.v:1533$3407
+  process $proc$ls180.v:1533$3395
     assign { } { }
     assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000
     sync always
@@ -116684,7 +116544,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0]
   end
   attribute \src "ls180.v:1534.5-1534.43"
-  process $proc$ls180.v:1534$3408
+  process $proc$ls180.v:1534$3396
     assign { } { }
     assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0
     sync always
@@ -116692,7 +116552,7 @@ module \ls180
       update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0]
   end
   attribute \src "ls180.v:1535.12-1535.51"
-  process $proc$ls180.v:1535$3409
+  process $proc$ls180.v:1535$3397
     assign { } { }
     assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000
     sync always
@@ -116700,7 +116560,7 @@ module \ls180
       update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0]
   end
   attribute \src "ls180.v:1536.12-1536.51"
-  process $proc$ls180.v:1536$3410
+  process $proc$ls180.v:1536$3398
     assign { } { }
     assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000
     sync always
@@ -116708,7 +116568,7 @@ module \ls180
       update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0]
   end
   attribute \src "ls180.v:1537.12-1537.51"
-  process $proc$ls180.v:1537$3411
+  process $proc$ls180.v:1537$3399
     assign { } { }
     assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000
     sync always
@@ -116716,23 +116576,15 @@ module \ls180
       update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0]
   end
   attribute \src "ls180.v:1538.12-1538.51"
-  process $proc$ls180.v:1538$3412
+  process $proc$ls180.v:1538$3400
     assign { } { }
     assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000
     sync always
     sync init
       update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0]
   end
-  attribute \src "ls180.v:154.11-154.24"
-  process $proc$ls180.v:154$2791
-    assign { } { }
-    assign $0\eint_1[2:0] 3'000
-    sync always
-      update \eint_1 $0\eint_1[2:0]
-    sync init
-  end
   attribute \src "ls180.v:1540.11-1540.39"
-  process $proc$ls180.v:1540$3413
+  process $proc$ls180.v:1540$3401
     assign { } { }
     assign $1\main_sdcore_cmd_count[2:0] 3'000
     sync always
@@ -116740,7 +116592,7 @@ module \ls180
       update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0]
   end
   attribute \src "ls180.v:1541.5-1541.32"
-  process $proc$ls180.v:1541$3414
+  process $proc$ls180.v:1541$3402
     assign { } { }
     assign $1\main_sdcore_cmd_done[0:0] 1'0
     sync always
@@ -116748,7 +116600,7 @@ module \ls180
       update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0]
   end
   attribute \src "ls180.v:1542.5-1542.33"
-  process $proc$ls180.v:1542$3415
+  process $proc$ls180.v:1542$3403
     assign { } { }
     assign $1\main_sdcore_cmd_error[0:0] 1'0
     sync always
@@ -116756,7 +116608,7 @@ module \ls180
       update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0]
   end
   attribute \src "ls180.v:1543.5-1543.35"
-  process $proc$ls180.v:1543$3416
+  process $proc$ls180.v:1543$3404
     assign { } { }
     assign $1\main_sdcore_cmd_timeout[0:0] 1'0
     sync always
@@ -116764,7 +116616,7 @@ module \ls180
       update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0]
   end
   attribute \src "ls180.v:1545.12-1545.42"
-  process $proc$ls180.v:1545$3417
+  process $proc$ls180.v:1545$3405
     assign { } { }
     assign $1\main_sdcore_data_count[31:0] 0
     sync always
@@ -116772,7 +116624,7 @@ module \ls180
       update \main_sdcore_data_count $1\main_sdcore_data_count[31:0]
   end
   attribute \src "ls180.v:1546.5-1546.33"
-  process $proc$ls180.v:1546$3418
+  process $proc$ls180.v:1546$3406
     assign { } { }
     assign $1\main_sdcore_data_done[0:0] 1'0
     sync always
@@ -116780,7 +116632,7 @@ module \ls180
       update \main_sdcore_data_done $1\main_sdcore_data_done[0:0]
   end
   attribute \src "ls180.v:1547.5-1547.34"
-  process $proc$ls180.v:1547$3419
+  process $proc$ls180.v:1547$3407
     assign { } { }
     assign $1\main_sdcore_data_error[0:0] 1'0
     sync always
@@ -116788,23 +116640,15 @@ module \ls180
       update \main_sdcore_data_error $1\main_sdcore_data_error[0:0]
   end
   attribute \src "ls180.v:1548.5-1548.36"
-  process $proc$ls180.v:1548$3420
+  process $proc$ls180.v:1548$3408
     assign { } { }
     assign $1\main_sdcore_data_timeout[0:0] 1'0
     sync always
     sync init
       update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0]
   end
-  attribute \src "ls180.v:155.12-155.74"
-  process $proc$ls180.v:155$2792
-    assign { } { }
-    assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000
-    sync always
-      update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
-    sync init
-  end
   attribute \src "ls180.v:1557.11-1557.41"
-  process $proc$ls180.v:1557$3421
+  process $proc$ls180.v:1557$3409
     assign { } { }
     assign $0\main_interface0_bus_cti[2:0] 3'000
     sync always
@@ -116812,7 +116656,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1558.11-1558.41"
-  process $proc$ls180.v:1558$3422
+  process $proc$ls180.v:1558$3410
     assign { } { }
     assign $0\main_interface0_bus_bte[1:0] 2'00
     sync always
@@ -116820,7 +116664,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1581.11-1581.45"
-  process $proc$ls180.v:1581$3423
+  process $proc$ls180.v:1581$3411
     assign { } { }
     assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000
     sync always
@@ -116828,7 +116672,7 @@ module \ls180
       update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0]
   end
   attribute \src "ls180.v:1582.5-1582.41"
-  process $proc$ls180.v:1582$3424
+  process $proc$ls180.v:1582$3412
     assign { } { }
     assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0
     sync always
@@ -116836,7 +116680,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1583.11-1583.47"
-  process $proc$ls180.v:1583$3425
+  process $proc$ls180.v:1583$3413
     assign { } { }
     assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000
     sync always
@@ -116844,7 +116688,7 @@ module \ls180
       update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0]
   end
   attribute \src "ls180.v:1584.11-1584.47"
-  process $proc$ls180.v:1584$3426
+  process $proc$ls180.v:1584$3414
     assign { } { }
     assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000
     sync always
@@ -116852,15 +116696,23 @@ module \ls180
       update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0]
   end
   attribute \src "ls180.v:1585.11-1585.50"
-  process $proc$ls180.v:1585$3427
+  process $proc$ls180.v:1585$3415
     assign { } { }
     assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000
     sync always
     sync init
       update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0]
   end
+  attribute \src "ls180.v:159.12-159.74"
+  process $proc$ls180.v:159$2781
+    assign { } { }
+    assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000
+    sync always
+      update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
+    sync init
+  end
   attribute \src "ls180.v:1605.5-1605.51"
-  process $proc$ls180.v:1605$3428
+  process $proc$ls180.v:1605$3416
     assign { } { }
     assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0
     sync always
@@ -116868,7 +116720,7 @@ module \ls180
       update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0]
   end
   attribute \src "ls180.v:1606.5-1606.50"
-  process $proc$ls180.v:1606$3429
+  process $proc$ls180.v:1606$3417
     assign { } { }
     assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0
     sync always
@@ -116876,7 +116728,7 @@ module \ls180
       update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0]
   end
   attribute \src "ls180.v:1607.12-1607.66"
-  process $proc$ls180.v:1607$3430
+  process $proc$ls180.v:1607$3418
     assign { } { }
     assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0
     sync always
@@ -116884,7 +116736,7 @@ module \ls180
       update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0]
   end
   attribute \src "ls180.v:1608.11-1608.77"
-  process $proc$ls180.v:1608$3431
+  process $proc$ls180.v:1608$3419
     assign { } { }
     assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000
     sync always
@@ -116892,23 +116744,15 @@ module \ls180
       update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
   end
   attribute \src "ls180.v:1609.11-1609.50"
-  process $proc$ls180.v:1609$3432
+  process $proc$ls180.v:1609$3420
     assign { } { }
     assign $1\main_sdblock2mem_converter_demux[1:0] 2'00
     sync always
     sync init
       update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0]
   end
-  attribute \src "ls180.v:161.5-161.74"
-  process $proc$ls180.v:161$2793
-    assign { } { }
-    assign $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] 1'0
-    sync always
-      update \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
-    sync init
-  end
   attribute \src "ls180.v:1611.5-1611.49"
-  process $proc$ls180.v:1611$3433
+  process $proc$ls180.v:1611$3421
     assign { } { }
     assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0
     sync always
@@ -116916,7 +116760,7 @@ module \ls180
       update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0]
   end
   attribute \src "ls180.v:1617.5-1617.45"
-  process $proc$ls180.v:1617$3434
+  process $proc$ls180.v:1617$3422
     assign { } { }
     assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
     sync always
@@ -116924,7 +116768,7 @@ module \ls180
       update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0]
   end
   attribute \src "ls180.v:1619.12-1619.62"
-  process $proc$ls180.v:1619$3435
+  process $proc$ls180.v:1619$3423
     assign { } { }
     assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0
     sync always
@@ -116932,7 +116776,7 @@ module \ls180
       update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0]
   end
   attribute \src "ls180.v:162.12-162.71"
-  process $proc$ls180.v:162$2794
+  process $proc$ls180.v:162$2782
     assign { } { }
     assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
     sync always
@@ -116940,7 +116784,7 @@ module \ls180
       update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0]
   end
   attribute \src "ls180.v:1620.12-1620.60"
-  process $proc$ls180.v:1620$3436
+  process $proc$ls180.v:1620$3424
     assign { } { }
     assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0
     sync always
@@ -116948,7 +116792,7 @@ module \ls180
       update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0]
   end
   attribute \src "ls180.v:1622.5-1622.57"
-  process $proc$ls180.v:1622$3437
+  process $proc$ls180.v:1622$3425
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0
     sync always
@@ -116956,7 +116800,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
   end
   attribute \src "ls180.v:1626.12-1626.67"
-  process $proc$ls180.v:1626$3438
+  process $proc$ls180.v:1626$3426
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
@@ -116964,7 +116808,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
   end
   attribute \src "ls180.v:1627.5-1627.54"
-  process $proc$ls180.v:1627$3439
+  process $proc$ls180.v:1627$3427
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0
     sync always
@@ -116972,7 +116816,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
   end
   attribute \src "ls180.v:1628.12-1628.69"
-  process $proc$ls180.v:1628$3440
+  process $proc$ls180.v:1628$3428
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0
     sync always
@@ -116980,7 +116824,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
   end
   attribute \src "ls180.v:1629.5-1629.56"
-  process $proc$ls180.v:1629$3441
+  process $proc$ls180.v:1629$3429
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0
     sync always
@@ -116988,7 +116832,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
   end
   attribute \src "ls180.v:163.12-163.73"
-  process $proc$ls180.v:163$2795
+  process $proc$ls180.v:163$2783
     assign { } { }
     assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0
     sync always
@@ -116996,7 +116840,7 @@ module \ls180
       update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0]
   end
   attribute \src "ls180.v:1630.5-1630.61"
-  process $proc$ls180.v:1630$3442
+  process $proc$ls180.v:1630$3430
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0
     sync always
@@ -117004,7 +116848,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
   end
   attribute \src "ls180.v:1631.5-1631.56"
-  process $proc$ls180.v:1631$3443
+  process $proc$ls180.v:1631$3431
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0
     sync always
@@ -117012,7 +116856,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
   end
   attribute \src "ls180.v:1632.5-1632.53"
-  process $proc$ls180.v:1632$3444
+  process $proc$ls180.v:1632$3432
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
     sync always
@@ -117020,7 +116864,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0]
   end
   attribute \src "ls180.v:1634.5-1634.59"
-  process $proc$ls180.v:1634$3445
+  process $proc$ls180.v:1634$3433
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0
     sync always
@@ -117028,7 +116872,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
   end
   attribute \src "ls180.v:1635.5-1635.54"
-  process $proc$ls180.v:1635$3446
+  process $proc$ls180.v:1635$3434
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0
     sync always
@@ -117036,7 +116880,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
   end
   attribute \src "ls180.v:1637.12-1637.61"
-  process $proc$ls180.v:1637$3447
+  process $proc$ls180.v:1637$3435
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0
     sync always
@@ -117044,7 +116888,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0]
   end
   attribute \src "ls180.v:1640.12-1640.43"
-  process $proc$ls180.v:1640$3448
+  process $proc$ls180.v:1640$3436
     assign { } { }
     assign $1\main_interface1_bus_adr[31:0] 0
     sync always
@@ -117052,7 +116896,7 @@ module \ls180
       update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0]
   end
   attribute \src "ls180.v:1641.12-1641.45"
-  process $proc$ls180.v:1641$3449
+  process $proc$ls180.v:1641$3437
     assign { } { }
     assign $0\main_interface1_bus_dat_w[31:0] 0
     sync always
@@ -117060,7 +116904,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1643.11-1643.41"
-  process $proc$ls180.v:1643$3450
+  process $proc$ls180.v:1643$3438
     assign { } { }
     assign $1\main_interface1_bus_sel[3:0] 4'0000
     sync always
@@ -117068,7 +116912,7 @@ module \ls180
       update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0]
   end
   attribute \src "ls180.v:1644.5-1644.35"
-  process $proc$ls180.v:1644$3451
+  process $proc$ls180.v:1644$3439
     assign { } { }
     assign $1\main_interface1_bus_cyc[0:0] 1'0
     sync always
@@ -117076,7 +116920,7 @@ module \ls180
       update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0]
   end
   attribute \src "ls180.v:1645.5-1645.35"
-  process $proc$ls180.v:1645$3452
+  process $proc$ls180.v:1645$3440
     assign { } { }
     assign $1\main_interface1_bus_stb[0:0] 1'0
     sync always
@@ -117084,7 +116928,7 @@ module \ls180
       update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0]
   end
   attribute \src "ls180.v:1647.5-1647.34"
-  process $proc$ls180.v:1647$3453
+  process $proc$ls180.v:1647$3441
     assign { } { }
     assign $1\main_interface1_bus_we[0:0] 1'0
     sync always
@@ -117092,7 +116936,7 @@ module \ls180
       update \main_interface1_bus_we $1\main_interface1_bus_we[0:0]
   end
   attribute \src "ls180.v:1648.11-1648.41"
-  process $proc$ls180.v:1648$3454
+  process $proc$ls180.v:1648$3442
     assign { } { }
     assign $0\main_interface1_bus_cti[2:0] 3'000
     sync always
@@ -117100,7 +116944,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1649.11-1649.41"
-  process $proc$ls180.v:1649$3455
+  process $proc$ls180.v:1649$3443
     assign { } { }
     assign $0\main_interface1_bus_bte[1:0] 2'00
     sync always
@@ -117108,7 +116952,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:165.11-165.69"
-  process $proc$ls180.v:165$2796
+  process $proc$ls180.v:165$2784
     assign { } { }
     assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
     sync always
@@ -117116,7 +116960,7 @@ module \ls180
       update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0]
   end
   attribute \src "ls180.v:1656.5-1656.43"
-  process $proc$ls180.v:1656$3456
+  process $proc$ls180.v:1656$3444
     assign { } { }
     assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0
     sync always
@@ -117124,7 +116968,7 @@ module \ls180
       update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0]
   end
   attribute \src "ls180.v:1657.5-1657.43"
-  process $proc$ls180.v:1657$3457
+  process $proc$ls180.v:1657$3445
     assign { } { }
     assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0
     sync always
@@ -117132,7 +116976,7 @@ module \ls180
       update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0]
   end
   attribute \src "ls180.v:1658.5-1658.42"
-  process $proc$ls180.v:1658$3458
+  process $proc$ls180.v:1658$3446
     assign { } { }
     assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0
     sync always
@@ -117140,7 +116984,7 @@ module \ls180
       update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0]
   end
   attribute \src "ls180.v:1659.12-1659.61"
-  process $proc$ls180.v:1659$3459
+  process $proc$ls180.v:1659$3447
     assign { } { }
     assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0
     sync always
@@ -117148,7 +116992,7 @@ module \ls180
       update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0]
   end
   attribute \src "ls180.v:166.5-166.63"
-  process $proc$ls180.v:166$2797
+  process $proc$ls180.v:166$2785
     assign { } { }
     assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
     sync always
@@ -117156,7 +117000,7 @@ module \ls180
       update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0]
   end
   attribute \src "ls180.v:1660.5-1660.45"
-  process $proc$ls180.v:1660$3460
+  process $proc$ls180.v:1660$3448
     assign { } { }
     assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0
     sync always
@@ -117164,7 +117008,7 @@ module \ls180
       update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0]
   end
   attribute \src "ls180.v:1662.5-1662.45"
-  process $proc$ls180.v:1662$3461
+  process $proc$ls180.v:1662$3449
     assign { } { }
     assign $0\main_sdmem2block_dma_source_first[0:0] 1'0
     sync always
@@ -117172,7 +117016,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1663.5-1663.44"
-  process $proc$ls180.v:1663$3462
+  process $proc$ls180.v:1663$3450
     assign { } { }
     assign $1\main_sdmem2block_dma_source_last[0:0] 1'0
     sync always
@@ -117180,7 +117024,7 @@ module \ls180
       update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0]
   end
   attribute \src "ls180.v:1664.12-1664.60"
-  process $proc$ls180.v:1664$3463
+  process $proc$ls180.v:1664$3451
     assign { } { }
     assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0
     sync always
@@ -117188,7 +117032,7 @@ module \ls180
       update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0]
   end
   attribute \src "ls180.v:1665.12-1665.45"
-  process $proc$ls180.v:1665$3464
+  process $proc$ls180.v:1665$3452
     assign { } { }
     assign $1\main_sdmem2block_dma_data[31:0] 0
     sync always
@@ -117196,7 +117040,7 @@ module \ls180
       update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0]
   end
   attribute \src "ls180.v:1666.12-1666.53"
-  process $proc$ls180.v:1666$3465
+  process $proc$ls180.v:1666$3453
     assign { } { }
     assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
@@ -117204,7 +117048,7 @@ module \ls180
       update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0]
   end
   attribute \src "ls180.v:1667.5-1667.40"
-  process $proc$ls180.v:1667$3466
+  process $proc$ls180.v:1667$3454
     assign { } { }
     assign $1\main_sdmem2block_dma_base_re[0:0] 1'0
     sync always
@@ -117212,7 +117056,7 @@ module \ls180
       update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0]
   end
   attribute \src "ls180.v:1668.12-1668.55"
-  process $proc$ls180.v:1668$3467
+  process $proc$ls180.v:1668$3455
     assign { } { }
     assign $1\main_sdmem2block_dma_length_storage[31:0] 0
     sync always
@@ -117220,7 +117064,7 @@ module \ls180
       update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0]
   end
   attribute \src "ls180.v:1669.5-1669.42"
-  process $proc$ls180.v:1669$3468
+  process $proc$ls180.v:1669$3456
     assign { } { }
     assign $1\main_sdmem2block_dma_length_re[0:0] 1'0
     sync always
@@ -117228,7 +117072,7 @@ module \ls180
       update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0]
   end
   attribute \src "ls180.v:167.5-167.63"
-  process $proc$ls180.v:167$2798
+  process $proc$ls180.v:167$2786
     assign { } { }
     assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
     sync always
@@ -117236,7 +117080,7 @@ module \ls180
       update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0]
   end
   attribute \src "ls180.v:1670.5-1670.47"
-  process $proc$ls180.v:1670$3469
+  process $proc$ls180.v:1670$3457
     assign { } { }
     assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0
     sync always
@@ -117244,7 +117088,7 @@ module \ls180
       update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0]
   end
   attribute \src "ls180.v:1671.5-1671.42"
-  process $proc$ls180.v:1671$3470
+  process $proc$ls180.v:1671$3458
     assign { } { }
     assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0
     sync always
@@ -117252,7 +117096,7 @@ module \ls180
       update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0]
   end
   attribute \src "ls180.v:1672.5-1672.44"
-  process $proc$ls180.v:1672$3471
+  process $proc$ls180.v:1672$3459
     assign { } { }
     assign $1\main_sdmem2block_dma_done_status[0:0] 1'0
     sync always
@@ -117260,7 +117104,7 @@ module \ls180
       update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0]
   end
   attribute \src "ls180.v:1674.5-1674.45"
-  process $proc$ls180.v:1674$3472
+  process $proc$ls180.v:1674$3460
     assign { } { }
     assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0
     sync always
@@ -117268,7 +117112,7 @@ module \ls180
       update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0]
   end
   attribute \src "ls180.v:1675.5-1675.40"
-  process $proc$ls180.v:1675$3473
+  process $proc$ls180.v:1675$3461
     assign { } { }
     assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0
     sync always
@@ -117276,7 +117120,7 @@ module \ls180
       update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0]
   end
   attribute \src "ls180.v:1679.12-1679.47"
-  process $proc$ls180.v:1679$3474
+  process $proc$ls180.v:1679$3462
     assign { } { }
     assign $1\main_sdmem2block_dma_offset[31:0] 0
     sync always
@@ -117284,7 +117128,7 @@ module \ls180
       update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0]
   end
   attribute \src "ls180.v:169.5-169.62"
-  process $proc$ls180.v:169$2799
+  process $proc$ls180.v:169$2787
     assign { } { }
     assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
     sync always
@@ -117292,7 +117136,7 @@ module \ls180
       update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0]
   end
   attribute \src "ls180.v:1691.11-1691.64"
-  process $proc$ls180.v:1691$3475
+  process $proc$ls180.v:1691$3463
     assign { } { }
     assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000
     sync always
@@ -117300,7 +117144,7 @@ module \ls180
       update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0]
   end
   attribute \src "ls180.v:1693.11-1693.48"
-  process $proc$ls180.v:1693$3476
+  process $proc$ls180.v:1693$3464
     assign { } { }
     assign $1\main_sdmem2block_converter_mux[1:0] 2'00
     sync always
@@ -117308,7 +117152,7 @@ module \ls180
       update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0]
   end
   attribute \src "ls180.v:170.11-170.69"
-  process $proc$ls180.v:170$2800
+  process $proc$ls180.v:170$2788
     assign { } { }
     assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000
     sync always
@@ -117316,7 +117160,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:171.11-171.69"
-  process $proc$ls180.v:171$2801
+  process $proc$ls180.v:171$2789
     assign { } { }
     assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00
     sync always
@@ -117324,7 +117168,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1717.11-1717.45"
-  process $proc$ls180.v:1717$3477
+  process $proc$ls180.v:1717$3465
     assign { } { }
     assign $1\main_sdmem2block_fifo_level[5:0] 6'000000
     sync always
@@ -117332,7 +117176,7 @@ module \ls180
       update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0]
   end
   attribute \src "ls180.v:1718.5-1718.41"
-  process $proc$ls180.v:1718$3478
+  process $proc$ls180.v:1718$3466
     assign { } { }
     assign $0\main_sdmem2block_fifo_replace[0:0] 1'0
     sync always
@@ -117340,7 +117184,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1719.11-1719.47"
-  process $proc$ls180.v:1719$3479
+  process $proc$ls180.v:1719$3467
     assign { } { }
     assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000
     sync always
@@ -117348,7 +117192,7 @@ module \ls180
       update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0]
   end
   attribute \src "ls180.v:1720.11-1720.47"
-  process $proc$ls180.v:1720$3480
+  process $proc$ls180.v:1720$3468
     assign { } { }
     assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000
     sync always
@@ -117356,7 +117200,7 @@ module \ls180
       update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0]
   end
   attribute \src "ls180.v:1721.11-1721.50"
-  process $proc$ls180.v:1721$3481
+  process $proc$ls180.v:1721$3469
     assign { } { }
     assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000
     sync always
@@ -117364,7 +117208,7 @@ module \ls180
       update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0]
   end
   attribute \src "ls180.v:173.5-173.44"
-  process $proc$ls180.v:173$2802
+  process $proc$ls180.v:173$2790
     assign { } { }
     assign $1\main_libresocsim_converter0_skip[0:0] 1'0
     sync always
@@ -117372,7 +117216,7 @@ module \ls180
       update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0]
   end
   attribute \src "ls180.v:1734.5-1734.36"
-  process $proc$ls180.v:1734$3482
+  process $proc$ls180.v:1734$3470
     assign { } { }
     assign $1\builder_converter0_state[0:0] 1'0
     sync always
@@ -117380,7 +117224,7 @@ module \ls180
       update \builder_converter0_state $1\builder_converter0_state[0:0]
   end
   attribute \src "ls180.v:1735.5-1735.41"
-  process $proc$ls180.v:1735$3483
+  process $proc$ls180.v:1735$3471
     assign { } { }
     assign $1\builder_converter0_next_state[0:0] 1'0
     sync always
@@ -117388,7 +117232,7 @@ module \ls180
       update \builder_converter0_next_state $1\builder_converter0_next_state[0:0]
   end
   attribute \src "ls180.v:1736.5-1736.69"
-  process $proc$ls180.v:1736$3484
+  process $proc$ls180.v:1736$3472
     assign { } { }
     assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
     sync always
@@ -117396,7 +117240,7 @@ module \ls180
       update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0]
   end
   attribute \src "ls180.v:1737.5-1737.72"
-  process $proc$ls180.v:1737$3485
+  process $proc$ls180.v:1737$3473
     assign { } { }
     assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0
     sync always
@@ -117404,7 +117248,7 @@ module \ls180
       update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
   end
   attribute \src "ls180.v:1738.5-1738.36"
-  process $proc$ls180.v:1738$3486
+  process $proc$ls180.v:1738$3474
     assign { } { }
     assign $1\builder_converter1_state[0:0] 1'0
     sync always
@@ -117412,7 +117256,7 @@ module \ls180
       update \builder_converter1_state $1\builder_converter1_state[0:0]
   end
   attribute \src "ls180.v:1739.5-1739.41"
-  process $proc$ls180.v:1739$3487
+  process $proc$ls180.v:1739$3475
     assign { } { }
     assign $1\builder_converter1_next_state[0:0] 1'0
     sync always
@@ -117420,7 +117264,7 @@ module \ls180
       update \builder_converter1_next_state $1\builder_converter1_next_state[0:0]
   end
   attribute \src "ls180.v:174.5-174.47"
-  process $proc$ls180.v:174$2803
+  process $proc$ls180.v:174$2791
     assign { } { }
     assign $1\main_libresocsim_converter0_counter[0:0] 1'0
     sync always
@@ -117428,7 +117272,7 @@ module \ls180
       update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0]
   end
   attribute \src "ls180.v:1740.5-1740.69"
-  process $proc$ls180.v:1740$3488
+  process $proc$ls180.v:1740$3476
     assign { } { }
     assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
     sync always
@@ -117436,7 +117280,7 @@ module \ls180
       update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0]
   end
   attribute \src "ls180.v:1741.5-1741.72"
-  process $proc$ls180.v:1741$3489
+  process $proc$ls180.v:1741$3477
     assign { } { }
     assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0
     sync always
@@ -117444,7 +117288,7 @@ module \ls180
       update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
   end
   attribute \src "ls180.v:1742.5-1742.36"
-  process $proc$ls180.v:1742$3490
+  process $proc$ls180.v:1742$3478
     assign { } { }
     assign $1\builder_converter2_state[0:0] 1'0
     sync always
@@ -117452,7 +117296,7 @@ module \ls180
       update \builder_converter2_state $1\builder_converter2_state[0:0]
   end
   attribute \src "ls180.v:1743.5-1743.41"
-  process $proc$ls180.v:1743$3491
+  process $proc$ls180.v:1743$3479
     assign { } { }
     assign $1\builder_converter2_next_state[0:0] 1'0
     sync always
@@ -117460,7 +117304,7 @@ module \ls180
       update \builder_converter2_next_state $1\builder_converter2_next_state[0:0]
   end
   attribute \src "ls180.v:1744.5-1744.69"
-  process $proc$ls180.v:1744$3492
+  process $proc$ls180.v:1744$3480
     assign { } { }
     assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
     sync always
@@ -117468,7 +117312,7 @@ module \ls180
       update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0]
   end
   attribute \src "ls180.v:1745.5-1745.72"
-  process $proc$ls180.v:1745$3493
+  process $proc$ls180.v:1745$3481
     assign { } { }
     assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0
     sync always
@@ -117476,7 +117320,7 @@ module \ls180
       update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
   end
   attribute \src "ls180.v:1746.11-1746.41"
-  process $proc$ls180.v:1746$3494
+  process $proc$ls180.v:1746$3482
     assign { } { }
     assign $1\builder_refresher_state[1:0] 2'00
     sync always
@@ -117484,7 +117328,7 @@ module \ls180
       update \builder_refresher_state $1\builder_refresher_state[1:0]
   end
   attribute \src "ls180.v:1747.11-1747.46"
-  process $proc$ls180.v:1747$3495
+  process $proc$ls180.v:1747$3483
     assign { } { }
     assign $1\builder_refresher_next_state[1:0] 2'00
     sync always
@@ -117492,7 +117336,7 @@ module \ls180
       update \builder_refresher_next_state $1\builder_refresher_next_state[1:0]
   end
   attribute \src "ls180.v:1748.11-1748.44"
-  process $proc$ls180.v:1748$3496
+  process $proc$ls180.v:1748$3484
     assign { } { }
     assign $1\builder_bankmachine0_state[2:0] 3'000
     sync always
@@ -117500,7 +117344,7 @@ module \ls180
       update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0]
   end
   attribute \src "ls180.v:1749.11-1749.49"
-  process $proc$ls180.v:1749$3497
+  process $proc$ls180.v:1749$3485
     assign { } { }
     assign $1\builder_bankmachine0_next_state[2:0] 3'000
     sync always
@@ -117508,7 +117352,7 @@ module \ls180
       update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0]
   end
   attribute \src "ls180.v:1750.11-1750.44"
-  process $proc$ls180.v:1750$3498
+  process $proc$ls180.v:1750$3486
     assign { } { }
     assign $1\builder_bankmachine1_state[2:0] 3'000
     sync always
@@ -117516,7 +117360,7 @@ module \ls180
       update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0]
   end
   attribute \src "ls180.v:1751.11-1751.49"
-  process $proc$ls180.v:1751$3499
+  process $proc$ls180.v:1751$3487
     assign { } { }
     assign $1\builder_bankmachine1_next_state[2:0] 3'000
     sync always
@@ -117524,7 +117368,7 @@ module \ls180
       update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0]
   end
   attribute \src "ls180.v:1752.11-1752.44"
-  process $proc$ls180.v:1752$3500
+  process $proc$ls180.v:1752$3488
     assign { } { }
     assign $1\builder_bankmachine2_state[2:0] 3'000
     sync always
@@ -117532,7 +117376,7 @@ module \ls180
       update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0]
   end
   attribute \src "ls180.v:1753.11-1753.49"
-  process $proc$ls180.v:1753$3501
+  process $proc$ls180.v:1753$3489
     assign { } { }
     assign $1\builder_bankmachine2_next_state[2:0] 3'000
     sync always
@@ -117540,7 +117384,7 @@ module \ls180
       update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0]
   end
   attribute \src "ls180.v:1754.11-1754.44"
-  process $proc$ls180.v:1754$3502
+  process $proc$ls180.v:1754$3490
     assign { } { }
     assign $1\builder_bankmachine3_state[2:0] 3'000
     sync always
@@ -117548,7 +117392,7 @@ module \ls180
       update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0]
   end
   attribute \src "ls180.v:1755.11-1755.49"
-  process $proc$ls180.v:1755$3503
+  process $proc$ls180.v:1755$3491
     assign { } { }
     assign $1\builder_bankmachine3_next_state[2:0] 3'000
     sync always
@@ -117556,7 +117400,7 @@ module \ls180
       update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0]
   end
   attribute \src "ls180.v:1756.11-1756.43"
-  process $proc$ls180.v:1756$3504
+  process $proc$ls180.v:1756$3492
     assign { } { }
     assign $1\builder_multiplexer_state[2:0] 3'000
     sync always
@@ -117564,7 +117408,7 @@ module \ls180
       update \builder_multiplexer_state $1\builder_multiplexer_state[2:0]
   end
   attribute \src "ls180.v:1757.11-1757.48"
-  process $proc$ls180.v:1757$3505
+  process $proc$ls180.v:1757$3493
     assign { } { }
     assign $1\builder_multiplexer_next_state[2:0] 3'000
     sync always
@@ -117572,7 +117416,7 @@ module \ls180
       update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0]
   end
   attribute \src "ls180.v:176.12-176.53"
-  process $proc$ls180.v:176$2804
+  process $proc$ls180.v:176$2792
     assign { } { }
     assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
@@ -117580,7 +117424,7 @@ module \ls180
       update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0]
   end
   attribute \src "ls180.v:177.12-177.71"
-  process $proc$ls180.v:177$2805
+  process $proc$ls180.v:177$2793
     assign { } { }
     assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
     sync always
@@ -117588,7 +117432,7 @@ module \ls180
       update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0]
   end
   attribute \src "ls180.v:1770.5-1770.27"
-  process $proc$ls180.v:1770$3506
+  process $proc$ls180.v:1770$3494
     assign { } { }
     assign $0\builder_locked0[0:0] 1'0
     sync always
@@ -117596,7 +117440,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1771.5-1771.27"
-  process $proc$ls180.v:1771$3507
+  process $proc$ls180.v:1771$3495
     assign { } { }
     assign $0\builder_locked1[0:0] 1'0
     sync always
@@ -117604,7 +117448,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1772.5-1772.27"
-  process $proc$ls180.v:1772$3508
+  process $proc$ls180.v:1772$3496
     assign { } { }
     assign $0\builder_locked2[0:0] 1'0
     sync always
@@ -117612,7 +117456,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1773.5-1773.27"
-  process $proc$ls180.v:1773$3509
+  process $proc$ls180.v:1773$3497
     assign { } { }
     assign $0\builder_locked3[0:0] 1'0
     sync always
@@ -117620,7 +117464,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1774.5-1774.42"
-  process $proc$ls180.v:1774$3510
+  process $proc$ls180.v:1774$3498
     assign { } { }
     assign $1\builder_new_master_wdata_ready[0:0] 1'0
     sync always
@@ -117628,7 +117472,7 @@ module \ls180
       update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0]
   end
   attribute \src "ls180.v:1775.5-1775.43"
-  process $proc$ls180.v:1775$3511
+  process $proc$ls180.v:1775$3499
     assign { } { }
     assign $1\builder_new_master_rdata_valid0[0:0] 1'0
     sync always
@@ -117636,7 +117480,7 @@ module \ls180
       update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0]
   end
   attribute \src "ls180.v:1776.5-1776.43"
-  process $proc$ls180.v:1776$3512
+  process $proc$ls180.v:1776$3500
     assign { } { }
     assign $1\builder_new_master_rdata_valid1[0:0] 1'0
     sync always
@@ -117644,7 +117488,7 @@ module \ls180
       update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0]
   end
   attribute \src "ls180.v:1777.5-1777.43"
-  process $proc$ls180.v:1777$3513
+  process $proc$ls180.v:1777$3501
     assign { } { }
     assign $1\builder_new_master_rdata_valid2[0:0] 1'0
     sync always
@@ -117652,7 +117496,7 @@ module \ls180
       update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0]
   end
   attribute \src "ls180.v:1778.5-1778.43"
-  process $proc$ls180.v:1778$3514
+  process $proc$ls180.v:1778$3502
     assign { } { }
     assign $1\builder_new_master_rdata_valid3[0:0] 1'0
     sync always
@@ -117660,7 +117504,7 @@ module \ls180
       update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0]
   end
   attribute \src "ls180.v:1779.5-1779.35"
-  process $proc$ls180.v:1779$3515
+  process $proc$ls180.v:1779$3503
     assign { } { }
     assign $1\builder_converter_state[0:0] 1'0
     sync always
@@ -117668,7 +117512,7 @@ module \ls180
       update \builder_converter_state $1\builder_converter_state[0:0]
   end
   attribute \src "ls180.v:178.12-178.73"
-  process $proc$ls180.v:178$2806
+  process $proc$ls180.v:178$2794
     assign { } { }
     assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0
     sync always
@@ -117676,7 +117520,7 @@ module \ls180
       update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0]
   end
   attribute \src "ls180.v:1780.5-1780.40"
-  process $proc$ls180.v:1780$3516
+  process $proc$ls180.v:1780$3504
     assign { } { }
     assign $1\builder_converter_next_state[0:0] 1'0
     sync always
@@ -117684,7 +117528,7 @@ module \ls180
       update \builder_converter_next_state $1\builder_converter_next_state[0:0]
   end
   attribute \src "ls180.v:1781.5-1781.55"
-  process $proc$ls180.v:1781$3517
+  process $proc$ls180.v:1781$3505
     assign { } { }
     assign $1\main_converter_counter_converter_next_value[0:0] 1'0
     sync always
@@ -117692,7 +117536,7 @@ module \ls180
       update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0]
   end
   attribute \src "ls180.v:1782.5-1782.58"
-  process $proc$ls180.v:1782$3518
+  process $proc$ls180.v:1782$3506
     assign { } { }
     assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0
     sync always
@@ -117700,7 +117544,7 @@ module \ls180
       update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0]
   end
   attribute \src "ls180.v:1783.11-1783.42"
-  process $proc$ls180.v:1783$3519
+  process $proc$ls180.v:1783$3507
     assign { } { }
     assign $1\builder_spimaster0_state[1:0] 2'00
     sync always
@@ -117708,7 +117552,7 @@ module \ls180
       update \builder_spimaster0_state $1\builder_spimaster0_state[1:0]
   end
   attribute \src "ls180.v:1784.11-1784.47"
-  process $proc$ls180.v:1784$3520
+  process $proc$ls180.v:1784$3508
     assign { } { }
     assign $1\builder_spimaster0_next_state[1:0] 2'00
     sync always
@@ -117716,7 +117560,7 @@ module \ls180
       update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0]
   end
   attribute \src "ls180.v:1785.11-1785.62"
-  process $proc$ls180.v:1785$3521
+  process $proc$ls180.v:1785$3509
     assign { } { }
     assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
     sync always
@@ -117724,7 +117568,7 @@ module \ls180
       update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0]
   end
   attribute \src "ls180.v:1786.5-1786.59"
-  process $proc$ls180.v:1786$3522
+  process $proc$ls180.v:1786$3510
     assign { } { }
     assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0
     sync always
@@ -117732,7 +117576,7 @@ module \ls180
       update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0]
   end
   attribute \src "ls180.v:1787.11-1787.42"
-  process $proc$ls180.v:1787$3523
+  process $proc$ls180.v:1787$3511
     assign { } { }
     assign $1\builder_spimaster1_state[1:0] 2'00
     sync always
@@ -117740,7 +117584,7 @@ module \ls180
       update \builder_spimaster1_state $1\builder_spimaster1_state[1:0]
   end
   attribute \src "ls180.v:1788.11-1788.47"
-  process $proc$ls180.v:1788$3524
+  process $proc$ls180.v:1788$3512
     assign { } { }
     assign $1\builder_spimaster1_next_state[1:0] 2'00
     sync always
@@ -117748,7 +117592,7 @@ module \ls180
       update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0]
   end
   attribute \src "ls180.v:1789.11-1789.60"
-  process $proc$ls180.v:1789$3525
+  process $proc$ls180.v:1789$3513
     assign { } { }
     assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
     sync always
@@ -117756,7 +117600,7 @@ module \ls180
       update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0]
   end
   attribute \src "ls180.v:1790.5-1790.57"
-  process $proc$ls180.v:1790$3526
+  process $proc$ls180.v:1790$3514
     assign { } { }
     assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0
     sync always
@@ -117764,7 +117608,7 @@ module \ls180
       update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0]
   end
   attribute \src "ls180.v:1791.5-1791.41"
-  process $proc$ls180.v:1791$3527
+  process $proc$ls180.v:1791$3515
     assign { } { }
     assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0
     sync always
@@ -117772,7 +117616,7 @@ module \ls180
       update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0]
   end
   attribute \src "ls180.v:1792.5-1792.46"
-  process $proc$ls180.v:1792$3528
+  process $proc$ls180.v:1792$3516
     assign { } { }
     assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0
     sync always
@@ -117780,7 +117624,7 @@ module \ls180
       update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0]
   end
   attribute \src "ls180.v:1793.11-1793.66"
-  process $proc$ls180.v:1793$3529
+  process $proc$ls180.v:1793$3517
     assign { } { }
     assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
     sync always
@@ -117788,7 +117632,7 @@ module \ls180
       update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
   end
   attribute \src "ls180.v:1794.5-1794.63"
-  process $proc$ls180.v:1794$3530
+  process $proc$ls180.v:1794$3518
     assign { } { }
     assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0
     sync always
@@ -117796,7 +117640,7 @@ module \ls180
       update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
   end
   attribute \src "ls180.v:1795.11-1795.47"
-  process $proc$ls180.v:1795$3531
+  process $proc$ls180.v:1795$3519
     assign { } { }
     assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00
     sync always
@@ -117804,7 +117648,7 @@ module \ls180
       update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0]
   end
   attribute \src "ls180.v:1796.11-1796.52"
-  process $proc$ls180.v:1796$3532
+  process $proc$ls180.v:1796$3520
     assign { } { }
     assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
     sync always
@@ -117812,7 +117656,7 @@ module \ls180
       update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0]
   end
   attribute \src "ls180.v:1797.11-1797.66"
-  process $proc$ls180.v:1797$3533
+  process $proc$ls180.v:1797$3521
     assign { } { }
     assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
     sync always
@@ -117820,7 +117664,7 @@ module \ls180
       update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
   end
   attribute \src "ls180.v:1798.5-1798.63"
-  process $proc$ls180.v:1798$3534
+  process $proc$ls180.v:1798$3522
     assign { } { }
     assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
     sync always
@@ -117828,7 +117672,7 @@ module \ls180
       update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
   end
   attribute \src "ls180.v:1799.11-1799.47"
-  process $proc$ls180.v:1799$3535
+  process $proc$ls180.v:1799$3523
     assign { } { }
     assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000
     sync always
@@ -117836,7 +117680,7 @@ module \ls180
       update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0]
   end
   attribute \src "ls180.v:180.11-180.69"
-  process $proc$ls180.v:180$2807
+  process $proc$ls180.v:180$2795
     assign { } { }
     assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000
     sync always
@@ -117844,7 +117688,7 @@ module \ls180
       update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0]
   end
   attribute \src "ls180.v:1800.11-1800.52"
-  process $proc$ls180.v:1800$3536
+  process $proc$ls180.v:1800$3524
     assign { } { }
     assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
     sync always
@@ -117852,7 +117696,7 @@ module \ls180
       update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0]
   end
   attribute \src "ls180.v:1801.11-1801.67"
-  process $proc$ls180.v:1801$3537
+  process $proc$ls180.v:1801$3525
     assign { } { }
     assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
     sync always
@@ -117860,7 +117704,7 @@ module \ls180
       update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
   end
   attribute \src "ls180.v:1802.5-1802.64"
-  process $proc$ls180.v:1802$3538
+  process $proc$ls180.v:1802$3526
     assign { } { }
     assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0
     sync always
@@ -117868,7 +117712,7 @@ module \ls180
       update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
   end
   attribute \src "ls180.v:1803.12-1803.71"
-  process $proc$ls180.v:1803$3539
+  process $proc$ls180.v:1803$3527
     assign { } { }
     assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0
     sync always
@@ -117876,7 +117720,7 @@ module \ls180
       update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
   end
   attribute \src "ls180.v:1804.5-1804.66"
-  process $proc$ls180.v:1804$3540
+  process $proc$ls180.v:1804$3528
     assign { } { }
     assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0
     sync always
@@ -117884,7 +117728,7 @@ module \ls180
       update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
   end
   attribute \src "ls180.v:1805.5-1805.66"
-  process $proc$ls180.v:1805$3541
+  process $proc$ls180.v:1805$3529
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
     sync always
@@ -117892,7 +117736,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
   end
   attribute \src "ls180.v:1806.5-1806.69"
-  process $proc$ls180.v:1806$3542
+  process $proc$ls180.v:1806$3530
     assign { } { }
     assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0
     sync always
@@ -117900,7 +117744,7 @@ module \ls180
       update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
   end
   attribute \src "ls180.v:1807.5-1807.41"
-  process $proc$ls180.v:1807$3543
+  process $proc$ls180.v:1807$3531
     assign { } { }
     assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0
     sync always
@@ -117908,7 +117752,7 @@ module \ls180
       update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0]
   end
   attribute \src "ls180.v:1808.5-1808.46"
-  process $proc$ls180.v:1808$3544
+  process $proc$ls180.v:1808$3532
     assign { } { }
     assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0
     sync always
@@ -117916,7 +117760,7 @@ module \ls180
       update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0]
   end
   attribute \src "ls180.v:1809.5-1809.66"
-  process $proc$ls180.v:1809$3545
+  process $proc$ls180.v:1809$3533
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
     sync always
@@ -117924,7 +117768,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
   end
   attribute \src "ls180.v:181.5-181.63"
-  process $proc$ls180.v:181$2808
+  process $proc$ls180.v:181$2796
     assign { } { }
     assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0
     sync always
@@ -117932,7 +117776,7 @@ module \ls180
       update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0]
   end
   attribute \src "ls180.v:1810.5-1810.69"
-  process $proc$ls180.v:1810$3546
+  process $proc$ls180.v:1810$3534
     assign { } { }
     assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0
     sync always
@@ -117940,7 +117784,7 @@ module \ls180
       update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
   end
   attribute \src "ls180.v:1811.11-1811.41"
-  process $proc$ls180.v:1811$3547
+  process $proc$ls180.v:1811$3535
     assign { } { }
     assign $1\builder_sdphy_fsm_state[2:0] 3'000
     sync always
@@ -117948,7 +117792,7 @@ module \ls180
       update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0]
   end
   attribute \src "ls180.v:1812.11-1812.46"
-  process $proc$ls180.v:1812$3548
+  process $proc$ls180.v:1812$3536
     assign { } { }
     assign $1\builder_sdphy_fsm_next_state[2:0] 3'000
     sync always
@@ -117956,7 +117800,7 @@ module \ls180
       update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0]
   end
   attribute \src "ls180.v:1813.11-1813.61"
-  process $proc$ls180.v:1813$3549
+  process $proc$ls180.v:1813$3537
     assign { } { }
     assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
     sync always
@@ -117964,7 +117808,7 @@ module \ls180
       update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
   end
   attribute \src "ls180.v:1814.5-1814.58"
-  process $proc$ls180.v:1814$3550
+  process $proc$ls180.v:1814$3538
     assign { } { }
     assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0
     sync always
@@ -117972,7 +117816,7 @@ module \ls180
       update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
   end
   attribute \src "ls180.v:1815.11-1815.48"
-  process $proc$ls180.v:1815$3551
+  process $proc$ls180.v:1815$3539
     assign { } { }
     assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000
     sync always
@@ -117980,7 +117824,7 @@ module \ls180
       update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0]
   end
   attribute \src "ls180.v:1816.11-1816.53"
-  process $proc$ls180.v:1816$3552
+  process $proc$ls180.v:1816$3540
     assign { } { }
     assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000
     sync always
@@ -117988,7 +117832,7 @@ module \ls180
       update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0]
   end
   attribute \src "ls180.v:1817.11-1817.70"
-  process $proc$ls180.v:1817$3553
+  process $proc$ls180.v:1817$3541
     assign { } { }
     assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
     sync always
@@ -117996,7 +117840,7 @@ module \ls180
       update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
   end
   attribute \src "ls180.v:1818.5-1818.66"
-  process $proc$ls180.v:1818$3554
+  process $proc$ls180.v:1818$3542
     assign { } { }
     assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
     sync always
@@ -118004,7 +117848,7 @@ module \ls180
       update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
   end
   attribute \src "ls180.v:1819.12-1819.73"
-  process $proc$ls180.v:1819$3555
+  process $proc$ls180.v:1819$3543
     assign { } { }
     assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0
     sync always
@@ -118012,7 +117856,7 @@ module \ls180
       update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
   end
   attribute \src "ls180.v:182.5-182.63"
-  process $proc$ls180.v:182$2809
+  process $proc$ls180.v:182$2797
     assign { } { }
     assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
     sync always
@@ -118020,7 +117864,7 @@ module \ls180
       update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0]
   end
   attribute \src "ls180.v:1820.5-1820.68"
-  process $proc$ls180.v:1820$3556
+  process $proc$ls180.v:1820$3544
     assign { } { }
     assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0
     sync always
@@ -118028,7 +117872,7 @@ module \ls180
       update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
   end
   attribute \src "ls180.v:1821.5-1821.69"
-  process $proc$ls180.v:1821$3557
+  process $proc$ls180.v:1821$3545
     assign { } { }
     assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
     sync always
@@ -118036,7 +117880,7 @@ module \ls180
       update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
   end
   attribute \src "ls180.v:1822.5-1822.72"
-  process $proc$ls180.v:1822$3558
+  process $proc$ls180.v:1822$3546
     assign { } { }
     assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0
     sync always
@@ -118044,7 +117888,7 @@ module \ls180
       update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
   end
   attribute \src "ls180.v:1823.5-1823.52"
-  process $proc$ls180.v:1823$3559
+  process $proc$ls180.v:1823$3547
     assign { } { }
     assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0
     sync always
@@ -118052,7 +117896,7 @@ module \ls180
       update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0]
   end
   attribute \src "ls180.v:1824.5-1824.57"
-  process $proc$ls180.v:1824$3560
+  process $proc$ls180.v:1824$3548
     assign { } { }
     assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0
     sync always
@@ -118060,7 +117904,7 @@ module \ls180
       update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0]
   end
   attribute \src "ls180.v:1825.12-1825.93"
-  process $proc$ls180.v:1825$3561
+  process $proc$ls180.v:1825$3549
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000
     sync always
@@ -118068,7 +117912,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
   end
   attribute \src "ls180.v:1826.5-1826.88"
-  process $proc$ls180.v:1826$3562
+  process $proc$ls180.v:1826$3550
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
     sync always
@@ -118076,7 +117920,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
   end
   attribute \src "ls180.v:1827.12-1827.93"
-  process $proc$ls180.v:1827$3563
+  process $proc$ls180.v:1827$3551
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
     sync always
@@ -118084,7 +117928,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
   end
   attribute \src "ls180.v:1828.5-1828.88"
-  process $proc$ls180.v:1828$3564
+  process $proc$ls180.v:1828$3552
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
     sync always
@@ -118092,7 +117936,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
   end
   attribute \src "ls180.v:1829.12-1829.93"
-  process $proc$ls180.v:1829$3565
+  process $proc$ls180.v:1829$3553
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
     sync always
@@ -118100,7 +117944,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
   end
   attribute \src "ls180.v:1830.5-1830.88"
-  process $proc$ls180.v:1830$3566
+  process $proc$ls180.v:1830$3554
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
     sync always
@@ -118108,7 +117952,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
   end
   attribute \src "ls180.v:1831.12-1831.93"
-  process $proc$ls180.v:1831$3567
+  process $proc$ls180.v:1831$3555
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
     sync always
@@ -118116,7 +117960,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
   end
   attribute \src "ls180.v:1832.5-1832.88"
-  process $proc$ls180.v:1832$3568
+  process $proc$ls180.v:1832$3556
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
     sync always
@@ -118124,7 +117968,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
   end
   attribute \src "ls180.v:1833.11-1833.87"
-  process $proc$ls180.v:1833$3569
+  process $proc$ls180.v:1833$3557
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
     sync always
@@ -118132,7 +117976,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
   end
   attribute \src "ls180.v:1834.5-1834.84"
-  process $proc$ls180.v:1834$3570
+  process $proc$ls180.v:1834$3558
     assign { } { }
     assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
     sync always
@@ -118140,7 +117984,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
   end
   attribute \src "ls180.v:1835.11-1835.42"
-  process $proc$ls180.v:1835$3571
+  process $proc$ls180.v:1835$3559
     assign { } { }
     assign $1\builder_sdcore_fsm_state[2:0] 3'000
     sync always
@@ -118148,7 +117992,7 @@ module \ls180
       update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0]
   end
   attribute \src "ls180.v:1836.11-1836.47"
-  process $proc$ls180.v:1836$3572
+  process $proc$ls180.v:1836$3560
     assign { } { }
     assign $1\builder_sdcore_fsm_next_state[2:0] 3'000
     sync always
@@ -118156,7 +118000,7 @@ module \ls180
       update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0]
   end
   attribute \src "ls180.v:1837.5-1837.55"
-  process $proc$ls180.v:1837$3573
+  process $proc$ls180.v:1837$3561
     assign { } { }
     assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
     sync always
@@ -118164,7 +118008,7 @@ module \ls180
       update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
   end
   attribute \src "ls180.v:1838.5-1838.58"
-  process $proc$ls180.v:1838$3574
+  process $proc$ls180.v:1838$3562
     assign { } { }
     assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
     sync always
@@ -118172,7 +118016,7 @@ module \ls180
       update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
   end
   attribute \src "ls180.v:1839.5-1839.56"
-  process $proc$ls180.v:1839$3575
+  process $proc$ls180.v:1839$3563
     assign { } { }
     assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
     sync always
@@ -118180,7 +118024,7 @@ module \ls180
       update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
   end
   attribute \src "ls180.v:184.5-184.62"
-  process $proc$ls180.v:184$2810
+  process $proc$ls180.v:184$2798
     assign { } { }
     assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
     sync always
@@ -118188,7 +118032,7 @@ module \ls180
       update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0]
   end
   attribute \src "ls180.v:1840.5-1840.59"
-  process $proc$ls180.v:1840$3576
+  process $proc$ls180.v:1840$3564
     assign { } { }
     assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
     sync always
@@ -118196,7 +118040,7 @@ module \ls180
       update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
   end
   attribute \src "ls180.v:1841.11-1841.62"
-  process $proc$ls180.v:1841$3577
+  process $proc$ls180.v:1841$3565
     assign { } { }
     assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
     sync always
@@ -118204,7 +118048,7 @@ module \ls180
       update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
   end
   attribute \src "ls180.v:1842.5-1842.59"
-  process $proc$ls180.v:1842$3578
+  process $proc$ls180.v:1842$3566
     assign { } { }
     assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0
     sync always
@@ -118212,7 +118056,7 @@ module \ls180
       update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
   end
   attribute \src "ls180.v:1843.12-1843.65"
-  process $proc$ls180.v:1843$3579
+  process $proc$ls180.v:1843$3567
     assign { } { }
     assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
     sync always
@@ -118220,7 +118064,7 @@ module \ls180
       update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
   end
   attribute \src "ls180.v:1844.5-1844.60"
-  process $proc$ls180.v:1844$3580
+  process $proc$ls180.v:1844$3568
     assign { } { }
     assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0
     sync always
@@ -118228,7 +118072,7 @@ module \ls180
       update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
   end
   attribute \src "ls180.v:1845.5-1845.56"
-  process $proc$ls180.v:1845$3581
+  process $proc$ls180.v:1845$3569
     assign { } { }
     assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
     sync always
@@ -118236,7 +118080,7 @@ module \ls180
       update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
   end
   attribute \src "ls180.v:1846.5-1846.59"
-  process $proc$ls180.v:1846$3582
+  process $proc$ls180.v:1846$3570
     assign { } { }
     assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0
     sync always
@@ -118244,7 +118088,7 @@ module \ls180
       update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
   end
   attribute \src "ls180.v:1847.5-1847.58"
-  process $proc$ls180.v:1847$3583
+  process $proc$ls180.v:1847$3571
     assign { } { }
     assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0
     sync always
@@ -118252,7 +118096,7 @@ module \ls180
       update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
   end
   attribute \src "ls180.v:1848.5-1848.61"
-  process $proc$ls180.v:1848$3584
+  process $proc$ls180.v:1848$3572
     assign { } { }
     assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0
     sync always
@@ -118260,7 +118104,7 @@ module \ls180
       update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
   end
   attribute \src "ls180.v:1849.5-1849.57"
-  process $proc$ls180.v:1849$3585
+  process $proc$ls180.v:1849$3573
     assign { } { }
     assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0
     sync always
@@ -118268,7 +118112,7 @@ module \ls180
       update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
   end
   attribute \src "ls180.v:185.11-185.69"
-  process $proc$ls180.v:185$2811
+  process $proc$ls180.v:185$2799
     assign { } { }
     assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000
     sync always
@@ -118276,7 +118120,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1850.5-1850.60"
-  process $proc$ls180.v:1850$3586
+  process $proc$ls180.v:1850$3574
     assign { } { }
     assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0
     sync always
@@ -118284,7 +118128,7 @@ module \ls180
       update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
   end
   attribute \src "ls180.v:1851.5-1851.59"
-  process $proc$ls180.v:1851$3587
+  process $proc$ls180.v:1851$3575
     assign { } { }
     assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0
     sync always
@@ -118292,7 +118136,7 @@ module \ls180
       update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
   end
   attribute \src "ls180.v:1852.5-1852.62"
-  process $proc$ls180.v:1852$3588
+  process $proc$ls180.v:1852$3576
     assign { } { }
     assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0
     sync always
@@ -118300,7 +118144,7 @@ module \ls180
       update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
   end
   attribute \src "ls180.v:1853.13-1853.76"
-  process $proc$ls180.v:1853$3589
+  process $proc$ls180.v:1853$3577
     assign { } { }
     assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
     sync always
@@ -118308,7 +118152,7 @@ module \ls180
       update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
   end
   attribute \src "ls180.v:1854.5-1854.69"
-  process $proc$ls180.v:1854$3590
+  process $proc$ls180.v:1854$3578
     assign { } { }
     assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0
     sync always
@@ -118316,7 +118160,7 @@ module \ls180
       update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
   end
   attribute \src "ls180.v:1855.11-1855.46"
-  process $proc$ls180.v:1855$3591
+  process $proc$ls180.v:1855$3579
     assign { } { }
     assign $1\builder_sdblock2memdma_state[1:0] 2'00
     sync always
@@ -118324,7 +118168,7 @@ module \ls180
       update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0]
   end
   attribute \src "ls180.v:1856.11-1856.51"
-  process $proc$ls180.v:1856$3592
+  process $proc$ls180.v:1856$3580
     assign { } { }
     assign $1\builder_sdblock2memdma_next_state[1:0] 2'00
     sync always
@@ -118332,7 +118176,7 @@ module \ls180
       update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0]
   end
   attribute \src "ls180.v:1857.12-1857.87"
-  process $proc$ls180.v:1857$3593
+  process $proc$ls180.v:1857$3581
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
     sync always
@@ -118340,7 +118184,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
   end
   attribute \src "ls180.v:1858.5-1858.82"
-  process $proc$ls180.v:1858$3594
+  process $proc$ls180.v:1858$3582
     assign { } { }
     assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0
     sync always
@@ -118348,7 +118192,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
   end
   attribute \src "ls180.v:1859.5-1859.44"
-  process $proc$ls180.v:1859$3595
+  process $proc$ls180.v:1859$3583
     assign { } { }
     assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0
     sync always
@@ -118356,7 +118200,7 @@ module \ls180
       update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0]
   end
   attribute \src "ls180.v:186.11-186.69"
-  process $proc$ls180.v:186$2812
+  process $proc$ls180.v:186$2800
     assign { } { }
     assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00
     sync always
@@ -118364,7 +118208,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1860.5-1860.49"
-  process $proc$ls180.v:1860$3596
+  process $proc$ls180.v:1860$3584
     assign { } { }
     assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0
     sync always
@@ -118372,7 +118216,7 @@ module \ls180
       update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0]
   end
   attribute \src "ls180.v:1861.12-1861.75"
-  process $proc$ls180.v:1861$3597
+  process $proc$ls180.v:1861$3585
     assign { } { }
     assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0
     sync always
@@ -118380,7 +118224,7 @@ module \ls180
       update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
   end
   attribute \src "ls180.v:1862.5-1862.70"
-  process $proc$ls180.v:1862$3598
+  process $proc$ls180.v:1862$3586
     assign { } { }
     assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0
     sync always
@@ -118388,7 +118232,7 @@ module \ls180
       update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
   end
   attribute \src "ls180.v:1863.11-1863.60"
-  process $proc$ls180.v:1863$3599
+  process $proc$ls180.v:1863$3587
     assign { } { }
     assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
     sync always
@@ -118396,7 +118240,7 @@ module \ls180
       update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0]
   end
   attribute \src "ls180.v:1864.11-1864.65"
-  process $proc$ls180.v:1864$3600
+  process $proc$ls180.v:1864$3588
     assign { } { }
     assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00
     sync always
@@ -118404,7 +118248,7 @@ module \ls180
       update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0]
   end
   attribute \src "ls180.v:1865.12-1865.87"
-  process $proc$ls180.v:1865$3601
+  process $proc$ls180.v:1865$3589
     assign { } { }
     assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
     sync always
@@ -118412,7 +118256,7 @@ module \ls180
       update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
   end
   attribute \src "ls180.v:1866.5-1866.82"
-  process $proc$ls180.v:1866$3602
+  process $proc$ls180.v:1866$3590
     assign { } { }
     assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0
     sync always
@@ -118420,7 +118264,7 @@ module \ls180
       update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
   end
   attribute \src "ls180.v:1867.12-1867.43"
-  process $proc$ls180.v:1867$3603
+  process $proc$ls180.v:1867$3591
     assign { } { }
     assign $1\builder_libresocsim_adr[13:0] 14'00000000000000
     sync always
@@ -118428,7 +118272,7 @@ module \ls180
       update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0]
   end
   attribute \src "ls180.v:1868.5-1868.34"
-  process $proc$ls180.v:1868$3604
+  process $proc$ls180.v:1868$3592
     assign { } { }
     assign $1\builder_libresocsim_we[0:0] 1'0
     sync always
@@ -118436,7 +118280,7 @@ module \ls180
       update \builder_libresocsim_we $1\builder_libresocsim_we[0:0]
   end
   attribute \src "ls180.v:1869.11-1869.43"
-  process $proc$ls180.v:1869$3605
+  process $proc$ls180.v:1869$3593
     assign { } { }
     assign $1\builder_libresocsim_dat_w[7:0] 8'00000000
     sync always
@@ -118444,7 +118288,7 @@ module \ls180
       update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0]
   end
   attribute \src "ls180.v:1873.12-1873.54"
-  process $proc$ls180.v:1873$3606
+  process $proc$ls180.v:1873$3594
     assign { } { }
     assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0
     sync always
@@ -118452,7 +118296,7 @@ module \ls180
       update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0]
   end
   attribute \src "ls180.v:1877.5-1877.44"
-  process $proc$ls180.v:1877$3607
+  process $proc$ls180.v:1877$3595
     assign { } { }
     assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0
     sync always
@@ -118460,7 +118304,7 @@ module \ls180
       update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0]
   end
   attribute \src "ls180.v:188.5-188.44"
-  process $proc$ls180.v:188$2813
+  process $proc$ls180.v:188$2801
     assign { } { }
     assign $1\main_libresocsim_converter1_skip[0:0] 1'0
     sync always
@@ -118468,7 +118312,7 @@ module \ls180
       update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0]
   end
   attribute \src "ls180.v:1881.5-1881.44"
-  process $proc$ls180.v:1881$3608
+  process $proc$ls180.v:1881$3596
     assign { } { }
     assign $0\builder_libresocsim_wishbone_err[0:0] 1'0
     sync always
@@ -118476,7 +118320,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:1884.12-1884.40"
-  process $proc$ls180.v:1884$3609
+  process $proc$ls180.v:1884$3597
     assign { } { }
     assign $1\builder_shared_dat_r[31:0] 0
     sync always
@@ -118484,7 +118328,7 @@ module \ls180
       update \builder_shared_dat_r $1\builder_shared_dat_r[31:0]
   end
   attribute \src "ls180.v:1888.5-1888.30"
-  process $proc$ls180.v:1888$3610
+  process $proc$ls180.v:1888$3598
     assign { } { }
     assign $1\builder_shared_ack[0:0] 1'0
     sync always
@@ -118492,7 +118336,7 @@ module \ls180
       update \builder_shared_ack $1\builder_shared_ack[0:0]
   end
   attribute \src "ls180.v:189.5-189.47"
-  process $proc$ls180.v:189$2814
+  process $proc$ls180.v:189$2802
     assign { } { }
     assign $1\main_libresocsim_converter1_counter[0:0] 1'0
     sync always
@@ -118500,7 +118344,7 @@ module \ls180
       update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0]
   end
   attribute \src "ls180.v:1894.11-1894.31"
-  process $proc$ls180.v:1894$3611
+  process $proc$ls180.v:1894$3599
     assign { } { }
     assign $1\builder_grant[2:0] 3'000
     sync always
@@ -118508,7 +118352,7 @@ module \ls180
       update \builder_grant $1\builder_grant[2:0]
   end
   attribute \src "ls180.v:1895.11-1895.35"
-  process $proc$ls180.v:1895$3612
+  process $proc$ls180.v:1895$3600
     assign { } { }
     assign $1\builder_slave_sel[4:0] 5'00000
     sync always
@@ -118516,7 +118360,7 @@ module \ls180
       update \builder_slave_sel $1\builder_slave_sel[4:0]
   end
   attribute \src "ls180.v:1896.11-1896.37"
-  process $proc$ls180.v:1896$3613
+  process $proc$ls180.v:1896$3601
     assign { } { }
     assign $1\builder_slave_sel_r[4:0] 5'00000
     sync always
@@ -118524,7 +118368,7 @@ module \ls180
       update \builder_slave_sel_r $1\builder_slave_sel_r[4:0]
   end
   attribute \src "ls180.v:1897.5-1897.25"
-  process $proc$ls180.v:1897$3614
+  process $proc$ls180.v:1897$3602
     assign { } { }
     assign $1\builder_error[0:0] 1'0
     sync always
@@ -118532,7 +118376,7 @@ module \ls180
       update \builder_error $1\builder_error[0:0]
   end
   attribute \src "ls180.v:1900.12-1900.39"
-  process $proc$ls180.v:1900$3615
+  process $proc$ls180.v:1900$3603
     assign { } { }
     assign $1\builder_count[19:0] 20'11110100001001000000
     sync always
@@ -118540,7 +118384,7 @@ module \ls180
       update \builder_count $1\builder_count[19:0]
   end
   attribute \src "ls180.v:1904.11-1904.51"
-  process $proc$ls180.v:1904$3616
+  process $proc$ls180.v:1904$3604
     assign { } { }
     assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118548,7 +118392,7 @@ module \ls180
       update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:191.12-191.53"
-  process $proc$ls180.v:191$2815
+  process $proc$ls180.v:191$2803
     assign { } { }
     assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
@@ -118556,7 +118400,7 @@ module \ls180
       update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0]
   end
   attribute \src "ls180.v:192.12-192.71"
-  process $proc$ls180.v:192$2816
+  process $proc$ls180.v:192$2804
     assign { } { }
     assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
     sync always
@@ -118564,7 +118408,7 @@ module \ls180
       update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0]
   end
   attribute \src "ls180.v:193.12-193.73"
-  process $proc$ls180.v:193$2817
+  process $proc$ls180.v:193$2805
     assign { } { }
     assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0
     sync always
@@ -118572,7 +118416,7 @@ module \ls180
       update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0]
   end
   attribute \src "ls180.v:1945.11-1945.51"
-  process $proc$ls180.v:1945$3617
+  process $proc$ls180.v:1945$3605
     assign { } { }
     assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118580,7 +118424,7 @@ module \ls180
       update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:195.11-195.69"
-  process $proc$ls180.v:195$2818
+  process $proc$ls180.v:195$2806
     assign { } { }
     assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000
     sync always
@@ -118588,7 +118432,7 @@ module \ls180
       update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0]
   end
   attribute \src "ls180.v:196.5-196.63"
-  process $proc$ls180.v:196$2819
+  process $proc$ls180.v:196$2807
     assign { } { }
     assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0
     sync always
@@ -118596,7 +118440,7 @@ module \ls180
       update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0]
   end
   attribute \src "ls180.v:197.5-197.63"
-  process $proc$ls180.v:197$2820
+  process $proc$ls180.v:197$2808
     assign { } { }
     assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0
     sync always
@@ -118604,7 +118448,7 @@ module \ls180
       update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0]
   end
   attribute \src "ls180.v:1974.11-1974.51"
-  process $proc$ls180.v:1974$3618
+  process $proc$ls180.v:1974$3606
     assign { } { }
     assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118612,7 +118456,7 @@ module \ls180
       update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:1987.11-1987.51"
-  process $proc$ls180.v:1987$3619
+  process $proc$ls180.v:1987$3607
     assign { } { }
     assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118620,7 +118464,7 @@ module \ls180
       update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:199.5-199.62"
-  process $proc$ls180.v:199$2821
+  process $proc$ls180.v:199$2809
     assign { } { }
     assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0
     sync always
@@ -118628,7 +118472,7 @@ module \ls180
       update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0]
   end
   attribute \src "ls180.v:200.11-200.69"
-  process $proc$ls180.v:200$2822
+  process $proc$ls180.v:200$2810
     assign { } { }
     assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000
     sync always
@@ -118636,7 +118480,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:201.11-201.69"
-  process $proc$ls180.v:201$2823
+  process $proc$ls180.v:201$2811
     assign { } { }
     assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00
     sync always
@@ -118644,7 +118488,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:2028.11-2028.51"
-  process $proc$ls180.v:2028$3620
+  process $proc$ls180.v:2028$3608
     assign { } { }
     assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118652,7 +118496,7 @@ module \ls180
       update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:203.5-203.44"
-  process $proc$ls180.v:203$2824
+  process $proc$ls180.v:203$2812
     assign { } { }
     assign $1\main_libresocsim_converter2_skip[0:0] 1'0
     sync always
@@ -118660,7 +118504,7 @@ module \ls180
       update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0]
   end
   attribute \src "ls180.v:204.5-204.47"
-  process $proc$ls180.v:204$2825
+  process $proc$ls180.v:204$2813
     assign { } { }
     assign $1\main_libresocsim_converter2_counter[0:0] 1'0
     sync always
@@ -118668,7 +118512,7 @@ module \ls180
       update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0]
   end
   attribute \src "ls180.v:206.12-206.53"
-  process $proc$ls180.v:206$2826
+  process $proc$ls180.v:206$2814
     assign { } { }
     assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
@@ -118676,7 +118520,7 @@ module \ls180
       update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0]
   end
   attribute \src "ls180.v:2069.11-2069.51"
-  process $proc$ls180.v:2069$3621
+  process $proc$ls180.v:2069$3609
     assign { } { }
     assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118684,7 +118528,7 @@ module \ls180
       update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:213.5-213.40"
-  process $proc$ls180.v:213$2827
+  process $proc$ls180.v:213$2815
     assign { } { }
     assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0
     sync always
@@ -118692,7 +118536,7 @@ module \ls180
       update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0]
   end
   attribute \src "ls180.v:2134.11-2134.51"
-  process $proc$ls180.v:2134$3622
+  process $proc$ls180.v:2134$3610
     assign { } { }
     assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118700,7 +118544,7 @@ module \ls180
       update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:217.5-217.40"
-  process $proc$ls180.v:217$2828
+  process $proc$ls180.v:217$2816
     assign { } { }
     assign $0\main_libresocsim_ram_bus_err[0:0] 1'0
     sync always
@@ -118708,7 +118552,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:220.11-220.37"
-  process $proc$ls180.v:220$2829
+  process $proc$ls180.v:220$2817
     assign { } { }
     assign $1\main_libresocsim_we[3:0] 4'0000
     sync always
@@ -118716,7 +118560,7 @@ module \ls180
       update \main_libresocsim_we $1\main_libresocsim_we[3:0]
   end
   attribute \src "ls180.v:222.12-222.49"
-  process $proc$ls180.v:222$2830
+  process $proc$ls180.v:222$2818
     assign { } { }
     assign $1\main_libresocsim_load_storage[31:0] 0
     sync always
@@ -118724,7 +118568,7 @@ module \ls180
       update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0]
   end
   attribute \src "ls180.v:223.5-223.36"
-  process $proc$ls180.v:223$2831
+  process $proc$ls180.v:223$2819
     assign { } { }
     assign $1\main_libresocsim_load_re[0:0] 1'0
     sync always
@@ -118732,7 +118576,7 @@ module \ls180
       update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0]
   end
   attribute \src "ls180.v:224.12-224.51"
-  process $proc$ls180.v:224$2832
+  process $proc$ls180.v:224$2820
     assign { } { }
     assign $1\main_libresocsim_reload_storage[31:0] 0
     sync always
@@ -118740,7 +118584,7 @@ module \ls180
       update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0]
   end
   attribute \src "ls180.v:225.5-225.38"
-  process $proc$ls180.v:225$2833
+  process $proc$ls180.v:225$2821
     assign { } { }
     assign $1\main_libresocsim_reload_re[0:0] 1'0
     sync always
@@ -118748,7 +118592,7 @@ module \ls180
       update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0]
   end
   attribute \src "ls180.v:226.5-226.39"
-  process $proc$ls180.v:226$2834
+  process $proc$ls180.v:226$2822
     assign { } { }
     assign $1\main_libresocsim_en_storage[0:0] 1'0
     sync always
@@ -118756,7 +118600,7 @@ module \ls180
       update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0]
   end
   attribute \src "ls180.v:2267.11-2267.51"
-  process $proc$ls180.v:2267$3623
+  process $proc$ls180.v:2267$3611
     assign { } { }
     assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118764,7 +118608,7 @@ module \ls180
       update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:227.5-227.34"
-  process $proc$ls180.v:227$2835
+  process $proc$ls180.v:227$2823
     assign { } { }
     assign $1\main_libresocsim_en_re[0:0] 1'0
     sync always
@@ -118772,7 +118616,7 @@ module \ls180
       update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0]
   end
   attribute \src "ls180.v:228.5-228.49"
-  process $proc$ls180.v:228$2836
+  process $proc$ls180.v:228$2824
     assign { } { }
     assign $1\main_libresocsim_update_value_storage[0:0] 1'0
     sync always
@@ -118780,7 +118624,7 @@ module \ls180
       update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0]
   end
   attribute \src "ls180.v:229.5-229.44"
-  process $proc$ls180.v:229$2837
+  process $proc$ls180.v:229$2825
     assign { } { }
     assign $1\main_libresocsim_update_value_re[0:0] 1'0
     sync always
@@ -118788,7 +118632,7 @@ module \ls180
       update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0]
   end
   attribute \src "ls180.v:230.12-230.49"
-  process $proc$ls180.v:230$2838
+  process $proc$ls180.v:230$2826
     assign { } { }
     assign $1\main_libresocsim_value_status[31:0] 0
     sync always
@@ -118796,7 +118640,7 @@ module \ls180
       update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0]
   end
   attribute \src "ls180.v:234.5-234.41"
-  process $proc$ls180.v:234$2839
+  process $proc$ls180.v:234$2827
     assign { } { }
     assign $1\main_libresocsim_zero_pending[0:0] 1'0
     sync always
@@ -118804,7 +118648,7 @@ module \ls180
       update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0]
   end
   attribute \src "ls180.v:2348.11-2348.51"
-  process $proc$ls180.v:2348$3624
+  process $proc$ls180.v:2348$3612
     assign { } { }
     assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118812,7 +118656,7 @@ module \ls180
       update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:236.5-236.39"
-  process $proc$ls180.v:236$2840
+  process $proc$ls180.v:236$2828
     assign { } { }
     assign $1\main_libresocsim_zero_clear[0:0] 1'0
     sync always
@@ -118820,7 +118664,7 @@ module \ls180
       update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0]
   end
   attribute \src "ls180.v:2365.11-2365.51"
-  process $proc$ls180.v:2365$3625
+  process $proc$ls180.v:2365$3613
     assign { } { }
     assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118828,7 +118672,7 @@ module \ls180
       update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:237.5-237.45"
-  process $proc$ls180.v:237$2841
+  process $proc$ls180.v:237$2829
     assign { } { }
     assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0
     sync always
@@ -118836,7 +118680,7 @@ module \ls180
       update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0]
   end
   attribute \src "ls180.v:2406.11-2406.52"
-  process $proc$ls180.v:2406$3626
+  process $proc$ls180.v:2406$3614
     assign { } { }
     assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118844,7 +118688,7 @@ module \ls180
       update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:2439.11-2439.52"
-  process $proc$ls180.v:2439$3627
+  process $proc$ls180.v:2439$3615
     assign { } { }
     assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118852,7 +118696,7 @@ module \ls180
       update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:246.5-246.49"
-  process $proc$ls180.v:246$2842
+  process $proc$ls180.v:246$2830
     assign { } { }
     assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0
     sync always
@@ -118860,7 +118704,7 @@ module \ls180
       update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0]
   end
   attribute \src "ls180.v:247.5-247.44"
-  process $proc$ls180.v:247$2843
+  process $proc$ls180.v:247$2831
     assign { } { }
     assign $1\main_libresocsim_eventmanager_re[0:0] 1'0
     sync always
@@ -118868,7 +118712,7 @@ module \ls180
       update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0]
   end
   attribute \src "ls180.v:248.12-248.42"
-  process $proc$ls180.v:248$2844
+  process $proc$ls180.v:248$2832
     assign { } { }
     assign $1\main_libresocsim_value[31:0] 0
     sync always
@@ -118876,7 +118720,7 @@ module \ls180
       update \main_libresocsim_value $1\main_libresocsim_value[31:0]
   end
   attribute \src "ls180.v:2480.11-2480.52"
-  process $proc$ls180.v:2480$3628
+  process $proc$ls180.v:2480$3616
     assign { } { }
     assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118884,7 +118728,7 @@ module \ls180
       update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:252.5-252.24"
-  process $proc$ls180.v:252$2845
+  process $proc$ls180.v:252$2833
     assign { } { }
     assign $1\main_int_rst[0:0] 1'1
     sync always
@@ -118892,7 +118736,7 @@ module \ls180
       update \main_int_rst $1\main_int_rst[0:0]
   end
   attribute \src "ls180.v:2545.11-2545.52"
-  process $proc$ls180.v:2545$3629
+  process $proc$ls180.v:2545$3617
     assign { } { }
     assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118900,7 +118744,7 @@ module \ls180
       update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:2570.11-2570.52"
-  process $proc$ls180.v:2570$3630
+  process $proc$ls180.v:2570$3618
     assign { } { }
     assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000
     sync always
@@ -118908,7 +118752,7 @@ module \ls180
       update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0]
   end
   attribute \src "ls180.v:2592.11-2592.31"
-  process $proc$ls180.v:2592$3631
+  process $proc$ls180.v:2592$3619
     assign { } { }
     assign $1\builder_state[1:0] 2'00
     sync always
@@ -118916,7 +118760,7 @@ module \ls180
       update \builder_state $1\builder_state[1:0]
   end
   attribute \src "ls180.v:2593.11-2593.36"
-  process $proc$ls180.v:2593$3632
+  process $proc$ls180.v:2593$3620
     assign { } { }
     assign $1\builder_next_state[1:0] 2'00
     sync always
@@ -118924,7 +118768,7 @@ module \ls180
       update \builder_next_state $1\builder_next_state[1:0]
   end
   attribute \src "ls180.v:2594.11-2594.55"
-  process $proc$ls180.v:2594$3633
+  process $proc$ls180.v:2594$3621
     assign { } { }
     assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000
     sync always
@@ -118932,7 +118776,7 @@ module \ls180
       update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0]
   end
   attribute \src "ls180.v:2595.5-2595.52"
-  process $proc$ls180.v:2595$3634
+  process $proc$ls180.v:2595$3622
     assign { } { }
     assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0
     sync always
@@ -118940,7 +118784,7 @@ module \ls180
       update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0]
   end
   attribute \src "ls180.v:2596.12-2596.55"
-  process $proc$ls180.v:2596$3635
+  process $proc$ls180.v:2596$3623
     assign { } { }
     assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000
     sync always
@@ -118948,7 +118792,7 @@ module \ls180
       update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0]
   end
   attribute \src "ls180.v:2597.5-2597.50"
-  process $proc$ls180.v:2597$3636
+  process $proc$ls180.v:2597$3624
     assign { } { }
     assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
     sync always
@@ -118956,7 +118800,7 @@ module \ls180
       update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0]
   end
   attribute \src "ls180.v:2598.5-2598.46"
-  process $proc$ls180.v:2598$3637
+  process $proc$ls180.v:2598$3625
     assign { } { }
     assign $1\builder_libresocsim_we_next_value2[0:0] 1'0
     sync always
@@ -118964,7 +118808,7 @@ module \ls180
       update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0]
   end
   attribute \src "ls180.v:2599.5-2599.49"
-  process $proc$ls180.v:2599$3638
+  process $proc$ls180.v:2599$3626
     assign { } { }
     assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0
     sync always
@@ -118972,7 +118816,7 @@ module \ls180
       update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0]
   end
   attribute \src "ls180.v:2600.5-2600.41"
-  process $proc$ls180.v:2600$3639
+  process $proc$ls180.v:2600$3627
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0
     sync always
@@ -118980,7 +118824,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0]
   end
   attribute \src "ls180.v:2601.12-2601.49"
-  process $proc$ls180.v:2601$3640
+  process $proc$ls180.v:2601$3628
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000
     sync always
@@ -118988,7 +118832,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0]
   end
   attribute \src "ls180.v:2602.11-2602.47"
-  process $proc$ls180.v:2602$3641
+  process $proc$ls180.v:2602$3629
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00
     sync always
@@ -118996,7 +118840,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0]
   end
   attribute \src "ls180.v:2603.5-2603.41"
-  process $proc$ls180.v:2603$3642
+  process $proc$ls180.v:2603$3630
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0
     sync always
@@ -119004,7 +118848,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0]
   end
   attribute \src "ls180.v:2604.5-2604.41"
-  process $proc$ls180.v:2604$3643
+  process $proc$ls180.v:2604$3631
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0
     sync always
@@ -119012,7 +118856,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0]
   end
   attribute \src "ls180.v:2605.5-2605.41"
-  process $proc$ls180.v:2605$3644
+  process $proc$ls180.v:2605$3632
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0
     sync always
@@ -119020,7 +118864,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0]
   end
   attribute \src "ls180.v:2606.5-2606.39"
-  process $proc$ls180.v:2606$3645
+  process $proc$ls180.v:2606$3633
     assign { } { }
     assign $1\builder_comb_t_array_muxed0[0:0] 1'0
     sync always
@@ -119028,7 +118872,7 @@ module \ls180
       update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0]
   end
   attribute \src "ls180.v:2607.5-2607.39"
-  process $proc$ls180.v:2607$3646
+  process $proc$ls180.v:2607$3634
     assign { } { }
     assign $1\builder_comb_t_array_muxed1[0:0] 1'0
     sync always
@@ -119036,7 +118880,7 @@ module \ls180
       update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0]
   end
   attribute \src "ls180.v:2608.5-2608.39"
-  process $proc$ls180.v:2608$3647
+  process $proc$ls180.v:2608$3635
     assign { } { }
     assign $1\builder_comb_t_array_muxed2[0:0] 1'0
     sync always
@@ -119044,7 +118888,7 @@ module \ls180
       update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0]
   end
   attribute \src "ls180.v:2609.5-2609.41"
-  process $proc$ls180.v:2609$3648
+  process $proc$ls180.v:2609$3636
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0
     sync always
@@ -119052,7 +118896,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0]
   end
   attribute \src "ls180.v:2610.12-2610.49"
-  process $proc$ls180.v:2610$3649
+  process $proc$ls180.v:2610$3637
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000
     sync always
@@ -119060,7 +118904,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0]
   end
   attribute \src "ls180.v:2611.11-2611.47"
-  process $proc$ls180.v:2611$3650
+  process $proc$ls180.v:2611$3638
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00
     sync always
@@ -119068,7 +118912,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0]
   end
   attribute \src "ls180.v:2612.5-2612.41"
-  process $proc$ls180.v:2612$3651
+  process $proc$ls180.v:2612$3639
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0
     sync always
@@ -119076,7 +118920,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0]
   end
   attribute \src "ls180.v:2613.5-2613.42"
-  process $proc$ls180.v:2613$3652
+  process $proc$ls180.v:2613$3640
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0
     sync always
@@ -119084,7 +118928,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0]
   end
   attribute \src "ls180.v:2614.5-2614.42"
-  process $proc$ls180.v:2614$3653
+  process $proc$ls180.v:2614$3641
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0
     sync always
@@ -119092,7 +118936,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0]
   end
   attribute \src "ls180.v:2615.5-2615.39"
-  process $proc$ls180.v:2615$3654
+  process $proc$ls180.v:2615$3642
     assign { } { }
     assign $1\builder_comb_t_array_muxed3[0:0] 1'0
     sync always
@@ -119100,7 +118944,7 @@ module \ls180
       update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0]
   end
   attribute \src "ls180.v:2616.5-2616.39"
-  process $proc$ls180.v:2616$3655
+  process $proc$ls180.v:2616$3643
     assign { } { }
     assign $1\builder_comb_t_array_muxed4[0:0] 1'0
     sync always
@@ -119108,7 +118952,7 @@ module \ls180
       update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0]
   end
   attribute \src "ls180.v:2617.5-2617.39"
-  process $proc$ls180.v:2617$3656
+  process $proc$ls180.v:2617$3644
     assign { } { }
     assign $1\builder_comb_t_array_muxed5[0:0] 1'0
     sync always
@@ -119116,7 +118960,7 @@ module \ls180
       update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0]
   end
   attribute \src "ls180.v:2618.12-2618.50"
-  process $proc$ls180.v:2618$3657
+  process $proc$ls180.v:2618$3645
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000
     sync always
@@ -119124,7 +118968,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0]
   end
   attribute \src "ls180.v:2619.5-2619.42"
-  process $proc$ls180.v:2619$3658
+  process $proc$ls180.v:2619$3646
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0
     sync always
@@ -119132,7 +118976,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0]
   end
   attribute \src "ls180.v:2620.5-2620.42"
-  process $proc$ls180.v:2620$3659
+  process $proc$ls180.v:2620$3647
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0
     sync always
@@ -119140,7 +118984,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0]
   end
   attribute \src "ls180.v:2621.12-2621.50"
-  process $proc$ls180.v:2621$3660
+  process $proc$ls180.v:2621$3648
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000
     sync always
@@ -119148,7 +118992,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0]
   end
   attribute \src "ls180.v:2622.5-2622.42"
-  process $proc$ls180.v:2622$3661
+  process $proc$ls180.v:2622$3649
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0
     sync always
@@ -119156,7 +119000,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0]
   end
   attribute \src "ls180.v:2623.5-2623.42"
-  process $proc$ls180.v:2623$3662
+  process $proc$ls180.v:2623$3650
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0
     sync always
@@ -119164,7 +119008,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0]
   end
   attribute \src "ls180.v:2624.12-2624.50"
-  process $proc$ls180.v:2624$3663
+  process $proc$ls180.v:2624$3651
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000
     sync always
@@ -119172,7 +119016,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0]
   end
   attribute \src "ls180.v:2625.5-2625.42"
-  process $proc$ls180.v:2625$3664
+  process $proc$ls180.v:2625$3652
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0
     sync always
@@ -119180,7 +119024,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0]
   end
   attribute \src "ls180.v:2626.5-2626.42"
-  process $proc$ls180.v:2626$3665
+  process $proc$ls180.v:2626$3653
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0
     sync always
@@ -119188,7 +119032,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0]
   end
   attribute \src "ls180.v:2627.12-2627.50"
-  process $proc$ls180.v:2627$3666
+  process $proc$ls180.v:2627$3654
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000
     sync always
@@ -119196,7 +119040,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0]
   end
   attribute \src "ls180.v:2628.5-2628.42"
-  process $proc$ls180.v:2628$3667
+  process $proc$ls180.v:2628$3655
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0
     sync always
@@ -119204,7 +119048,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0]
   end
   attribute \src "ls180.v:2629.5-2629.42"
-  process $proc$ls180.v:2629$3668
+  process $proc$ls180.v:2629$3656
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0
     sync always
@@ -119212,7 +119056,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0]
   end
   attribute \src "ls180.v:2630.12-2630.50"
-  process $proc$ls180.v:2630$3669
+  process $proc$ls180.v:2630$3657
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed24[31:0] 0
     sync always
@@ -119220,7 +119064,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0]
   end
   attribute \src "ls180.v:2631.12-2631.50"
-  process $proc$ls180.v:2631$3670
+  process $proc$ls180.v:2631$3658
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed25[31:0] 0
     sync always
@@ -119228,7 +119072,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0]
   end
   attribute \src "ls180.v:2632.11-2632.48"
-  process $proc$ls180.v:2632$3671
+  process $proc$ls180.v:2632$3659
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000
     sync always
@@ -119236,7 +119080,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0]
   end
   attribute \src "ls180.v:2633.5-2633.42"
-  process $proc$ls180.v:2633$3672
+  process $proc$ls180.v:2633$3660
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0
     sync always
@@ -119244,7 +119088,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0]
   end
   attribute \src "ls180.v:2634.5-2634.42"
-  process $proc$ls180.v:2634$3673
+  process $proc$ls180.v:2634$3661
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0
     sync always
@@ -119252,7 +119096,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0]
   end
   attribute \src "ls180.v:2635.5-2635.42"
-  process $proc$ls180.v:2635$3674
+  process $proc$ls180.v:2635$3662
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0
     sync always
@@ -119260,7 +119104,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0]
   end
   attribute \src "ls180.v:2636.11-2636.48"
-  process $proc$ls180.v:2636$3675
+  process $proc$ls180.v:2636$3663
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000
     sync always
@@ -119268,7 +119112,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0]
   end
   attribute \src "ls180.v:2637.11-2637.48"
-  process $proc$ls180.v:2637$3676
+  process $proc$ls180.v:2637$3664
     assign { } { }
     assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00
     sync always
@@ -119276,7 +119120,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0]
   end
   attribute \src "ls180.v:2638.11-2638.47"
-  process $proc$ls180.v:2638$3677
+  process $proc$ls180.v:2638$3665
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00
     sync always
@@ -119284,7 +119128,7 @@ module \ls180
       update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0]
   end
   attribute \src "ls180.v:2639.12-2639.49"
-  process $proc$ls180.v:2639$3678
+  process $proc$ls180.v:2639$3666
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000
     sync always
@@ -119292,7 +119136,7 @@ module \ls180
       update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0]
   end
   attribute \src "ls180.v:2640.5-2640.41"
-  process $proc$ls180.v:2640$3679
+  process $proc$ls180.v:2640$3667
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0
     sync always
@@ -119300,7 +119144,7 @@ module \ls180
       update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0]
   end
   attribute \src "ls180.v:2641.5-2641.41"
-  process $proc$ls180.v:2641$3680
+  process $proc$ls180.v:2641$3668
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0
     sync always
@@ -119308,7 +119152,7 @@ module \ls180
       update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0]
   end
   attribute \src "ls180.v:2642.5-2642.41"
-  process $proc$ls180.v:2642$3681
+  process $proc$ls180.v:2642$3669
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0
     sync always
@@ -119316,7 +119160,7 @@ module \ls180
       update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0]
   end
   attribute \src "ls180.v:2643.5-2643.41"
-  process $proc$ls180.v:2643$3682
+  process $proc$ls180.v:2643$3670
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0
     sync always
@@ -119324,7 +119168,7 @@ module \ls180
       update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0]
   end
   attribute \src "ls180.v:2644.5-2644.41"
-  process $proc$ls180.v:2644$3683
+  process $proc$ls180.v:2644$3671
     assign { } { }
     assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0
     sync always
@@ -119332,7 +119176,7 @@ module \ls180
       update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0]
   end
   attribute \src "ls180.v:2645.5-2645.39"
-  process $proc$ls180.v:2645$3684
+  process $proc$ls180.v:2645$3672
     assign { } { }
     assign $1\builder_sync_f_array_muxed0[0:0] 1'0
     sync always
@@ -119340,7 +119184,7 @@ module \ls180
       update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0]
   end
   attribute \src "ls180.v:2646.5-2646.39"
-  process $proc$ls180.v:2646$3685
+  process $proc$ls180.v:2646$3673
     assign { } { }
     assign $1\builder_sync_f_array_muxed1[0:0] 1'0
     sync always
@@ -119348,7 +119192,7 @@ module \ls180
       update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0]
   end
   attribute \src "ls180.v:267.12-267.38"
-  process $proc$ls180.v:267$2846
+  process $proc$ls180.v:267$2834
     assign { } { }
     assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000
     sync always
@@ -119356,7 +119200,7 @@ module \ls180
       update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0]
   end
   attribute \src "ls180.v:268.5-268.36"
-  process $proc$ls180.v:268$2847
+  process $proc$ls180.v:268$2835
     assign { } { }
     assign $1\main_dfi_p0_rddata_valid[0:0] 1'0
     sync always
@@ -119364,7 +119208,7 @@ module \ls180
       update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0]
   end
   attribute \src "ls180.v:269.11-269.32"
-  process $proc$ls180.v:269$2848
+  process $proc$ls180.v:269$2836
     assign { } { }
     assign $1\main_rddata_en[2:0] 3'000
     sync always
@@ -119372,7 +119216,7 @@ module \ls180
       update \main_rddata_en $1\main_rddata_en[2:0]
   end
   attribute \src "ls180.v:2703.32-2703.66"
-  process $proc$ls180.v:2703$3686
+  process $proc$ls180.v:2703$3674
     assign { } { }
     assign $1\builder_multiregimpl0_regs0[0:0] 1'0
     sync always
@@ -119380,7 +119224,7 @@ module \ls180
       update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0]
   end
   attribute \src "ls180.v:2704.32-2704.66"
-  process $proc$ls180.v:2704$3687
+  process $proc$ls180.v:2704$3675
     assign { } { }
     assign $1\builder_multiregimpl0_regs1[0:0] 1'0
     sync always
@@ -119388,7 +119232,7 @@ module \ls180
       update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0]
   end
   attribute \src "ls180.v:2705.32-2705.66"
-  process $proc$ls180.v:2705$3688
+  process $proc$ls180.v:2705$3676
     assign { } { }
     assign $1\builder_multiregimpl1_regs0[0:0] 1'0
     sync always
@@ -119396,7 +119240,7 @@ module \ls180
       update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0]
   end
   attribute \src "ls180.v:2706.32-2706.66"
-  process $proc$ls180.v:2706$3689
+  process $proc$ls180.v:2706$3677
     assign { } { }
     assign $1\builder_multiregimpl1_regs1[0:0] 1'0
     sync always
@@ -119404,7 +119248,7 @@ module \ls180
       update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0]
   end
   attribute \src "ls180.v:2707.32-2707.66"
-  process $proc$ls180.v:2707$3690
+  process $proc$ls180.v:2707$3678
     assign { } { }
     assign $1\builder_multiregimpl2_regs0[0:0] 1'0
     sync always
@@ -119412,7 +119256,7 @@ module \ls180
       update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0]
   end
   attribute \src "ls180.v:2708.32-2708.66"
-  process $proc$ls180.v:2708$3691
+  process $proc$ls180.v:2708$3679
     assign { } { }
     assign $1\builder_multiregimpl2_regs1[0:0] 1'0
     sync always
@@ -119420,7 +119264,7 @@ module \ls180
       update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0]
   end
   attribute \src "ls180.v:2709.32-2709.66"
-  process $proc$ls180.v:2709$3692
+  process $proc$ls180.v:2709$3680
     assign { } { }
     assign $1\builder_multiregimpl3_regs0[0:0] 1'0
     sync always
@@ -119428,7 +119272,7 @@ module \ls180
       update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0]
   end
   attribute \src "ls180.v:2710.32-2710.66"
-  process $proc$ls180.v:2710$3693
+  process $proc$ls180.v:2710$3681
     assign { } { }
     assign $1\builder_multiregimpl3_regs1[0:0] 1'0
     sync always
@@ -119436,7 +119280,7 @@ module \ls180
       update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0]
   end
   attribute \src "ls180.v:2711.32-2711.66"
-  process $proc$ls180.v:2711$3694
+  process $proc$ls180.v:2711$3682
     assign { } { }
     assign $1\builder_multiregimpl4_regs0[0:0] 1'0
     sync always
@@ -119444,7 +119288,7 @@ module \ls180
       update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0]
   end
   attribute \src "ls180.v:2712.32-2712.66"
-  process $proc$ls180.v:2712$3695
+  process $proc$ls180.v:2712$3683
     assign { } { }
     assign $1\builder_multiregimpl4_regs1[0:0] 1'0
     sync always
@@ -119452,7 +119296,7 @@ module \ls180
       update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0]
   end
   attribute \src "ls180.v:2713.32-2713.66"
-  process $proc$ls180.v:2713$3696
+  process $proc$ls180.v:2713$3684
     assign { } { }
     assign $1\builder_multiregimpl5_regs0[0:0] 1'0
     sync always
@@ -119460,7 +119304,7 @@ module \ls180
       update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0]
   end
   attribute \src "ls180.v:2714.32-2714.66"
-  process $proc$ls180.v:2714$3697
+  process $proc$ls180.v:2714$3685
     assign { } { }
     assign $1\builder_multiregimpl5_regs1[0:0] 1'0
     sync always
@@ -119468,7 +119312,7 @@ module \ls180
       update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0]
   end
   attribute \src "ls180.v:2715.32-2715.66"
-  process $proc$ls180.v:2715$3698
+  process $proc$ls180.v:2715$3686
     assign { } { }
     assign $1\builder_multiregimpl6_regs0[0:0] 1'0
     sync always
@@ -119476,7 +119320,7 @@ module \ls180
       update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0]
   end
   attribute \src "ls180.v:2716.32-2716.66"
-  process $proc$ls180.v:2716$3699
+  process $proc$ls180.v:2716$3687
     assign { } { }
     assign $1\builder_multiregimpl6_regs1[0:0] 1'0
     sync always
@@ -119484,7 +119328,7 @@ module \ls180
       update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0]
   end
   attribute \src "ls180.v:2717.32-2717.66"
-  process $proc$ls180.v:2717$3700
+  process $proc$ls180.v:2717$3688
     assign { } { }
     assign $1\builder_multiregimpl7_regs0[0:0] 1'0
     sync always
@@ -119492,7 +119336,7 @@ module \ls180
       update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0]
   end
   attribute \src "ls180.v:2718.32-2718.66"
-  process $proc$ls180.v:2718$3701
+  process $proc$ls180.v:2718$3689
     assign { } { }
     assign $1\builder_multiregimpl7_regs1[0:0] 1'0
     sync always
@@ -119500,7 +119344,7 @@ module \ls180
       update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0]
   end
   attribute \src "ls180.v:2719.32-2719.66"
-  process $proc$ls180.v:2719$3702
+  process $proc$ls180.v:2719$3690
     assign { } { }
     assign $1\builder_multiregimpl8_regs0[0:0] 1'0
     sync always
@@ -119508,7 +119352,7 @@ module \ls180
       update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0]
   end
   attribute \src "ls180.v:272.5-272.36"
-  process $proc$ls180.v:272$2849
+  process $proc$ls180.v:272$2837
     assign { } { }
     assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1
     sync always
@@ -119516,7 +119360,7 @@ module \ls180
       update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0]
   end
   attribute \src "ls180.v:2720.32-2720.66"
-  process $proc$ls180.v:2720$3703
+  process $proc$ls180.v:2720$3691
     assign { } { }
     assign $1\builder_multiregimpl8_regs1[0:0] 1'0
     sync always
@@ -119524,7 +119368,7 @@ module \ls180
       update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0]
   end
   attribute \src "ls180.v:2721.32-2721.66"
-  process $proc$ls180.v:2721$3704
+  process $proc$ls180.v:2721$3692
     assign { } { }
     assign $1\builder_multiregimpl9_regs0[0:0] 1'0
     sync always
@@ -119532,7 +119376,7 @@ module \ls180
       update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0]
   end
   attribute \src "ls180.v:2722.32-2722.66"
-  process $proc$ls180.v:2722$3705
+  process $proc$ls180.v:2722$3693
     assign { } { }
     assign $1\builder_multiregimpl9_regs1[0:0] 1'0
     sync always
@@ -119540,7 +119384,7 @@ module \ls180
       update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0]
   end
   attribute \src "ls180.v:2723.32-2723.67"
-  process $proc$ls180.v:2723$3706
+  process $proc$ls180.v:2723$3694
     assign { } { }
     assign $1\builder_multiregimpl10_regs0[0:0] 1'0
     sync always
@@ -119548,7 +119392,7 @@ module \ls180
       update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0]
   end
   attribute \src "ls180.v:2724.32-2724.67"
-  process $proc$ls180.v:2724$3707
+  process $proc$ls180.v:2724$3695
     assign { } { }
     assign $1\builder_multiregimpl10_regs1[0:0] 1'0
     sync always
@@ -119556,7 +119400,7 @@ module \ls180
       update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0]
   end
   attribute \src "ls180.v:2725.32-2725.67"
-  process $proc$ls180.v:2725$3708
+  process $proc$ls180.v:2725$3696
     assign { } { }
     assign $1\builder_multiregimpl11_regs0[0:0] 1'0
     sync always
@@ -119564,7 +119408,7 @@ module \ls180
       update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0]
   end
   attribute \src "ls180.v:2726.32-2726.67"
-  process $proc$ls180.v:2726$3709
+  process $proc$ls180.v:2726$3697
     assign { } { }
     assign $1\builder_multiregimpl11_regs1[0:0] 1'0
     sync always
@@ -119572,7 +119416,7 @@ module \ls180
       update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0]
   end
   attribute \src "ls180.v:2727.32-2727.67"
-  process $proc$ls180.v:2727$3710
+  process $proc$ls180.v:2727$3698
     assign { } { }
     assign $1\builder_multiregimpl12_regs0[0:0] 1'0
     sync always
@@ -119580,7 +119424,7 @@ module \ls180
       update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0]
   end
   attribute \src "ls180.v:2728.32-2728.67"
-  process $proc$ls180.v:2728$3711
+  process $proc$ls180.v:2728$3699
     assign { } { }
     assign $1\builder_multiregimpl12_regs1[0:0] 1'0
     sync always
@@ -119588,7 +119432,7 @@ module \ls180
       update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0]
   end
   attribute \src "ls180.v:2729.32-2729.67"
-  process $proc$ls180.v:2729$3712
+  process $proc$ls180.v:2729$3700
     assign { } { }
     assign $1\builder_multiregimpl13_regs0[0:0] 1'0
     sync always
@@ -119596,7 +119440,7 @@ module \ls180
       update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0]
   end
   attribute \src "ls180.v:273.5-273.35"
-  process $proc$ls180.v:273$2850
+  process $proc$ls180.v:273$2838
     assign { } { }
     assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1
     sync always
@@ -119604,7 +119448,7 @@ module \ls180
       update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0]
   end
   attribute \src "ls180.v:2730.32-2730.67"
-  process $proc$ls180.v:2730$3713
+  process $proc$ls180.v:2730$3701
     assign { } { }
     assign $1\builder_multiregimpl13_regs1[0:0] 1'0
     sync always
@@ -119612,7 +119456,7 @@ module \ls180
       update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0]
   end
   attribute \src "ls180.v:2731.32-2731.67"
-  process $proc$ls180.v:2731$3714
+  process $proc$ls180.v:2731$3702
     assign { } { }
     assign $1\builder_multiregimpl14_regs0[0:0] 1'0
     sync always
@@ -119620,7 +119464,7 @@ module \ls180
       update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0]
   end
   attribute \src "ls180.v:2732.32-2732.67"
-  process $proc$ls180.v:2732$3715
+  process $proc$ls180.v:2732$3703
     assign { } { }
     assign $1\builder_multiregimpl14_regs1[0:0] 1'0
     sync always
@@ -119628,7 +119472,7 @@ module \ls180
       update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0]
   end
   attribute \src "ls180.v:2733.32-2733.67"
-  process $proc$ls180.v:2733$3716
+  process $proc$ls180.v:2733$3704
     assign { } { }
     assign $1\builder_multiregimpl15_regs0[0:0] 1'0
     sync always
@@ -119636,7 +119480,7 @@ module \ls180
       update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0]
   end
   attribute \src "ls180.v:2734.32-2734.67"
-  process $proc$ls180.v:2734$3717
+  process $proc$ls180.v:2734$3705
     assign { } { }
     assign $1\builder_multiregimpl15_regs1[0:0] 1'0
     sync always
@@ -119644,7 +119488,7 @@ module \ls180
       update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0]
   end
   attribute \src "ls180.v:2735.32-2735.67"
-  process $proc$ls180.v:2735$3718
+  process $proc$ls180.v:2735$3706
     assign { } { }
     assign $1\builder_multiregimpl16_regs0[0:0] 1'0
     sync always
@@ -119652,7 +119496,7 @@ module \ls180
       update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0]
   end
   attribute \src "ls180.v:2736.32-2736.67"
-  process $proc$ls180.v:2736$3719
+  process $proc$ls180.v:2736$3707
     assign { } { }
     assign $1\builder_multiregimpl16_regs1[0:0] 1'0
     sync always
@@ -119660,7 +119504,7 @@ module \ls180
       update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0]
   end
   attribute \src "ls180.v:274.5-274.36"
-  process $proc$ls180.v:274$2851
+  process $proc$ls180.v:274$2839
     assign { } { }
     assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1
     sync always
@@ -119668,7 +119512,7 @@ module \ls180
       update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0]
   end
   attribute \src "ls180.v:275.5-275.35"
-  process $proc$ls180.v:275$2852
+  process $proc$ls180.v:275$2840
     assign { } { }
     assign $1\main_sdram_inti_p0_we_n[0:0] 1'1
     sync always
@@ -119703,7 +119547,7 @@ module \ls180
       update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0]
   end
   attribute \src "ls180.v:279.5-279.36"
-  process $proc$ls180.v:279$2853
+  process $proc$ls180.v:279$2841
     assign { } { }
     assign $0\main_sdram_inti_p0_act_n[0:0] 1'1
     sync always
@@ -119722,13 +119566,13 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign { } { }
     assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
-    assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
-    assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0
     assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0
     assign $0\main_libresocsim_converter0_skip[0:0] 1'0
+    assign { } { }
+    assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
     assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
+    assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0
     assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
     assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
     assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
@@ -119816,7 +119660,7 @@ module \ls180
       update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0]
   end
   attribute \src "ls180.v:284.12-284.45"
-  process $proc$ls180.v:284$2854
+  process $proc$ls180.v:284$2842
     assign { } { }
     assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
     sync always
@@ -119824,7 +119668,7 @@ module \ls180
       update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0]
   end
   attribute \src "ls180.v:285.5-285.43"
-  process $proc$ls180.v:285$2855
+  process $proc$ls180.v:285$2843
     assign { } { }
     assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0
     sync always
@@ -119843,16 +119687,16 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0
     assign $0\main_libresocsim_converter1_skip[0:0] 1'0
     assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
+    assign { } { }
+    assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
     assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0
+    assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0
     assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000
     assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0
     assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
     assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
-    assign { } { }
-    assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
     assign $0\builder_converter1_next_state[0:0] \builder_converter1_state
     attribute \src "ls180.v:2862.2-2895.9"
     switch \builder_converter1_state
@@ -119951,13 +119795,13 @@ module \ls180
     assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
     assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
     assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000
+    assign { } { }
     assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0
+    assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
     assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0
+    assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0
     assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0
     assign $0\main_libresocsim_converter2_skip[0:0] 1'0
-    assign { } { }
-    assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
-    assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0
     assign $0\builder_converter2_next_state[0:0] \builder_converter2_state
     attribute \src "ls180.v:2922.2-2955.9"
     switch \builder_converter2_state
@@ -120050,7 +119894,7 @@ module \ls180
       update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0]
   end
   attribute \src "ls180.v:300.12-300.46"
-  process $proc$ls180.v:300$2856
+  process $proc$ls180.v:300$2844
     assign { } { }
     assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000
     sync always
@@ -120058,7 +119902,7 @@ module \ls180
       update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0]
   end
   attribute \src "ls180.v:301.5-301.44"
-  process $proc$ls180.v:301$2857
+  process $proc$ls180.v:301$2845
     assign { } { }
     assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0
     sync always
@@ -120163,7 +120007,7 @@ module \ls180
       update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0]
   end
   attribute \src "ls180.v:302.12-302.48"
-  process $proc$ls180.v:302$2858
+  process $proc$ls180.v:302$2846
     assign { } { }
     assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000
     sync always
@@ -120171,7 +120015,7 @@ module \ls180
       update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0]
   end
   attribute \src "ls180.v:303.11-303.43"
-  process $proc$ls180.v:303$2859
+  process $proc$ls180.v:303$2847
     assign { } { }
     assign $1\main_sdram_master_p0_bank[1:0] 2'00
     sync always
@@ -120179,7 +120023,7 @@ module \ls180
       update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0]
   end
   attribute \src "ls180.v:304.5-304.38"
-  process $proc$ls180.v:304$2860
+  process $proc$ls180.v:304$2848
     assign { } { }
     assign $1\main_sdram_master_p0_cas_n[0:0] 1'1
     sync always
@@ -120187,7 +120031,7 @@ module \ls180
       update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0]
   end
   attribute \src "ls180.v:305.5-305.37"
-  process $proc$ls180.v:305$2861
+  process $proc$ls180.v:305$2849
     assign { } { }
     assign $1\main_sdram_master_p0_cs_n[0:0] 1'1
     sync always
@@ -120195,7 +120039,7 @@ module \ls180
       update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0]
   end
   attribute \src "ls180.v:306.5-306.38"
-  process $proc$ls180.v:306$2862
+  process $proc$ls180.v:306$2850
     assign { } { }
     assign $1\main_sdram_master_p0_ras_n[0:0] 1'1
     sync always
@@ -120203,7 +120047,7 @@ module \ls180
       update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0]
   end
   attribute \src "ls180.v:307.5-307.37"
-  process $proc$ls180.v:307$2863
+  process $proc$ls180.v:307$2851
     assign { } { }
     assign $1\main_sdram_master_p0_we_n[0:0] 1'1
     sync always
@@ -120242,7 +120086,7 @@ module \ls180
       update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0]
   end
   attribute \src "ls180.v:308.5-308.36"
-  process $proc$ls180.v:308$2864
+  process $proc$ls180.v:308$2852
     assign { } { }
     assign $1\main_sdram_master_p0_cke[0:0] 1'0
     sync always
@@ -120250,7 +120094,7 @@ module \ls180
       update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0]
   end
   attribute \src "ls180.v:309.5-309.36"
-  process $proc$ls180.v:309$2865
+  process $proc$ls180.v:309$2853
     assign { } { }
     assign $1\main_sdram_master_p0_odt[0:0] 1'0
     sync always
@@ -120258,7 +120102,7 @@ module \ls180
       update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0]
   end
   attribute \src "ls180.v:310.5-310.40"
-  process $proc$ls180.v:310$2866
+  process $proc$ls180.v:310$2854
     assign { } { }
     assign $1\main_sdram_master_p0_reset_n[0:0] 1'0
     sync always
@@ -120266,7 +120110,7 @@ module \ls180
       update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0]
   end
   attribute \src "ls180.v:311.5-311.38"
-  process $proc$ls180.v:311$2867
+  process $proc$ls180.v:311$2855
     assign { } { }
     assign $1\main_sdram_master_p0_act_n[0:0] 1'1
     sync always
@@ -120274,7 +120118,7 @@ module \ls180
       update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0]
   end
   attribute \src "ls180.v:312.12-312.47"
-  process $proc$ls180.v:312$2868
+  process $proc$ls180.v:312$2856
     assign { } { }
     assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
     sync always
@@ -120282,7 +120126,7 @@ module \ls180
       update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0]
   end
   attribute \src "ls180.v:313.5-313.42"
-  process $proc$ls180.v:313$2869
+  process $proc$ls180.v:313$2857
     assign { } { }
     assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0
     sync always
@@ -120348,7 +120192,7 @@ module \ls180
       update \builder_refresher_next_state $0\builder_refresher_next_state[1:0]
   end
   attribute \src "ls180.v:314.11-314.50"
-  process $proc$ls180.v:314$2870
+  process $proc$ls180.v:314$2858
     assign { } { }
     assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00
     sync always
@@ -120356,7 +120200,7 @@ module \ls180
       update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0]
   end
   attribute \src "ls180.v:315.5-315.42"
-  process $proc$ls180.v:315$2871
+  process $proc$ls180.v:315$2859
     assign { } { }
     assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0
     sync always
@@ -120416,7 +120260,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
   end
   attribute \src "ls180.v:322.11-322.36"
-  process $proc$ls180.v:322$2872
+  process $proc$ls180.v:322$2860
     assign { } { }
     assign $1\main_sdram_storage[3:0] 4'0001
     sync always
@@ -120441,12 +120285,12 @@ module \ls180
     assign { } { }
     assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
     assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
-    assign { } { }
     assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
     assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
     assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0
     assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0
     assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
+    assign { } { }
     assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
     assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
     assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
@@ -120601,7 +120445,7 @@ module \ls180
       update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0]
   end
   attribute \src "ls180.v:323.5-323.25"
-  process $proc$ls180.v:323$2873
+  process $proc$ls180.v:323$2861
     assign { } { }
     assign $1\main_sdram_re[0:0] 1'0
     sync always
@@ -120609,7 +120453,7 @@ module \ls180
       update \main_sdram_re $1\main_sdram_re[0:0]
   end
   attribute \src "ls180.v:324.11-324.44"
-  process $proc$ls180.v:324$2874
+  process $proc$ls180.v:324$2862
     assign { } { }
     assign $1\main_sdram_command_storage[5:0] 6'000000
     sync always
@@ -120617,7 +120461,7 @@ module \ls180
       update \main_sdram_command_storage $1\main_sdram_command_storage[5:0]
   end
   attribute \src "ls180.v:325.5-325.33"
-  process $proc$ls180.v:325$2875
+  process $proc$ls180.v:325$2863
     assign { } { }
     assign $1\main_sdram_command_re[0:0] 1'0
     sync always
@@ -120625,7 +120469,7 @@ module \ls180
       update \main_sdram_command_re $1\main_sdram_command_re[0:0]
   end
   attribute \src "ls180.v:329.5-329.38"
-  process $proc$ls180.v:329$2876
+  process $proc$ls180.v:329$2864
     assign { } { }
     assign $0\main_sdram_command_issue_w[0:0] 1'0
     sync always
@@ -120633,7 +120477,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:330.12-330.46"
-  process $proc$ls180.v:330$2877
+  process $proc$ls180.v:330$2865
     assign { } { }
     assign $1\main_sdram_address_storage[12:0] 13'0000000000000
     sync always
@@ -120641,7 +120485,7 @@ module \ls180
       update \main_sdram_address_storage $1\main_sdram_address_storage[12:0]
   end
   attribute \src "ls180.v:331.5-331.33"
-  process $proc$ls180.v:331$2878
+  process $proc$ls180.v:331$2866
     assign { } { }
     assign $1\main_sdram_address_re[0:0] 1'0
     sync always
@@ -120649,7 +120493,7 @@ module \ls180
       update \main_sdram_address_re $1\main_sdram_address_re[0:0]
   end
   attribute \src "ls180.v:332.11-332.45"
-  process $proc$ls180.v:332$2879
+  process $proc$ls180.v:332$2867
     assign { } { }
     assign $1\main_sdram_baddress_storage[1:0] 2'00
     sync always
@@ -120657,7 +120501,7 @@ module \ls180
       update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0]
   end
   attribute \src "ls180.v:333.5-333.34"
-  process $proc$ls180.v:333$2880
+  process $proc$ls180.v:333$2868
     assign { } { }
     assign $1\main_sdram_baddress_re[0:0] 1'0
     sync always
@@ -120681,7 +120525,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0]
   end
   attribute \src "ls180.v:334.12-334.45"
-  process $proc$ls180.v:334$2881
+  process $proc$ls180.v:334$2869
     assign { } { }
     assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000
     sync always
@@ -120709,7 +120553,7 @@ module \ls180
       update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0]
   end
   attribute \src "ls180.v:335.5-335.32"
-  process $proc$ls180.v:335$2882
+  process $proc$ls180.v:335$2870
     assign { } { }
     assign $1\main_sdram_wrdata_re[0:0] 1'0
     sync always
@@ -120717,7 +120561,7 @@ module \ls180
       update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0]
   end
   attribute \src "ls180.v:336.12-336.37"
-  process $proc$ls180.v:336$2883
+  process $proc$ls180.v:336$2871
     assign { } { }
     assign $1\main_sdram_status[15:0] 16'0000000000000000
     sync always
@@ -120756,15 +120600,15 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign { } { }
     assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0
-    assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
     assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
+    assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
     assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
     assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
     assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
     assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
     assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
+    assign { } { }
     assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
     assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0
     assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0
@@ -120992,13 +120836,13 @@ module \ls180
     assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
     assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
     assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
+    assign { } { }
     assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
     assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
     assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
     assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
     assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
     assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
-    assign { } { }
     assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state
     attribute \src "ls180.v:3556.2-3632.9"
     switch \builder_bankmachine2_state
@@ -121183,7 +121027,7 @@ module \ls180
       update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0]
   end
   attribute \src "ls180.v:366.12-366.46"
-  process $proc$ls180.v:366$2884
+  process $proc$ls180.v:366$2872
     assign { } { }
     assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000
     sync always
@@ -121191,7 +121035,7 @@ module \ls180
       update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0]
   end
   attribute \src "ls180.v:367.11-367.47"
-  process $proc$ls180.v:367$2885
+  process $proc$ls180.v:367$2873
     assign { } { }
     assign $1\main_sdram_interface_wdata_we[1:0] 2'00
     sync always
@@ -121215,7 +121059,7 @@ module \ls180
       update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
   end
   attribute \src "ls180.v:369.12-369.45"
-  process $proc$ls180.v:369$2886
+  process $proc$ls180.v:369$2874
     assign { } { }
     assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000
     sync always
@@ -121239,8 +121083,8 @@ module \ls180
     assign { } { }
     assign { } { }
     assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
-    assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0
     assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0
+    assign { } { }
     assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0
     assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
     assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
@@ -121249,7 +121093,7 @@ module \ls180
     assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
     assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
     assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
-    assign { } { }
+    assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0
     assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
     assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
     assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state
@@ -121400,7 +121244,7 @@ module \ls180
       update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0]
   end
   attribute \src "ls180.v:370.11-370.40"
-  process $proc$ls180.v:370$2887
+  process $proc$ls180.v:370$2875
     assign { } { }
     assign $1\main_sdram_dfi_p0_bank[1:0] 2'00
     sync always
@@ -121408,7 +121252,7 @@ module \ls180
       update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0]
   end
   attribute \src "ls180.v:371.5-371.35"
-  process $proc$ls180.v:371$2888
+  process $proc$ls180.v:371$2876
     assign { } { }
     assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1
     sync always
@@ -121416,7 +121260,7 @@ module \ls180
       update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0]
   end
   attribute \src "ls180.v:372.5-372.34"
-  process $proc$ls180.v:372$2889
+  process $proc$ls180.v:372$2877
     assign { } { }
     assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1
     sync always
@@ -121424,7 +121268,7 @@ module \ls180
       update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0]
   end
   attribute \src "ls180.v:373.5-373.35"
-  process $proc$ls180.v:373$2890
+  process $proc$ls180.v:373$2878
     assign { } { }
     assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1
     sync always
@@ -121432,7 +121276,7 @@ module \ls180
       update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0]
   end
   attribute \src "ls180.v:374.5-374.34"
-  process $proc$ls180.v:374$2891
+  process $proc$ls180.v:374$2879
     assign { } { }
     assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1
     sync always
@@ -121440,7 +121284,7 @@ module \ls180
       update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0]
   end
   attribute \src "ls180.v:378.5-378.35"
-  process $proc$ls180.v:378$2892
+  process $proc$ls180.v:378$2880
     assign { } { }
     assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1
     sync always
@@ -121448,7 +121292,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:380.5-380.39"
-  process $proc$ls180.v:380$2893
+  process $proc$ls180.v:380$2881
     assign { } { }
     assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0
     sync always
@@ -121467,7 +121311,7 @@ module \ls180
       update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0]
   end
   attribute \src "ls180.v:382.5-382.39"
-  process $proc$ls180.v:382$2894
+  process $proc$ls180.v:382$2882
     assign { } { }
     assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0
     sync always
@@ -121528,7 +121372,7 @@ module \ls180
       update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0]
   end
   attribute \src "ls180.v:385.5-385.32"
-  process $proc$ls180.v:385$2895
+  process $proc$ls180.v:385$2883
     assign { } { }
     assign $1\main_sdram_cmd_valid[0:0] 1'0
     sync always
@@ -121550,7 +121394,7 @@ module \ls180
       update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0]
   end
   attribute \src "ls180.v:386.5-386.32"
-  process $proc$ls180.v:386$2896
+  process $proc$ls180.v:386$2884
     assign { } { }
     assign $1\main_sdram_cmd_ready[0:0] 1'0
     sync always
@@ -121586,7 +121430,7 @@ module \ls180
       update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0]
   end
   attribute \src "ls180.v:387.5-387.31"
-  process $proc$ls180.v:387$2897
+  process $proc$ls180.v:387$2885
     assign { } { }
     assign $1\main_sdram_cmd_last[0:0] 1'0
     sync always
@@ -121615,7 +121459,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0]
   end
   attribute \src "ls180.v:388.12-388.44"
-  process $proc$ls180.v:388$2898
+  process $proc$ls180.v:388$2886
     assign { } { }
     assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000
     sync always
@@ -121644,7 +121488,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0]
   end
   attribute \src "ls180.v:389.11-389.43"
-  process $proc$ls180.v:389$2899
+  process $proc$ls180.v:389$2887
     assign { } { }
     assign $1\main_sdram_cmd_payload_ba[1:0] 2'00
     sync always
@@ -121673,7 +121517,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0]
   end
   attribute \src "ls180.v:390.5-390.38"
-  process $proc$ls180.v:390$2900
+  process $proc$ls180.v:390$2888
     assign { } { }
     assign $1\main_sdram_cmd_payload_cas[0:0] 1'0
     sync always
@@ -121702,7 +121546,7 @@ module \ls180
       update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0]
   end
   attribute \src "ls180.v:391.5-391.38"
-  process $proc$ls180.v:391$2901
+  process $proc$ls180.v:391$2889
     assign { } { }
     assign $1\main_sdram_cmd_payload_ras[0:0] 1'0
     sync always
@@ -121723,8 +121567,8 @@ module \ls180
     assign { } { }
     assign $0\main_sdram_steerer_sel[1:0] 2'00
     assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0
-    assign $0\main_sdram_en0[0:0] 1'0
     assign { } { }
+    assign $0\main_sdram_en0[0:0] 1'0
     assign $0\main_sdram_en1[0:0] 1'0
     assign $0\main_sdram_choose_req_want_reads[0:0] 1'0
     assign $0\main_sdram_choose_req_want_writes[0:0] 1'0
@@ -121836,7 +121680,7 @@ module \ls180
       update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0]
   end
   attribute \src "ls180.v:392.5-392.37"
-  process $proc$ls180.v:392$2902
+  process $proc$ls180.v:392$2890
     assign { } { }
     assign $1\main_sdram_cmd_payload_we[0:0] 1'0
     sync always
@@ -121844,7 +121688,7 @@ module \ls180
       update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0]
   end
   attribute \src "ls180.v:393.5-393.42"
-  process $proc$ls180.v:393$2903
+  process $proc$ls180.v:393$2891
     assign { } { }
     assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0
     sync always
@@ -121852,7 +121696,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:394.5-394.43"
-  process $proc$ls180.v:394$2904
+  process $proc$ls180.v:394$2892
     assign { } { }
     assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0
     sync always
@@ -121860,7 +121704,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:400.11-400.44"
-  process $proc$ls180.v:400$2905
+  process $proc$ls180.v:400$2893
     assign { } { }
     assign $1\main_sdram_timer_count1[9:0] 10'1100001101
     sync always
@@ -121889,7 +121733,7 @@ module \ls180
       update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0]
   end
   attribute \src "ls180.v:402.5-402.38"
-  process $proc$ls180.v:402$2906
+  process $proc$ls180.v:402$2894
     assign { } { }
     assign $1\main_sdram_postponer_req_o[0:0] 1'0
     sync always
@@ -121897,7 +121741,7 @@ module \ls180
       update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0]
   end
   attribute \src "ls180.v:403.5-403.38"
-  process $proc$ls180.v:403$2907
+  process $proc$ls180.v:403$2895
     assign { } { }
     assign $1\main_sdram_postponer_count[0:0] 1'0
     sync always
@@ -121922,7 +121766,7 @@ module \ls180
       update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0]
   end
   attribute \src "ls180.v:404.5-404.39"
-  process $proc$ls180.v:404$2908
+  process $proc$ls180.v:404$2896
     assign { } { }
     assign $1\main_sdram_sequencer_start0[0:0] 1'0
     sync always
@@ -121941,16 +121785,16 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0
     assign $0\main_litedram_wb_we[0:0] 1'0
     assign $0\main_converter_skip[0:0] 1'0
     assign $0\main_wb_sdram_ack[0:0] 1'0
+    assign { } { }
+    assign $0\main_converter_counter_converter_next_value[0:0] 1'0
+    assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0
     assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000
     assign $0\main_litedram_wb_sel[1:0] 2'00
     assign $0\main_litedram_wb_cyc[0:0] 1'0
-    assign { } { }
     assign $0\main_litedram_wb_stb[0:0] 1'0
-    assign $0\main_converter_counter_converter_next_value[0:0] 1'0
     assign $0\builder_converter_next_state[0:0] \builder_converter_state
     attribute \src "ls180.v:4055.2-4088.9"
     switch \builder_converter_state
@@ -122018,7 +121862,7 @@ module \ls180
       update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0]
   end
   attribute \src "ls180.v:407.5-407.38"
-  process $proc$ls180.v:407$2909
+  process $proc$ls180.v:407$2897
     assign { } { }
     assign $1\main_sdram_sequencer_done1[0:0] 1'0
     sync always
@@ -122026,7 +121870,7 @@ module \ls180
       update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0]
   end
   attribute \src "ls180.v:408.11-408.46"
-  process $proc$ls180.v:408$2910
+  process $proc$ls180.v:408$2898
     assign { } { }
     assign $1\main_sdram_sequencer_counter[3:0] 4'0000
     sync always
@@ -122034,7 +121878,7 @@ module \ls180
       update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0]
   end
   attribute \src "ls180.v:409.5-409.38"
-  process $proc$ls180.v:409$2911
+  process $proc$ls180.v:409$2899
     assign { } { }
     assign $1\main_sdram_sequencer_count[0:0] 1'0
     sync always
@@ -122079,7 +121923,7 @@ module \ls180
       update \main_uart_rx_clear $0\main_uart_rx_clear[0:0]
   end
   attribute \src "ls180.v:415.5-415.51"
-  process $proc$ls180.v:415$2912
+  process $proc$ls180.v:415$2900
     assign { } { }
     assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
     sync always
@@ -122096,7 +121940,7 @@ module \ls180
       update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0]
   end
   attribute \src "ls180.v:416.5-416.51"
-  process $proc$ls180.v:416$2913
+  process $proc$ls180.v:416$2901
     assign { } { }
     assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
     sync always
@@ -122120,7 +121964,7 @@ module \ls180
       update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0]
   end
   attribute \src "ls180.v:418.5-418.47"
-  process $proc$ls180.v:418$2914
+  process $proc$ls180.v:418$2902
     assign { } { }
     assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
     sync always
@@ -122128,7 +121972,7 @@ module \ls180
       update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0]
   end
   attribute \src "ls180.v:419.5-419.45"
-  process $proc$ls180.v:419$2915
+  process $proc$ls180.v:419$2903
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
     sync always
@@ -122136,7 +121980,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0]
   end
   attribute \src "ls180.v:420.5-420.45"
-  process $proc$ls180.v:420$2916
+  process $proc$ls180.v:420$2904
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
     sync always
@@ -122160,7 +122004,7 @@ module \ls180
       update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0]
   end
   attribute \src "ls180.v:421.12-421.57"
-  process $proc$ls180.v:421$2917
+  process $proc$ls180.v:421$2905
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
     sync always
@@ -122168,7 +122012,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
   end
   attribute \src "ls180.v:423.5-423.51"
-  process $proc$ls180.v:423$2918
+  process $proc$ls180.v:423$2906
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
     sync always
@@ -122186,15 +122030,15 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign { } { }
     assign $0\main_spimaster25_clk_enable[0:0] 1'0
+    assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
     assign $0\main_spimaster26_cs_enable[0:0] 1'0
+    assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0
     assign $0\main_spimaster28_mosi_latch[0:0] 1'0
     assign $0\main_spimaster2_done[0:0] 1'0
     assign $0\main_spimaster29_miso_latch[0:0] 1'0
     assign $0\main_spimaster3_irq[0:0] 1'0
-    assign { } { }
-    assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
-    assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0
     assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state
     attribute \src "ls180.v:4244.2-4280.9"
     switch \builder_spimaster0_state
@@ -122266,7 +122110,7 @@ module \ls180
       update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0]
   end
   attribute \src "ls180.v:424.5-424.51"
-  process $proc$ls180.v:424$2919
+  process $proc$ls180.v:424$2907
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
     sync always
@@ -122274,7 +122118,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
   end
   attribute \src "ls180.v:425.5-425.50"
-  process $proc$ls180.v:425$2920
+  process $proc$ls180.v:425$2908
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
     sync always
@@ -122282,7 +122126,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
   end
   attribute \src "ls180.v:426.5-426.54"
-  process $proc$ls180.v:426$2921
+  process $proc$ls180.v:426$2909
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
     sync always
@@ -122290,7 +122134,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
   end
   attribute \src "ls180.v:427.5-427.55"
-  process $proc$ls180.v:427$2922
+  process $proc$ls180.v:427$2910
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
     sync always
@@ -122298,7 +122142,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
   end
   attribute \src "ls180.v:428.5-428.56"
-  process $proc$ls180.v:428$2923
+  process $proc$ls180.v:428$2911
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
     sync always
@@ -122306,7 +122150,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
   end
   attribute \src "ls180.v:429.5-429.50"
-  process $proc$ls180.v:429$2924
+  process $proc$ls180.v:429$2912
     assign { } { }
     assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0
     sync always
@@ -122324,15 +122168,15 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign { } { }
+    assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
+    assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0
     assign $0\main_spisdcard_clk_enable[0:0] 1'0
     assign $0\main_spisdcard_cs_enable[0:0] 1'0
     assign $0\main_spisdcard_mosi_latch[0:0] 1'0
-    assign { } { }
     assign $0\main_spisdcard_done0[0:0] 1'0
     assign $0\main_spisdcard_miso_latch[0:0] 1'0
-    assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
     assign $0\main_spisdcard_irq[0:0] 1'0
-    assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0
     assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state
     attribute \src "ls180.v:4303.2-4339.9"
     switch \builder_spimaster1_state
@@ -122404,7 +122248,7 @@ module \ls180
       update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0]
   end
   attribute \src "ls180.v:432.5-432.67"
-  process $proc$ls180.v:432$2925
+  process $proc$ls180.v:432$2913
     assign { } { }
     assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0
     sync always
@@ -122412,7 +122256,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:433.5-433.66"
-  process $proc$ls180.v:433$2926
+  process $proc$ls180.v:433$2914
     assign { } { }
     assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0
     sync always
@@ -122463,14 +122307,14 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
+    assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
+    assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
     assign { } { }
     assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0
     assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
     assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0
     assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
-    assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
-    assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
-    assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
     assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state
     attribute \src "ls180.v:4412.2-4434.9"
     switch \builder_sdphy_sdphyinit_state
@@ -122528,14 +122372,14 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
-    assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
-    assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
-    assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
     assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0
     assign $0\main_sdphy_cmdw_done[0:0] 1'0
     assign { } { }
     assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
+    assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
+    assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
+    assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
+    assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
     assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state
     attribute \src "ls180.v:4446.2-4511.9"
     switch \builder_sdphy_sdphycmdw_state
@@ -122641,7 +122485,7 @@ module \ls180
       update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
   end
   attribute \src "ls180.v:448.11-448.68"
-  process $proc$ls180.v:448$2927
+  process $proc$ls180.v:448$2915
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000
     sync always
@@ -122649,7 +122493,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
   end
   attribute \src "ls180.v:449.5-449.64"
-  process $proc$ls180.v:449$2928
+  process $proc$ls180.v:449$2916
     assign { } { }
     assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0
     sync always
@@ -122657,7 +122501,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:450.11-450.70"
-  process $proc$ls180.v:450$2929
+  process $proc$ls180.v:450$2917
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000
     sync always
@@ -122665,7 +122509,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
   end
   attribute \src "ls180.v:451.11-451.70"
-  process $proc$ls180.v:451$2930
+  process $proc$ls180.v:451$2918
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000
     sync always
@@ -122673,7 +122517,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
   end
   attribute \src "ls180.v:452.11-452.73"
-  process $proc$ls180.v:452$2931
+  process $proc$ls180.v:452$2919
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
     sync always
@@ -122698,6 +122542,12 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0
+    assign $0\main_sdphy_cmdr_source_last[0:0] 1'0
+    assign { } { }
+    assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
+    assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
+    assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000
     assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0
     assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0
     assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0
@@ -122707,13 +122557,7 @@ module \ls180
     assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0
     assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0
     assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0
-    assign { } { }
     assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0
-    assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
-    assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0
-    assign $0\main_sdphy_cmdr_source_last[0:0] 1'0
-    assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
-    assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000
     assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state
     attribute \src "ls180.v:4564.2-4638.9"
     switch \builder_sdphy_sdphycmdr_state
@@ -122857,12 +122701,12 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
     assign { } { }
+    assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
     assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
-    assign $0\main_sdphy_dataw_valid[0:0] 1'0
-    assign $0\main_sdphy_dataw_error[0:0] 1'0
     assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0
+    assign $0\main_sdphy_dataw_error[0:0] 1'0
+    assign $0\main_sdphy_dataw_valid[0:0] 1'0
     assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state
     attribute \src "ls180.v:4681.2-4699.9"
     switch \builder_sdphy_sdphycrcr_state
@@ -122911,15 +122755,15 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
+    assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
+    assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0
     assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0
     assign $0\main_sdphy_dataw_start[0:0] 1'0
     assign { } { }
     assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
     assign $0\main_sdphy_dataw_stop[0:0] 1'0
     assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0
-    assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
-    assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
-    assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0
     assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state
     attribute \src "ls180.v:4712.2-4772.9"
     switch \builder_sdphy_fsm_state
@@ -123029,7 +122873,7 @@ module \ls180
       update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
   end
   attribute \src "ls180.v:473.5-473.59"
-  process $proc$ls180.v:473$2932
+  process $proc$ls180.v:473$2920
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0
     sync always
@@ -123037,7 +122881,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
   end
   attribute \src "ls180.v:475.5-475.59"
-  process $proc$ls180.v:475$2933
+  process $proc$ls180.v:475$2921
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0
     sync always
@@ -123045,7 +122889,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
   end
   attribute \src "ls180.v:476.5-476.58"
-  process $proc$ls180.v:476$2934
+  process $proc$ls180.v:476$2922
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0
     sync always
@@ -123053,7 +122897,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
   end
   attribute \src "ls180.v:477.5-477.64"
-  process $proc$ls180.v:477$2935
+  process $proc$ls180.v:477$2923
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0
     sync always
@@ -123061,7 +122905,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
   end
   attribute \src "ls180.v:478.12-478.74"
-  process $proc$ls180.v:478$2936
+  process $proc$ls180.v:478$2924
     assign { } { }
     assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
     sync always
@@ -123069,7 +122913,7 @@ module \ls180
       update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
   end
   attribute \src "ls180.v:479.12-479.47"
-  process $proc$ls180.v:479$2937
+  process $proc$ls180.v:479$2925
     assign { } { }
     assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000
     sync always
@@ -123077,7 +122921,7 @@ module \ls180
       update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0]
   end
   attribute \src "ls180.v:480.5-480.46"
-  process $proc$ls180.v:480$2938
+  process $proc$ls180.v:480$2926
     assign { } { }
     assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0
     sync always
@@ -123101,21 +122945,21 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdphy_datar_sink_ready[0:0] 1'0
-    assign { } { }
-    assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
     assign $0\main_sdphy_datar_source_valid[0:0] 1'0
-    assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
-    assign $0\main_sdphy_datar_source_last[0:0] 1'0
     assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0
     assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
     assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0
     assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000
+    assign $0\main_sdphy_datar_source_last[0:0] 1'0
     assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000
     assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0
-    assign $0\main_sdphy_datar_stop[0:0] 1'0
     assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
+    assign $0\main_sdphy_datar_stop[0:0] 1'0
     assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0
+    assign $0\main_sdphy_datar_sink_ready[0:0] 1'0
+    assign { } { }
+    assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
+    assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
     assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state
     attribute \src "ls180.v:4824.2-4907.9"
     switch \builder_sdphy_sdphydatar_state
@@ -123268,7 +123112,7 @@ module \ls180
       update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
   end
   attribute \src "ls180.v:482.5-482.44"
-  process $proc$ls180.v:482$2939
+  process $proc$ls180.v:482$2927
     assign { } { }
     assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0
     sync always
@@ -123276,7 +123120,7 @@ module \ls180
       update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0]
   end
   attribute \src "ls180.v:483.5-483.45"
-  process $proc$ls180.v:483$2940
+  process $proc$ls180.v:483$2928
     assign { } { }
     assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0
     sync always
@@ -123284,7 +123128,7 @@ module \ls180
       update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0]
   end
   attribute \src "ls180.v:484.5-484.54"
-  process $proc$ls180.v:484$2941
+  process $proc$ls180.v:484$2929
     assign { } { }
     assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
     sync always
@@ -123292,7 +123136,7 @@ module \ls180
       update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
   end
   attribute \src "ls180.v:486.32-486.76"
-  process $proc$ls180.v:486$2942
+  process $proc$ls180.v:486$2930
     assign { } { }
     assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
     sync always
@@ -123300,7 +123144,7 @@ module \ls180
       update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
   end
   attribute \src "ls180.v:487.11-487.55"
-  process $proc$ls180.v:487$2943
+  process $proc$ls180.v:487$2931
     assign { } { }
     assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000
     sync always
@@ -123308,7 +123152,7 @@ module \ls180
       update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0]
   end
   attribute \src "ls180.v:489.32-489.75"
-  process $proc$ls180.v:489$2944
+  process $proc$ls180.v:489$2932
     assign { } { }
     assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1
     sync always
@@ -123316,7 +123160,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:491.32-491.76"
-  process $proc$ls180.v:491$2945
+  process $proc$ls180.v:491$2933
     assign { } { }
     assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1
     sync always
@@ -123340,7 +123184,7 @@ module \ls180
       update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0]
   end
   attribute \src "ls180.v:497.5-497.51"
-  process $proc$ls180.v:497$2946
+  process $proc$ls180.v:497$2934
     assign { } { }
     assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
     sync always
@@ -123348,7 +123192,7 @@ module \ls180
       update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0]
   end
   attribute \src "ls180.v:498.5-498.51"
-  process $proc$ls180.v:498$2947
+  process $proc$ls180.v:498$2935
     assign { } { }
     assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
     sync always
@@ -123388,7 +123232,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0]
   end
   attribute \src "ls180.v:500.5-500.47"
-  process $proc$ls180.v:500$2948
+  process $proc$ls180.v:500$2936
     assign { } { }
     assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
     sync always
@@ -123412,7 +123256,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0]
   end
   attribute \src "ls180.v:501.5-501.45"
-  process $proc$ls180.v:501$2949
+  process $proc$ls180.v:501$2937
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
     sync always
@@ -123436,7 +123280,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0]
   end
   attribute \src "ls180.v:502.5-502.45"
-  process $proc$ls180.v:502$2950
+  process $proc$ls180.v:502$2938
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0
     sync always
@@ -123460,21 +123304,21 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
+    assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
+    assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
+    assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
+    assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
+    assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
     assign { } { }
     assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000
     assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
     assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0
-    assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
     assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
     assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
     assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0
     assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
     assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000
-    assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
-    assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
-    assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
-    assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
-    assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
     assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state
     attribute \src "ls180.v:5043.2-5104.9"
     switch \builder_sdcore_crcupstreaminserter_state
@@ -123575,7 +123419,7 @@ module \ls180
       update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
   end
   attribute \src "ls180.v:503.12-503.57"
-  process $proc$ls180.v:503$2951
+  process $proc$ls180.v:503$2939
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
     sync always
@@ -123583,7 +123427,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0]
   end
   attribute \src "ls180.v:505.5-505.51"
-  process $proc$ls180.v:505$2952
+  process $proc$ls180.v:505$2940
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
     sync always
@@ -123591,7 +123435,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0]
   end
   attribute \src "ls180.v:506.5-506.51"
-  process $proc$ls180.v:506$2953
+  process $proc$ls180.v:506$2941
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
     sync always
@@ -123599,7 +123443,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0]
   end
   attribute \src "ls180.v:507.5-507.50"
-  process $proc$ls180.v:507$2954
+  process $proc$ls180.v:507$2942
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0
     sync always
@@ -123607,7 +123451,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0]
   end
   attribute \src "ls180.v:508.5-508.54"
-  process $proc$ls180.v:508$2955
+  process $proc$ls180.v:508$2943
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
     sync always
@@ -123615,7 +123459,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
   end
   attribute \src "ls180.v:509.5-509.55"
-  process $proc$ls180.v:509$2956
+  process $proc$ls180.v:509$2944
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
     sync always
@@ -123623,7 +123467,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
   end
   attribute \src "ls180.v:510.5-510.56"
-  process $proc$ls180.v:510$2957
+  process $proc$ls180.v:510$2945
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
     sync always
@@ -123645,7 +123489,7 @@ module \ls180
       update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0]
   end
   attribute \src "ls180.v:511.5-511.50"
-  process $proc$ls180.v:511$2958
+  process $proc$ls180.v:511$2946
     assign { } { }
     assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0
     sync always
@@ -123701,7 +123545,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0]
   end
   attribute \src "ls180.v:514.5-514.67"
-  process $proc$ls180.v:514$2959
+  process $proc$ls180.v:514$2947
     assign { } { }
     assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0
     sync always
@@ -123725,7 +123569,7 @@ module \ls180
       update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0]
   end
   attribute \src "ls180.v:515.5-515.66"
-  process $proc$ls180.v:515$2960
+  process $proc$ls180.v:515$2948
     assign { } { }
     assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0
     sync always
@@ -123867,19 +123711,6 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0
-    assign { } { }
-    assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
-    assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
-    assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0
-    assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000
-    assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
-    assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
-    assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
-    assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0
-    assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
-    assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0
-    assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
     assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0
     assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0
     assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0
@@ -123906,6 +123737,19 @@ module \ls180
     assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0
     assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000
     assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0
+    assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0
+    assign { } { }
+    assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
+    assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
+    assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0
+    assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000
+    assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
+    assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
+    assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
+    assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0
+    assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
+    assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0
+    assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
     assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state
     attribute \src "ls180.v:5249.2-5397.9"
     switch \builder_sdcore_fsm_state
@@ -124177,7 +124021,7 @@ module \ls180
       update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
   end
   attribute \src "ls180.v:530.11-530.68"
-  process $proc$ls180.v:530$2961
+  process $proc$ls180.v:530$2949
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000
     sync always
@@ -124185,7 +124029,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
   end
   attribute \src "ls180.v:531.5-531.64"
-  process $proc$ls180.v:531$2962
+  process $proc$ls180.v:531$2950
     assign { } { }
     assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0
     sync always
@@ -124193,7 +124037,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:532.11-532.70"
-  process $proc$ls180.v:532$2963
+  process $proc$ls180.v:532$2951
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000
     sync always
@@ -124201,7 +124045,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
   end
   attribute \src "ls180.v:533.11-533.70"
-  process $proc$ls180.v:533$2964
+  process $proc$ls180.v:533$2952
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000
     sync always
@@ -124209,7 +124053,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
   end
   attribute \src "ls180.v:534.11-534.73"
-  process $proc$ls180.v:534$2965
+  process $proc$ls180.v:534$2953
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
     sync always
@@ -124242,14 +124086,14 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0
+    assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
+    assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0
+    assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0
     assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
     assign { } { }
     assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
     assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0
-    assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0
-    assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0
-    assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
-    assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0
     assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state
     attribute \src "ls180.v:5469.2-5497.9"
     switch \builder_sdblock2memdma_state
@@ -124304,7 +124148,7 @@ module \ls180
       update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
   end
   attribute \src "ls180.v:55.5-55.42"
-  process $proc$ls180.v:55$2775
+  process $proc$ls180.v:55$2763
     assign { } { }
     assign $1\main_libresocsim_reset_storage[0:0] 1'0
     sync always
@@ -124325,18 +124169,18 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\main_interface1_bus_adr[31:0] 0
+    assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0
+    assign $0\main_interface1_bus_sel[3:0] 4'0000
+    assign $0\main_interface1_bus_cyc[0:0] 1'0
+    assign $0\main_interface1_bus_stb[0:0] 1'0
+    assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0
     assign $0\main_interface1_bus_we[0:0] 1'0
     assign $0\main_sdmem2block_dma_source_last[0:0] 1'0
     assign { } { }
     assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0
     assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0
     assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0
-    assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0
-    assign $0\main_interface1_bus_adr[31:0] 0
-    assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0
-    assign $0\main_interface1_bus_sel[3:0] 4'0000
-    assign $0\main_interface1_bus_cyc[0:0] 1'0
-    assign $0\main_interface1_bus_stb[0:0] 1'0
     assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state
     attribute \src "ls180.v:5532.2-5554.9"
     switch \builder_sdmem2blockdma_fsm_state
@@ -124385,7 +124229,7 @@ module \ls180
       update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
   end
   attribute \src "ls180.v:555.5-555.59"
-  process $proc$ls180.v:555$2966
+  process $proc$ls180.v:555$2954
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0
     sync always
@@ -124401,13 +124245,13 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_sdmem2block_dma_done_status[0:0] 1'0
     assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0
+    assign $0\main_sdmem2block_dma_done_status[0:0] 1'0
     assign { } { }
     assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
     assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0
-    assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0
     assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0
+    assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0
     assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state
     attribute \src "ls180.v:5565.2-5591.9"
     switch \builder_sdmem2blockdma_resetinserter_state
@@ -124459,7 +124303,7 @@ module \ls180
       update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
   end
   attribute \src "ls180.v:557.5-557.59"
-  process $proc$ls180.v:557$2967
+  process $proc$ls180.v:557$2955
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0
     sync always
@@ -124467,7 +124311,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
   end
   attribute \src "ls180.v:558.5-558.58"
-  process $proc$ls180.v:558$2968
+  process $proc$ls180.v:558$2956
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0
     sync always
@@ -124475,7 +124319,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
   end
   attribute \src "ls180.v:559.5-559.64"
-  process $proc$ls180.v:559$2969
+  process $proc$ls180.v:559$2957
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0
     sync always
@@ -124483,7 +124327,7 @@ module \ls180
       update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
   end
   attribute \src "ls180.v:56.5-56.37"
-  process $proc$ls180.v:56$2776
+  process $proc$ls180.v:56$2764
     assign { } { }
     assign $1\main_libresocsim_reset_re[0:0] 1'0
     sync always
@@ -124491,7 +124335,7 @@ module \ls180
       update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0]
   end
   attribute \src "ls180.v:560.12-560.74"
-  process $proc$ls180.v:560$2970
+  process $proc$ls180.v:560$2958
     assign { } { }
     assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
     sync always
@@ -124521,7 +124365,7 @@ module \ls180
       update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0]
   end
   attribute \src "ls180.v:561.12-561.47"
-  process $proc$ls180.v:561$2971
+  process $proc$ls180.v:561$2959
     assign { } { }
     assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000
     sync always
@@ -124529,7 +124373,7 @@ module \ls180
       update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0]
   end
   attribute \src "ls180.v:562.5-562.46"
-  process $proc$ls180.v:562$2972
+  process $proc$ls180.v:562$2960
     assign { } { }
     assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0
     sync always
@@ -124553,7 +124397,7 @@ module \ls180
       update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0]
   end
   attribute \src "ls180.v:564.5-564.44"
-  process $proc$ls180.v:564$2973
+  process $proc$ls180.v:564$2961
     assign { } { }
     assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0
     sync always
@@ -124571,15 +124415,15 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\builder_libresocsim_we_next_value2[0:0] 1'0
+    assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0
+    assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0
+    assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0
     assign { } { }
     assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000
     assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0
     assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000
     assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
-    assign $0\builder_libresocsim_we_next_value2[0:0] 1'0
-    assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0
-    assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0
-    assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0
     assign $0\builder_next_state[1:0] \builder_state
     attribute \src "ls180.v:5660.2-5684.9"
     switch \builder_state
@@ -124623,7 +124467,7 @@ module \ls180
       update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0]
   end
   attribute \src "ls180.v:565.5-565.45"
-  process $proc$ls180.v:565$2974
+  process $proc$ls180.v:565$2962
     assign { } { }
     assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0
     sync always
@@ -124631,7 +124475,7 @@ module \ls180
       update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0]
   end
   attribute \src "ls180.v:566.5-566.54"
-  process $proc$ls180.v:566$2975
+  process $proc$ls180.v:566$2963
     assign { } { }
     assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
     sync always
@@ -124639,7 +124483,7 @@ module \ls180
       update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
   end
   attribute \src "ls180.v:568.32-568.76"
-  process $proc$ls180.v:568$2976
+  process $proc$ls180.v:568$2964
     assign { } { }
     assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
     sync always
@@ -124647,7 +124491,7 @@ module \ls180
       update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0]
   end
   attribute \src "ls180.v:569.11-569.55"
-  process $proc$ls180.v:569$2977
+  process $proc$ls180.v:569$2965
     assign { } { }
     assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000
     sync always
@@ -124655,7 +124499,7 @@ module \ls180
       update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0]
   end
   attribute \src "ls180.v:57.12-57.60"
-  process $proc$ls180.v:57$2777
+  process $proc$ls180.v:57$2765
     assign { } { }
     assign $1\main_libresocsim_scratch_storage[31:0] 305419896
     sync always
@@ -124663,7 +124507,7 @@ module \ls180
       update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0]
   end
   attribute \src "ls180.v:571.32-571.75"
-  process $proc$ls180.v:571$2978
+  process $proc$ls180.v:571$2966
     assign { } { }
     assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1
     sync always
@@ -124683,7 +124527,7 @@ module \ls180
       update \builder_slave_sel $0\builder_slave_sel[4:0]
   end
   attribute \src "ls180.v:573.32-573.76"
-  process $proc$ls180.v:573$2979
+  process $proc$ls180.v:573$2967
     assign { } { }
     assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1
     sync always
@@ -124715,7 +124559,7 @@ module \ls180
       update \builder_error $0\builder_error[0:0]
   end
   attribute \src "ls180.v:579.5-579.51"
-  process $proc$ls180.v:579$2980
+  process $proc$ls180.v:579$2968
     assign { } { }
     assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
     sync always
@@ -124723,7 +124567,7 @@ module \ls180
       update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0]
   end
   attribute \src "ls180.v:58.5-58.39"
-  process $proc$ls180.v:58$2778
+  process $proc$ls180.v:58$2766
     assign { } { }
     assign $1\main_libresocsim_scratch_re[0:0] 1'0
     sync always
@@ -124731,7 +124575,7 @@ module \ls180
       update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0]
   end
   attribute \src "ls180.v:580.5-580.51"
-  process $proc$ls180.v:580$2981
+  process $proc$ls180.v:580$2969
     assign { } { }
     assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
     sync always
@@ -124739,7 +124583,7 @@ module \ls180
       update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0]
   end
   attribute \src "ls180.v:582.5-582.47"
-  process $proc$ls180.v:582$2982
+  process $proc$ls180.v:582$2970
     assign { } { }
     assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
     sync always
@@ -124747,7 +124591,7 @@ module \ls180
       update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0]
   end
   attribute \src "ls180.v:583.5-583.45"
-  process $proc$ls180.v:583$2983
+  process $proc$ls180.v:583$2971
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
     sync always
@@ -124755,7 +124599,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0]
   end
   attribute \src "ls180.v:584.5-584.45"
-  process $proc$ls180.v:584$2984
+  process $proc$ls180.v:584$2972
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0
     sync always
@@ -124763,7 +124607,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0]
   end
   attribute \src "ls180.v:585.12-585.57"
-  process $proc$ls180.v:585$2985
+  process $proc$ls180.v:585$2973
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
     sync always
@@ -124771,7 +124615,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0]
   end
   attribute \src "ls180.v:587.5-587.51"
-  process $proc$ls180.v:587$2986
+  process $proc$ls180.v:587$2974
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
     sync always
@@ -124779,7 +124623,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0]
   end
   attribute \src "ls180.v:588.5-588.51"
-  process $proc$ls180.v:588$2987
+  process $proc$ls180.v:588$2975
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
     sync always
@@ -124787,7 +124631,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0]
   end
   attribute \src "ls180.v:589.5-589.50"
-  process $proc$ls180.v:589$2988
+  process $proc$ls180.v:589$2976
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
     sync always
@@ -124795,7 +124639,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0]
   end
   attribute \src "ls180.v:590.5-590.54"
-  process $proc$ls180.v:590$2989
+  process $proc$ls180.v:590$2977
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
     sync always
@@ -124803,7 +124647,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
   end
   attribute \src "ls180.v:591.5-591.55"
-  process $proc$ls180.v:591$2990
+  process $proc$ls180.v:591$2978
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
     sync always
@@ -124811,7 +124655,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
   end
   attribute \src "ls180.v:592.5-592.56"
-  process $proc$ls180.v:592$2991
+  process $proc$ls180.v:592$2979
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
     sync always
@@ -124819,7 +124663,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
   end
   attribute \src "ls180.v:593.5-593.50"
-  process $proc$ls180.v:593$2992
+  process $proc$ls180.v:593$2980
     assign { } { }
     assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0
     sync always
@@ -124827,7 +124671,7 @@ module \ls180
       update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0]
   end
   attribute \src "ls180.v:596.5-596.67"
-  process $proc$ls180.v:596$2993
+  process $proc$ls180.v:596$2981
     assign { } { }
     assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0
     sync always
@@ -124835,7 +124679,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:597.5-597.66"
-  process $proc$ls180.v:597$2994
+  process $proc$ls180.v:597$2982
     assign { } { }
     assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0
     sync always
@@ -124843,7 +124687,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:612.11-612.68"
-  process $proc$ls180.v:612$2995
+  process $proc$ls180.v:612$2983
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000
     sync always
@@ -124851,7 +124695,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
   end
   attribute \src "ls180.v:613.5-613.64"
-  process $proc$ls180.v:613$2996
+  process $proc$ls180.v:613$2984
     assign { } { }
     assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0
     sync always
@@ -124859,7 +124703,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:614.11-614.70"
-  process $proc$ls180.v:614$2997
+  process $proc$ls180.v:614$2985
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000
     sync always
@@ -124867,7 +124711,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
   end
   attribute \src "ls180.v:615.11-615.70"
-  process $proc$ls180.v:615$2998
+  process $proc$ls180.v:615$2986
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000
     sync always
@@ -124875,7 +124719,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
   end
   attribute \src "ls180.v:616.11-616.73"
-  process $proc$ls180.v:616$2999
+  process $proc$ls180.v:616$2987
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
     sync always
@@ -124897,7 +124741,7 @@ module \ls180
       update \main_spimaster9_start $0\main_spimaster9_start[0:0]
   end
   attribute \src "ls180.v:63.12-63.47"
-  process $proc$ls180.v:63$2779
+  process $proc$ls180.v:63$2767
     assign { } { }
     assign $1\main_libresocsim_bus_errors[31:0] 0
     sync always
@@ -124919,7 +124763,7 @@ module \ls180
       update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0]
   end
   attribute \src "ls180.v:637.5-637.59"
-  process $proc$ls180.v:637$3000
+  process $proc$ls180.v:637$2988
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0
     sync always
@@ -124927,7 +124771,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
   end
   attribute \src "ls180.v:639.5-639.59"
-  process $proc$ls180.v:639$3001
+  process $proc$ls180.v:639$2989
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0
     sync always
@@ -124935,7 +124779,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
   end
   attribute \src "ls180.v:640.5-640.58"
-  process $proc$ls180.v:640$3002
+  process $proc$ls180.v:640$2990
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0
     sync always
@@ -124943,7 +124787,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
   end
   attribute \src "ls180.v:641.5-641.64"
-  process $proc$ls180.v:641$3003
+  process $proc$ls180.v:641$2991
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0
     sync always
@@ -124951,7 +124795,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
   end
   attribute \src "ls180.v:642.12-642.74"
-  process $proc$ls180.v:642$3004
+  process $proc$ls180.v:642$2992
     assign { } { }
     assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
     sync always
@@ -124959,7 +124803,7 @@ module \ls180
       update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
   end
   attribute \src "ls180.v:643.12-643.47"
-  process $proc$ls180.v:643$3005
+  process $proc$ls180.v:643$2993
     assign { } { }
     assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000
     sync always
@@ -124967,7 +124811,7 @@ module \ls180
       update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0]
   end
   attribute \src "ls180.v:644.5-644.46"
-  process $proc$ls180.v:644$3006
+  process $proc$ls180.v:644$2994
     assign { } { }
     assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0
     sync always
@@ -124975,7 +124819,7 @@ module \ls180
       update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0]
   end
   attribute \src "ls180.v:646.5-646.44"
-  process $proc$ls180.v:646$3007
+  process $proc$ls180.v:646$2995
     assign { } { }
     assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0
     sync always
@@ -124983,7 +124827,7 @@ module \ls180
       update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0]
   end
   attribute \src "ls180.v:647.5-647.45"
-  process $proc$ls180.v:647$3008
+  process $proc$ls180.v:647$2996
     assign { } { }
     assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0
     sync always
@@ -124991,7 +124835,7 @@ module \ls180
       update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0]
   end
   attribute \src "ls180.v:648.5-648.54"
-  process $proc$ls180.v:648$3009
+  process $proc$ls180.v:648$2997
     assign { } { }
     assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
     sync always
@@ -124999,7 +124843,7 @@ module \ls180
       update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
   end
   attribute \src "ls180.v:65.12-65.55"
-  process $proc$ls180.v:65$2780
+  process $proc$ls180.v:65$2768
     assign { } { }
     assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000
     sync always
@@ -125007,7 +124851,7 @@ module \ls180
       update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0]
   end
   attribute \src "ls180.v:650.32-650.76"
-  process $proc$ls180.v:650$3010
+  process $proc$ls180.v:650$2998
     assign { } { }
     assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
     sync always
@@ -125015,7 +124859,7 @@ module \ls180
       update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0]
   end
   attribute \src "ls180.v:651.11-651.55"
-  process $proc$ls180.v:651$3011
+  process $proc$ls180.v:651$2999
     assign { } { }
     assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000
     sync always
@@ -125045,7 +124889,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0]
   end
   attribute \src "ls180.v:653.32-653.75"
-  process $proc$ls180.v:653$3012
+  process $proc$ls180.v:653$3000
     assign { } { }
     assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1
     sync always
@@ -125075,7 +124919,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0]
   end
   attribute \src "ls180.v:655.32-655.76"
-  process $proc$ls180.v:655$3013
+  process $proc$ls180.v:655$3001
     assign { } { }
     assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1
     sync always
@@ -125171,7 +125015,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0]
   end
   attribute \src "ls180.v:661.5-661.51"
-  process $proc$ls180.v:661$3014
+  process $proc$ls180.v:661$3002
     assign { } { }
     assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0
     sync always
@@ -125179,7 +125023,7 @@ module \ls180
       update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0]
   end
   attribute \src "ls180.v:662.5-662.51"
-  process $proc$ls180.v:662$3015
+  process $proc$ls180.v:662$3003
     assign { } { }
     assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
     sync always
@@ -125231,7 +125075,7 @@ module \ls180
       update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0]
   end
   attribute \src "ls180.v:664.5-664.47"
-  process $proc$ls180.v:664$3016
+  process $proc$ls180.v:664$3004
     assign { } { }
     assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
     sync always
@@ -125239,7 +125083,7 @@ module \ls180
       update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0]
   end
   attribute \src "ls180.v:665.5-665.45"
-  process $proc$ls180.v:665$3017
+  process $proc$ls180.v:665$3005
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
     sync always
@@ -125269,7 +125113,7 @@ module \ls180
       update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0]
   end
   attribute \src "ls180.v:666.5-666.45"
-  process $proc$ls180.v:666$3018
+  process $proc$ls180.v:666$3006
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0
     sync always
@@ -125277,7 +125121,7 @@ module \ls180
       update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0]
   end
   attribute \src "ls180.v:667.12-667.57"
-  process $proc$ls180.v:667$3019
+  process $proc$ls180.v:667$3007
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
     sync always
@@ -125307,7 +125151,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0]
   end
   attribute \src "ls180.v:669.5-669.51"
-  process $proc$ls180.v:669$3020
+  process $proc$ls180.v:669$3008
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
     sync always
@@ -125337,7 +125181,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0]
   end
   attribute \src "ls180.v:670.5-670.51"
-  process $proc$ls180.v:670$3021
+  process $proc$ls180.v:670$3009
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
     sync always
@@ -125367,7 +125211,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0]
   end
   attribute \src "ls180.v:671.5-671.50"
-  process $proc$ls180.v:671$3022
+  process $proc$ls180.v:671$3010
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0
     sync always
@@ -125375,7 +125219,7 @@ module \ls180
       update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0]
   end
   attribute \src "ls180.v:672.5-672.54"
-  process $proc$ls180.v:672$3023
+  process $proc$ls180.v:672$3011
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
     sync always
@@ -125405,7 +125249,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0]
   end
   attribute \src "ls180.v:673.5-673.55"
-  process $proc$ls180.v:673$3024
+  process $proc$ls180.v:673$3012
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
     sync always
@@ -125413,7 +125257,7 @@ module \ls180
       update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
   end
   attribute \src "ls180.v:674.5-674.56"
-  process $proc$ls180.v:674$3025
+  process $proc$ls180.v:674$3013
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
     sync always
@@ -125443,7 +125287,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0]
   end
   attribute \src "ls180.v:675.5-675.50"
-  process $proc$ls180.v:675$3026
+  process $proc$ls180.v:675$3014
     assign { } { }
     assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
     sync always
@@ -125495,7 +125339,7 @@ module \ls180
       update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0]
   end
   attribute \src "ls180.v:678.5-678.67"
-  process $proc$ls180.v:678$3027
+  process $proc$ls180.v:678$3015
     assign { } { }
     assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0
     sync always
@@ -125503,7 +125347,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:679.5-679.66"
-  process $proc$ls180.v:679$3028
+  process $proc$ls180.v:679$3016
     assign { } { }
     assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0
     sync always
@@ -125736,7 +125580,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0]
   end
   attribute \src "ls180.v:694.11-694.68"
-  process $proc$ls180.v:694$3029
+  process $proc$ls180.v:694$3017
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000
     sync always
@@ -125769,7 +125613,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0]
   end
   attribute \src "ls180.v:695.5-695.64"
-  process $proc$ls180.v:695$3030
+  process $proc$ls180.v:695$3018
     assign { } { }
     assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0
     sync always
@@ -125777,7 +125621,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:696.11-696.70"
-  process $proc$ls180.v:696$3031
+  process $proc$ls180.v:696$3019
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000
     sync always
@@ -125810,7 +125654,7 @@ module \ls180
       update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0]
   end
   attribute \src "ls180.v:697.11-697.70"
-  process $proc$ls180.v:697$3032
+  process $proc$ls180.v:697$3020
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000
     sync always
@@ -125818,7 +125662,7 @@ module \ls180
       update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
   end
   attribute \src "ls180.v:698.11-698.73"
-  process $proc$ls180.v:698$3033
+  process $proc$ls180.v:698$3021
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
     sync always
@@ -126105,7 +125949,7 @@ module \ls180
       update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0]
   end
   attribute \src "ls180.v:719.5-719.59"
-  process $proc$ls180.v:719$3034
+  process $proc$ls180.v:719$3022
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0
     sync always
@@ -126113,7 +125957,7 @@ module \ls180
       update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
   end
   attribute \src "ls180.v:72.5-72.46"
-  process $proc$ls180.v:72$2781
+  process $proc$ls180.v:72$2769
     assign { } { }
     assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0
     sync always
@@ -126155,7 +125999,7 @@ module \ls180
       update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0]
   end
   attribute \src "ls180.v:721.5-721.59"
-  process $proc$ls180.v:721$3035
+  process $proc$ls180.v:721$3023
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0
     sync always
@@ -126163,7 +126007,7 @@ module \ls180
       update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
   end
   attribute \src "ls180.v:722.5-722.58"
-  process $proc$ls180.v:722$3036
+  process $proc$ls180.v:722$3024
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0
     sync always
@@ -126171,7 +126015,7 @@ module \ls180
       update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
   end
   attribute \src "ls180.v:723.5-723.64"
-  process $proc$ls180.v:723$3037
+  process $proc$ls180.v:723$3025
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0
     sync always
@@ -126213,7 +126057,7 @@ module \ls180
       update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0]
   end
   attribute \src "ls180.v:724.12-724.74"
-  process $proc$ls180.v:724$3038
+  process $proc$ls180.v:724$3026
     assign { } { }
     assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
     sync always
@@ -126221,7 +126065,7 @@ module \ls180
       update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
   end
   attribute \src "ls180.v:725.12-725.47"
-  process $proc$ls180.v:725$3039
+  process $proc$ls180.v:725$3027
     assign { } { }
     assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000
     sync always
@@ -126229,7 +126073,7 @@ module \ls180
       update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0]
   end
   attribute \src "ls180.v:726.5-726.46"
-  process $proc$ls180.v:726$3040
+  process $proc$ls180.v:726$3028
     assign { } { }
     assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0
     sync always
@@ -126237,7 +126081,7 @@ module \ls180
       update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0]
   end
   attribute \src "ls180.v:728.5-728.44"
-  process $proc$ls180.v:728$3041
+  process $proc$ls180.v:728$3029
     assign { } { }
     assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0
     sync always
@@ -126245,7 +126089,7 @@ module \ls180
       update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0]
   end
   attribute \src "ls180.v:729.5-729.45"
-  process $proc$ls180.v:729$3042
+  process $proc$ls180.v:729$3030
     assign { } { }
     assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0
     sync always
@@ -126253,7 +126097,7 @@ module \ls180
       update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0]
   end
   attribute \src "ls180.v:730.5-730.54"
-  process $proc$ls180.v:730$3043
+  process $proc$ls180.v:730$3031
     assign { } { }
     assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
     sync always
@@ -126284,7 +126128,7 @@ module \ls180
       update \main_gpio_status $0\main_gpio_status[15:0]
   end
   attribute \src "ls180.v:732.32-732.76"
-  process $proc$ls180.v:732$3044
+  process $proc$ls180.v:732$3032
     assign { } { }
     assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
     sync always
@@ -126292,7 +126136,7 @@ module \ls180
       update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
   end
   attribute \src "ls180.v:733.11-733.55"
-  process $proc$ls180.v:733$3045
+  process $proc$ls180.v:733$3033
     assign { } { }
     assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000
     sync always
@@ -126300,7 +126144,7 @@ module \ls180
       update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0]
   end
   attribute \src "ls180.v:735.32-735.75"
-  process $proc$ls180.v:735$3046
+  process $proc$ls180.v:735$3034
     assign { } { }
     assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1
     sync always
@@ -126426,7 +126270,7 @@ module \ls180
       update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0]
   end
   attribute \src "ls180.v:737.32-737.76"
-  process $proc$ls180.v:737$3047
+  process $proc$ls180.v:737$3035
     assign { } { }
     assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1
     sync always
@@ -126434,7 +126278,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:740.5-740.44"
-  process $proc$ls180.v:740$3048
+  process $proc$ls180.v:740$3036
     assign { } { }
     assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0
     sync always
@@ -126442,7 +126286,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:741.5-741.45"
-  process $proc$ls180.v:741$3049
+  process $proc$ls180.v:741$3037
     assign { } { }
     assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0
     sync always
@@ -126450,7 +126294,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:742.5-742.43"
-  process $proc$ls180.v:742$3050
+  process $proc$ls180.v:742$3038
     assign { } { }
     assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0
     sync always
@@ -126458,23 +126302,23 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:743.5-743.48"
-  process $proc$ls180.v:743$3051
+  process $proc$ls180.v:743$3039
     assign { } { }
     assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0
     sync always
       update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0]
     sync init
   end
-  attribute \src "ls180.v:7431.1-10055.4"
+  attribute \src "ls180.v:7431.1-10043.4"
   process $proc$ls180.v:7431$2374
+    assign $0\spisdcard_clk[0:0] \spisdcard_clk
+    assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
+    assign { } { }
     assign $0\uart_tx[0:0] \uart_tx
     assign $0\pwm[1:0] \pwm
     assign $0\spimaster_clk[0:0] \spimaster_clk
     assign $0\spimaster_mosi[0:0] \spimaster_mosi
     assign { } { }
-    assign $0\spisdcard_clk[0:0] \spisdcard_clk
-    assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
-    assign { } { }
     assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage
     assign { } { }
     assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage
@@ -126879,42 +126723,30 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\main_dummy[35:0] [0] $or$ls180.v:7432$2375_Y
-    assign $0\main_dummy[35:0] [1] $or$ls180.v:7433$2376_Y
-    assign $0\main_dummy[35:0] [2] $or$ls180.v:7434$2377_Y
-    assign $0\main_dummy[35:0] [3] $or$ls180.v:7435$2378_Y
-    assign $0\main_dummy[35:0] [4] $or$ls180.v:7436$2379_Y
-    assign $0\main_dummy[35:0] [5] $or$ls180.v:7437$2380_Y
-    assign $0\main_dummy[35:0] [6] $or$ls180.v:7438$2381_Y
-    assign $0\main_dummy[35:0] [7] $or$ls180.v:7439$2382_Y
-    assign $0\main_dummy[35:0] [8] $or$ls180.v:7440$2383_Y
-    assign $0\main_dummy[35:0] [9] $or$ls180.v:7441$2384_Y
-    assign $0\main_dummy[35:0] [10] $or$ls180.v:7442$2385_Y
-    assign $0\main_dummy[35:0] [11] $or$ls180.v:7443$2386_Y
-    assign $0\main_dummy[35:0] [12] $or$ls180.v:7444$2387_Y
-    assign $0\main_dummy[35:0] [13] $or$ls180.v:7445$2388_Y
-    assign $0\main_dummy[35:0] [14] $or$ls180.v:7446$2389_Y
-    assign $0\main_dummy[35:0] [15] $or$ls180.v:7447$2390_Y
-    assign $0\main_dummy[35:0] [16] $or$ls180.v:7448$2391_Y
-    assign $0\main_dummy[35:0] [17] $or$ls180.v:7449$2392_Y
-    assign $0\main_dummy[35:0] [18] $or$ls180.v:7450$2393_Y
-    assign $0\main_dummy[35:0] [19] $or$ls180.v:7451$2394_Y
-    assign $0\main_dummy[35:0] [20] $or$ls180.v:7452$2395_Y
-    assign $0\main_dummy[35:0] [21] $or$ls180.v:7453$2396_Y
-    assign $0\main_dummy[35:0] [22] $or$ls180.v:7454$2397_Y
-    assign $0\main_dummy[35:0] [23] $or$ls180.v:7455$2398_Y
-    assign $0\main_dummy[35:0] [24] $or$ls180.v:7456$2399_Y
-    assign $0\main_dummy[35:0] [25] $or$ls180.v:7457$2400_Y
-    assign $0\main_dummy[35:0] [26] $or$ls180.v:7458$2401_Y
-    assign $0\main_dummy[35:0] [27] $or$ls180.v:7459$2402_Y
-    assign $0\main_dummy[35:0] [28] $or$ls180.v:7460$2403_Y
-    assign $0\main_dummy[35:0] [29] $or$ls180.v:7461$2404_Y
-    assign $0\main_dummy[35:0] [30] $or$ls180.v:7462$2405_Y
-    assign $0\main_dummy[35:0] [31] $or$ls180.v:7463$2406_Y
-    assign $0\main_dummy[35:0] [32] $or$ls180.v:7464$2407_Y
-    assign $0\main_dummy[35:0] [33] $or$ls180.v:7465$2408_Y
-    assign $0\main_dummy[35:0] [34] $or$ls180.v:7466$2409_Y
-    assign $0\main_dummy[35:0] [35] $or$ls180.v:7467$2410_Y
+    assign $0\main_dummy[23:0] [0] $or$ls180.v:7432$2375_Y
+    assign $0\main_dummy[23:0] [1] $or$ls180.v:7433$2376_Y
+    assign $0\main_dummy[23:0] [2] $or$ls180.v:7434$2377_Y
+    assign $0\main_dummy[23:0] [3] $or$ls180.v:7435$2378_Y
+    assign $0\main_dummy[23:0] [4] $or$ls180.v:7436$2379_Y
+    assign $0\main_dummy[23:0] [5] $or$ls180.v:7437$2380_Y
+    assign $0\main_dummy[23:0] [6] $or$ls180.v:7438$2381_Y
+    assign $0\main_dummy[23:0] [7] $or$ls180.v:7439$2382_Y
+    assign $0\main_dummy[23:0] [8] $or$ls180.v:7440$2383_Y
+    assign $0\main_dummy[23:0] [9] $or$ls180.v:7441$2384_Y
+    assign $0\main_dummy[23:0] [10] $or$ls180.v:7442$2385_Y
+    assign $0\main_dummy[23:0] [11] $or$ls180.v:7443$2386_Y
+    assign $0\main_dummy[23:0] [12] $or$ls180.v:7444$2387_Y
+    assign $0\main_dummy[23:0] [13] $or$ls180.v:7445$2388_Y
+    assign $0\main_dummy[23:0] [14] $or$ls180.v:7446$2389_Y
+    assign $0\main_dummy[23:0] [15] $or$ls180.v:7447$2390_Y
+    assign $0\main_dummy[23:0] [16] $or$ls180.v:7448$2391_Y
+    assign $0\main_dummy[23:0] [17] $or$ls180.v:7449$2392_Y
+    assign $0\main_dummy[23:0] [18] $or$ls180.v:7450$2393_Y
+    assign $0\main_dummy[23:0] [19] $or$ls180.v:7451$2394_Y
+    assign $0\main_dummy[23:0] [20] $or$ls180.v:7452$2395_Y
+    assign $0\main_dummy[23:0] [21] $or$ls180.v:7453$2396_Y
+    assign $0\main_dummy[23:0] [22] $or$ls180.v:7454$2397_Y
+    assign $0\main_dummy[23:0] [23] $or$ls180.v:7455$2398_Y
     assign $0\builder_converter0_state[0:0] \builder_converter0_next_state
     assign $0\builder_converter1_state[0:0] \builder_converter1_next_state
     assign $0\builder_converter2_state[0:0] \builder_converter2_next_state
@@ -126937,14 +126769,14 @@ module \ls180
     assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0
     assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0
     assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1
-    assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7909$2507_Y
-    assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7910$2508_Y
-    assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7911$2509_Y
+    assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7897$2495_Y
+    assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7898$2496_Y
+    assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7899$2497_Y
     assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5
     assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6
     assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state
-    assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7945$2527_Y
-    assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7946$2539_Y
+    assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7933$2515_Y
+    assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7934$2527_Y
     assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0
     assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1
     assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2
@@ -126954,11 +126786,11 @@ module \ls180
     assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx
     assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger
     assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger
-    assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8104$2585_Y
-    assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8113$2588_Y
+    assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8092$2573_Y
+    assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8101$2576_Y
     assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state
-    assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8139$2590_Y
-    assign $0\spimaster_cs_n[0:0] $or$ls180.v:8148$2593_Y
+    assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8127$2578_Y
+    assign $0\spimaster_cs_n[0:0] $or$ls180.v:8136$2581_Y
     assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state
     assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1
     assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1
@@ -127069,154 +126901,154 @@ module \ls180
     assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0
     assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15]
     assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0
-    attribute \src "ls180.v:7468.2-7470.5"
-    switch $or$ls180.v:7468$2411_Y
-      attribute \src "ls180.v:7468.6-7468.94"
+    attribute \src "ls180.v:7456.2-7458.5"
+    switch $or$ls180.v:7456$2399_Y
+      attribute \src "ls180.v:7456.6-7456.94"
       case 1'1
         assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r
       case 
     end
-    attribute \src "ls180.v:7472.2-7474.5"
+    attribute \src "ls180.v:7460.2-7462.5"
     switch \main_libresocsim_converter0_counter_converter0_next_value_ce
-      attribute \src "ls180.v:7472.6-7472.66"
+      attribute \src "ls180.v:7460.6-7460.66"
       case 1'1
         assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value
       case 
     end
-    attribute \src "ls180.v:7475.2-7478.5"
+    attribute \src "ls180.v:7463.2-7466.5"
     switch \main_libresocsim_converter0_reset
-      attribute \src "ls180.v:7475.6-7475.39"
+      attribute \src "ls180.v:7463.6-7463.39"
       case 1'1
         assign $0\main_libresocsim_converter0_counter[0:0] 1'0
         assign $0\builder_converter0_state[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:7479.2-7481.5"
-    switch $or$ls180.v:7479$2412_Y
-      attribute \src "ls180.v:7479.6-7479.94"
+    attribute \src "ls180.v:7467.2-7469.5"
+    switch $or$ls180.v:7467$2400_Y
+      attribute \src "ls180.v:7467.6-7467.94"
       case 1'1
         assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r
       case 
     end
-    attribute \src "ls180.v:7483.2-7485.5"
+    attribute \src "ls180.v:7471.2-7473.5"
     switch \main_libresocsim_converter1_counter_converter1_next_value_ce
-      attribute \src "ls180.v:7483.6-7483.66"
+      attribute \src "ls180.v:7471.6-7471.66"
       case 1'1
         assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value
       case 
     end
-    attribute \src "ls180.v:7486.2-7489.5"
+    attribute \src "ls180.v:7474.2-7477.5"
     switch \main_libresocsim_converter1_reset
-      attribute \src "ls180.v:7486.6-7486.39"
+      attribute \src "ls180.v:7474.6-7474.39"
       case 1'1
         assign $0\main_libresocsim_converter1_counter[0:0] 1'0
         assign $0\builder_converter1_state[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:7490.2-7492.5"
-    switch $or$ls180.v:7490$2413_Y
-      attribute \src "ls180.v:7490.6-7490.94"
+    attribute \src "ls180.v:7478.2-7480.5"
+    switch $or$ls180.v:7478$2401_Y
+      attribute \src "ls180.v:7478.6-7478.94"
       case 1'1
         assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r
       case 
     end
-    attribute \src "ls180.v:7494.2-7496.5"
+    attribute \src "ls180.v:7482.2-7484.5"
     switch \main_libresocsim_converter2_counter_converter2_next_value_ce
-      attribute \src "ls180.v:7494.6-7494.66"
+      attribute \src "ls180.v:7482.6-7482.66"
       case 1'1
         assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value
       case 
     end
-    attribute \src "ls180.v:7497.2-7500.5"
+    attribute \src "ls180.v:7485.2-7488.5"
     switch \main_libresocsim_converter2_reset
-      attribute \src "ls180.v:7497.6-7497.39"
+      attribute \src "ls180.v:7485.6-7485.39"
       case 1'1
         assign $0\main_libresocsim_converter2_counter[0:0] 1'0
         assign $0\builder_converter2_state[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:7501.2-7505.5"
-    switch $ne$ls180.v:7501$2414_Y
-      attribute \src "ls180.v:7501.6-7501.53"
+    attribute \src "ls180.v:7489.2-7493.5"
+    switch $ne$ls180.v:7489$2402_Y
+      attribute \src "ls180.v:7489.6-7489.53"
       case 1'1
-        attribute \src "ls180.v:7502.3-7504.6"
+        attribute \src "ls180.v:7490.3-7492.6"
         switch \main_libresocsim_bus_error
-          attribute \src "ls180.v:7502.7-7502.33"
+          attribute \src "ls180.v:7490.7-7490.33"
           case 1'1
-            assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7503$2415_Y
+            assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7491$2403_Y
           case 
         end
       case 
     end
-    attribute \src "ls180.v:7507.2-7509.5"
-    switch $and$ls180.v:7507$2418_Y
-      attribute \src "ls180.v:7507.6-7507.103"
+    attribute \src "ls180.v:7495.2-7497.5"
+    switch $and$ls180.v:7495$2406_Y
+      attribute \src "ls180.v:7495.6-7495.103"
       case 1'1
         assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:7510.2-7518.5"
+    attribute \src "ls180.v:7498.2-7506.5"
     switch \main_libresocsim_en_storage
-      attribute \src "ls180.v:7510.6-7510.33"
+      attribute \src "ls180.v:7498.6-7498.33"
       case 1'1
-        attribute \src "ls180.v:7511.3-7515.6"
-        switch $eq$ls180.v:7511$2419_Y
-          attribute \src "ls180.v:7511.7-7511.39"
+        attribute \src "ls180.v:7499.3-7503.6"
+        switch $eq$ls180.v:7499$2407_Y
+          attribute \src "ls180.v:7499.7-7499.39"
           case 1'1
             assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage
-          attribute \src "ls180.v:7513.7-7513.11"
+          attribute \src "ls180.v:7501.7-7501.11"
           case 
-            assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7514$2420_Y
+            assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7502$2408_Y
         end
-      attribute \src "ls180.v:7516.6-7516.10"
+      attribute \src "ls180.v:7504.6-7504.10"
       case 
         assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage
     end
-    attribute \src "ls180.v:7519.2-7521.5"
+    attribute \src "ls180.v:7507.2-7509.5"
     switch \main_libresocsim_update_value_re
-      attribute \src "ls180.v:7519.6-7519.38"
+      attribute \src "ls180.v:7507.6-7507.38"
       case 1'1
         assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value
       case 
     end
-    attribute \src "ls180.v:7522.2-7524.5"
+    attribute \src "ls180.v:7510.2-7512.5"
     switch \main_libresocsim_zero_clear
-      attribute \src "ls180.v:7522.6-7522.33"
+      attribute \src "ls180.v:7510.6-7510.33"
       case 1'1
         assign $0\main_libresocsim_zero_pending[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:7526.2-7528.5"
-    switch $and$ls180.v:7526$2422_Y
-      attribute \src "ls180.v:7526.6-7526.76"
+    attribute \src "ls180.v:7514.2-7516.5"
+    switch $and$ls180.v:7514$2410_Y
+      attribute \src "ls180.v:7514.6-7514.76"
       case 1'1
         assign $0\main_libresocsim_zero_pending[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:7531.2-7533.5"
+    attribute \src "ls180.v:7519.2-7521.5"
     switch \main_sdram_inti_p0_rddata_valid
-      attribute \src "ls180.v:7531.6-7531.37"
+      attribute \src "ls180.v:7519.6-7519.37"
       case 1'1
         assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata
       case 
     end
-    attribute \src "ls180.v:7534.2-7538.5"
-    switch $and$ls180.v:7534$2424_Y
-      attribute \src "ls180.v:7534.6-7534.57"
+    attribute \src "ls180.v:7522.2-7526.5"
+    switch $and$ls180.v:7522$2412_Y
+      attribute \src "ls180.v:7522.6-7522.57"
       case 1'1
-        assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7535$2425_Y
-      attribute \src "ls180.v:7536.6-7536.10"
+        assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7523$2413_Y
+      attribute \src "ls180.v:7524.6-7524.10"
       case 
         assign $0\main_sdram_timer_count1[9:0] 10'1100001101
     end
-    attribute \src "ls180.v:7540.2-7546.5"
+    attribute \src "ls180.v:7528.2-7534.5"
     switch \main_sdram_postponer_req_i
-      attribute \src "ls180.v:7540.6-7540.32"
+      attribute \src "ls180.v:7528.6-7528.32"
       case 1'1
-        assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7541$2426_Y
-        attribute \src "ls180.v:7542.3-7545.6"
-        switch $eq$ls180.v:7542$2427_Y
-          attribute \src "ls180.v:7542.7-7542.43"
+        assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7529$2414_Y
+        attribute \src "ls180.v:7530.3-7533.6"
+        switch $eq$ls180.v:7530$2415_Y
+          attribute \src "ls180.v:7530.7-7530.43"
           case 1'1
             assign $0\main_sdram_postponer_count[0:0] 1'0
             assign $0\main_sdram_postponer_req_o[0:0] 1'1
@@ -127224,30 +127056,30 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:7547.2-7555.5"
+    attribute \src "ls180.v:7535.2-7543.5"
     switch \main_sdram_sequencer_start0
-      attribute \src "ls180.v:7547.6-7547.33"
+      attribute \src "ls180.v:7535.6-7535.33"
       case 1'1
         assign $0\main_sdram_sequencer_count[0:0] 1'0
-      attribute \src "ls180.v:7549.6-7549.10"
+      attribute \src "ls180.v:7537.6-7537.10"
       case 
-        attribute \src "ls180.v:7550.3-7554.6"
+        attribute \src "ls180.v:7538.3-7542.6"
         switch \main_sdram_sequencer_done1
-          attribute \src "ls180.v:7550.7-7550.33"
+          attribute \src "ls180.v:7538.7-7538.33"
           case 1'1
-            attribute \src "ls180.v:7551.4-7553.7"
-            switch $ne$ls180.v:7551$2428_Y
-              attribute \src "ls180.v:7551.8-7551.44"
+            attribute \src "ls180.v:7539.4-7541.7"
+            switch $ne$ls180.v:7539$2416_Y
+              attribute \src "ls180.v:7539.8-7539.44"
               case 1'1
-                assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7552$2429_Y
+                assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7540$2417_Y
               case 
             end
           case 
         end
     end
-    attribute \src "ls180.v:7562.2-7568.5"
-    switch $and$ls180.v:7562$2431_Y
-      attribute \src "ls180.v:7562.6-7562.76"
+    attribute \src "ls180.v:7550.2-7556.5"
+    switch $and$ls180.v:7550$2419_Y
+      attribute \src "ls180.v:7550.6-7550.76"
       case 1'1
         assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000
         assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
@@ -127256,9 +127088,9 @@ module \ls180
         assign $0\main_sdram_cmd_payload_we[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:7569.2-7575.5"
-    switch $eq$ls180.v:7569$2432_Y
-      attribute \src "ls180.v:7569.6-7569.44"
+    attribute \src "ls180.v:7557.2-7563.5"
+    switch $eq$ls180.v:7557$2420_Y
+      attribute \src "ls180.v:7557.6-7557.44"
       case 1'1
         assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000
         assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
@@ -127267,9 +127099,9 @@ module \ls180
         assign $0\main_sdram_cmd_payload_we[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:7576.2-7583.5"
-    switch $eq$ls180.v:7576$2433_Y
-      attribute \src "ls180.v:7576.6-7576.44"
+    attribute \src "ls180.v:7564.2-7571.5"
+    switch $eq$ls180.v:7564$2421_Y
+      attribute \src "ls180.v:7564.6-7564.44"
       case 1'1
         assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000
         assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
@@ -127279,83 +127111,83 @@ module \ls180
         assign $0\main_sdram_sequencer_done1[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:7584.2-7594.5"
-    switch $eq$ls180.v:7584$2434_Y
-      attribute \src "ls180.v:7584.6-7584.44"
+    attribute \src "ls180.v:7572.2-7582.5"
+    switch $eq$ls180.v:7572$2422_Y
+      attribute \src "ls180.v:7572.6-7572.44"
       case 1'1
         assign $0\main_sdram_sequencer_counter[3:0] 4'0000
-      attribute \src "ls180.v:7586.6-7586.10"
+      attribute \src "ls180.v:7574.6-7574.10"
       case 
-        attribute \src "ls180.v:7587.3-7593.6"
-        switch $ne$ls180.v:7587$2435_Y
-          attribute \src "ls180.v:7587.7-7587.45"
+        attribute \src "ls180.v:7575.3-7581.6"
+        switch $ne$ls180.v:7575$2423_Y
+          attribute \src "ls180.v:7575.7-7575.45"
           case 1'1
-            assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7588$2436_Y
-          attribute \src "ls180.v:7589.7-7589.11"
+            assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7576$2424_Y
+          attribute \src "ls180.v:7577.7-7577.11"
           case 
-            attribute \src "ls180.v:7590.4-7592.7"
+            attribute \src "ls180.v:7578.4-7580.7"
             switch \main_sdram_sequencer_start1
-              attribute \src "ls180.v:7590.8-7590.35"
+              attribute \src "ls180.v:7578.8-7578.35"
               case 1'1
                 assign $0\main_sdram_sequencer_counter[3:0] 4'0001
               case 
             end
         end
     end
-    attribute \src "ls180.v:7596.2-7603.5"
+    attribute \src "ls180.v:7584.2-7591.5"
     switch \main_sdram_bankmachine0_row_close
-      attribute \src "ls180.v:7596.6-7596.39"
+      attribute \src "ls180.v:7584.6-7584.39"
       case 1'1
         assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0
-      attribute \src "ls180.v:7598.6-7598.10"
+      attribute \src "ls180.v:7586.6-7586.10"
       case 
-        attribute \src "ls180.v:7599.3-7602.6"
+        attribute \src "ls180.v:7587.3-7590.6"
         switch \main_sdram_bankmachine0_row_open
-          attribute \src "ls180.v:7599.7-7599.39"
+          attribute \src "ls180.v:7587.7-7587.39"
           case 1'1
             assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1
             assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
           case 
         end
     end
-    attribute \src "ls180.v:7604.2-7606.5"
-    switch $and$ls180.v:7604$2439_Y
-      attribute \src "ls180.v:7604.6-7604.191"
+    attribute \src "ls180.v:7592.2-7594.5"
+    switch $and$ls180.v:7592$2427_Y
+      attribute \src "ls180.v:7592.6-7592.191"
       case 1'1
-        assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7605$2440_Y
+        assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7593$2428_Y
       case 
     end
-    attribute \src "ls180.v:7607.2-7609.5"
+    attribute \src "ls180.v:7595.2-7597.5"
     switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
-      attribute \src "ls180.v:7607.6-7607.58"
+      attribute \src "ls180.v:7595.6-7595.58"
       case 1'1
-        assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7608$2441_Y
+        assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7596$2429_Y
       case 
     end
-    attribute \src "ls180.v:7610.2-7618.5"
-    switch $and$ls180.v:7610$2444_Y
-      attribute \src "ls180.v:7610.6-7610.191"
+    attribute \src "ls180.v:7598.2-7606.5"
+    switch $and$ls180.v:7598$2432_Y
+      attribute \src "ls180.v:7598.6-7598.191"
       case 1'1
-        attribute \src "ls180.v:7611.3-7613.6"
-        switch $not$ls180.v:7611$2445_Y
-          attribute \src "ls180.v:7611.7-7611.62"
+        attribute \src "ls180.v:7599.3-7601.6"
+        switch $not$ls180.v:7599$2433_Y
+          attribute \src "ls180.v:7599.7-7599.62"
           case 1'1
-            assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7612$2446_Y
+            assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7600$2434_Y
           case 
         end
-      attribute \src "ls180.v:7614.6-7614.10"
+      attribute \src "ls180.v:7602.6-7602.10"
       case 
-        attribute \src "ls180.v:7615.3-7617.6"
+        attribute \src "ls180.v:7603.3-7605.6"
         switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
-          attribute \src "ls180.v:7615.7-7615.59"
+          attribute \src "ls180.v:7603.7-7603.59"
           case 1'1
-            assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7616$2447_Y
+            assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7604$2435_Y
           case 
         end
     end
-    attribute \src "ls180.v:7619.2-7625.5"
-    switch $or$ls180.v:7619$2449_Y
-      attribute \src "ls180.v:7619.6-7619.108"
+    attribute \src "ls180.v:7607.2-7613.5"
+    switch $or$ls180.v:7607$2437_Y
+      attribute \src "ls180.v:7607.6-7607.108"
       case 1'1
         assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid
         assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first
@@ -127364,27 +127196,27 @@ module \ls180
         assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr
       case 
     end
-    attribute \src "ls180.v:7626.2-7640.5"
+    attribute \src "ls180.v:7614.2-7628.5"
     switch \main_sdram_bankmachine0_twtpcon_valid
-      attribute \src "ls180.v:7626.6-7626.43"
+      attribute \src "ls180.v:7614.6-7614.43"
       case 1'1
         assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100
-        attribute \src "ls180.v:7628.3-7632.6"
+        attribute \src "ls180.v:7616.3-7620.6"
         switch 1'0
-          attribute \src "ls180.v:7630.7-7630.11"
+          attribute \src "ls180.v:7618.7-7618.11"
           case 
             assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:7633.6-7633.10"
+      attribute \src "ls180.v:7621.6-7621.10"
       case 
-        attribute \src "ls180.v:7634.3-7639.6"
-        switch $not$ls180.v:7634$2450_Y
-          attribute \src "ls180.v:7634.7-7634.47"
+        attribute \src "ls180.v:7622.3-7627.6"
+        switch $not$ls180.v:7622$2438_Y
+          attribute \src "ls180.v:7622.7-7622.47"
           case 1'1
-            assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7635$2451_Y
-            attribute \src "ls180.v:7636.4-7638.7"
-            switch $eq$ls180.v:7636$2452_Y
-              attribute \src "ls180.v:7636.8-7636.55"
+            assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7623$2439_Y
+            attribute \src "ls180.v:7624.4-7626.7"
+            switch $eq$ls180.v:7624$2440_Y
+              attribute \src "ls180.v:7624.8-7624.55"
               case 1'1
                 assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1
               case 
@@ -127392,60 +127224,60 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7642.2-7649.5"
+    attribute \src "ls180.v:7630.2-7637.5"
     switch \main_sdram_bankmachine1_row_close
-      attribute \src "ls180.v:7642.6-7642.39"
+      attribute \src "ls180.v:7630.6-7630.39"
       case 1'1
         assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0
-      attribute \src "ls180.v:7644.6-7644.10"
+      attribute \src "ls180.v:7632.6-7632.10"
       case 
-        attribute \src "ls180.v:7645.3-7648.6"
+        attribute \src "ls180.v:7633.3-7636.6"
         switch \main_sdram_bankmachine1_row_open
-          attribute \src "ls180.v:7645.7-7645.39"
+          attribute \src "ls180.v:7633.7-7633.39"
           case 1'1
             assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1
             assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
           case 
         end
     end
-    attribute \src "ls180.v:7650.2-7652.5"
-    switch $and$ls180.v:7650$2455_Y
-      attribute \src "ls180.v:7650.6-7650.191"
+    attribute \src "ls180.v:7638.2-7640.5"
+    switch $and$ls180.v:7638$2443_Y
+      attribute \src "ls180.v:7638.6-7638.191"
       case 1'1
-        assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7651$2456_Y
+        assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7639$2444_Y
       case 
     end
-    attribute \src "ls180.v:7653.2-7655.5"
+    attribute \src "ls180.v:7641.2-7643.5"
     switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
-      attribute \src "ls180.v:7653.6-7653.58"
+      attribute \src "ls180.v:7641.6-7641.58"
       case 1'1
-        assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7654$2457_Y
+        assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7642$2445_Y
       case 
     end
-    attribute \src "ls180.v:7656.2-7664.5"
-    switch $and$ls180.v:7656$2460_Y
-      attribute \src "ls180.v:7656.6-7656.191"
+    attribute \src "ls180.v:7644.2-7652.5"
+    switch $and$ls180.v:7644$2448_Y
+      attribute \src "ls180.v:7644.6-7644.191"
       case 1'1
-        attribute \src "ls180.v:7657.3-7659.6"
-        switch $not$ls180.v:7657$2461_Y
-          attribute \src "ls180.v:7657.7-7657.62"
+        attribute \src "ls180.v:7645.3-7647.6"
+        switch $not$ls180.v:7645$2449_Y
+          attribute \src "ls180.v:7645.7-7645.62"
           case 1'1
-            assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7658$2462_Y
+            assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7646$2450_Y
           case 
         end
-      attribute \src "ls180.v:7660.6-7660.10"
+      attribute \src "ls180.v:7648.6-7648.10"
       case 
-        attribute \src "ls180.v:7661.3-7663.6"
+        attribute \src "ls180.v:7649.3-7651.6"
         switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
-          attribute \src "ls180.v:7661.7-7661.59"
+          attribute \src "ls180.v:7649.7-7649.59"
           case 1'1
-            assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7662$2463_Y
+            assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7650$2451_Y
           case 
         end
     end
-    attribute \src "ls180.v:7665.2-7671.5"
-    switch $or$ls180.v:7665$2465_Y
-      attribute \src "ls180.v:7665.6-7665.108"
+    attribute \src "ls180.v:7653.2-7659.5"
+    switch $or$ls180.v:7653$2453_Y
+      attribute \src "ls180.v:7653.6-7653.108"
       case 1'1
         assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid
         assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first
@@ -127454,27 +127286,27 @@ module \ls180
         assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr
       case 
     end
-    attribute \src "ls180.v:7672.2-7686.5"
+    attribute \src "ls180.v:7660.2-7674.5"
     switch \main_sdram_bankmachine1_twtpcon_valid
-      attribute \src "ls180.v:7672.6-7672.43"
+      attribute \src "ls180.v:7660.6-7660.43"
       case 1'1
         assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100
-        attribute \src "ls180.v:7674.3-7678.6"
+        attribute \src "ls180.v:7662.3-7666.6"
         switch 1'0
-          attribute \src "ls180.v:7676.7-7676.11"
+          attribute \src "ls180.v:7664.7-7664.11"
           case 
             assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:7679.6-7679.10"
+      attribute \src "ls180.v:7667.6-7667.10"
       case 
-        attribute \src "ls180.v:7680.3-7685.6"
-        switch $not$ls180.v:7680$2466_Y
-          attribute \src "ls180.v:7680.7-7680.47"
+        attribute \src "ls180.v:7668.3-7673.6"
+        switch $not$ls180.v:7668$2454_Y
+          attribute \src "ls180.v:7668.7-7668.47"
           case 1'1
-            assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7681$2467_Y
-            attribute \src "ls180.v:7682.4-7684.7"
-            switch $eq$ls180.v:7682$2468_Y
-              attribute \src "ls180.v:7682.8-7682.55"
+            assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7669$2455_Y
+            attribute \src "ls180.v:7670.4-7672.7"
+            switch $eq$ls180.v:7670$2456_Y
+              attribute \src "ls180.v:7670.8-7670.55"
               case 1'1
                 assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1
               case 
@@ -127482,60 +127314,60 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7688.2-7695.5"
+    attribute \src "ls180.v:7676.2-7683.5"
     switch \main_sdram_bankmachine2_row_close
-      attribute \src "ls180.v:7688.6-7688.39"
+      attribute \src "ls180.v:7676.6-7676.39"
       case 1'1
         assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0
-      attribute \src "ls180.v:7690.6-7690.10"
+      attribute \src "ls180.v:7678.6-7678.10"
       case 
-        attribute \src "ls180.v:7691.3-7694.6"
+        attribute \src "ls180.v:7679.3-7682.6"
         switch \main_sdram_bankmachine2_row_open
-          attribute \src "ls180.v:7691.7-7691.39"
+          attribute \src "ls180.v:7679.7-7679.39"
           case 1'1
             assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1
             assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
           case 
         end
     end
-    attribute \src "ls180.v:7696.2-7698.5"
-    switch $and$ls180.v:7696$2471_Y
-      attribute \src "ls180.v:7696.6-7696.191"
+    attribute \src "ls180.v:7684.2-7686.5"
+    switch $and$ls180.v:7684$2459_Y
+      attribute \src "ls180.v:7684.6-7684.191"
       case 1'1
-        assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7697$2472_Y
+        assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7685$2460_Y
       case 
     end
-    attribute \src "ls180.v:7699.2-7701.5"
+    attribute \src "ls180.v:7687.2-7689.5"
     switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
-      attribute \src "ls180.v:7699.6-7699.58"
+      attribute \src "ls180.v:7687.6-7687.58"
       case 1'1
-        assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7700$2473_Y
+        assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7688$2461_Y
       case 
     end
-    attribute \src "ls180.v:7702.2-7710.5"
-    switch $and$ls180.v:7702$2476_Y
-      attribute \src "ls180.v:7702.6-7702.191"
+    attribute \src "ls180.v:7690.2-7698.5"
+    switch $and$ls180.v:7690$2464_Y
+      attribute \src "ls180.v:7690.6-7690.191"
       case 1'1
-        attribute \src "ls180.v:7703.3-7705.6"
-        switch $not$ls180.v:7703$2477_Y
-          attribute \src "ls180.v:7703.7-7703.62"
+        attribute \src "ls180.v:7691.3-7693.6"
+        switch $not$ls180.v:7691$2465_Y
+          attribute \src "ls180.v:7691.7-7691.62"
           case 1'1
-            assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7704$2478_Y
+            assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7692$2466_Y
           case 
         end
-      attribute \src "ls180.v:7706.6-7706.10"
+      attribute \src "ls180.v:7694.6-7694.10"
       case 
-        attribute \src "ls180.v:7707.3-7709.6"
+        attribute \src "ls180.v:7695.3-7697.6"
         switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
-          attribute \src "ls180.v:7707.7-7707.59"
+          attribute \src "ls180.v:7695.7-7695.59"
           case 1'1
-            assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7708$2479_Y
+            assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7696$2467_Y
           case 
         end
     end
-    attribute \src "ls180.v:7711.2-7717.5"
-    switch $or$ls180.v:7711$2481_Y
-      attribute \src "ls180.v:7711.6-7711.108"
+    attribute \src "ls180.v:7699.2-7705.5"
+    switch $or$ls180.v:7699$2469_Y
+      attribute \src "ls180.v:7699.6-7699.108"
       case 1'1
         assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid
         assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first
@@ -127544,27 +127376,27 @@ module \ls180
         assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr
       case 
     end
-    attribute \src "ls180.v:7718.2-7732.5"
+    attribute \src "ls180.v:7706.2-7720.5"
     switch \main_sdram_bankmachine2_twtpcon_valid
-      attribute \src "ls180.v:7718.6-7718.43"
+      attribute \src "ls180.v:7706.6-7706.43"
       case 1'1
         assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100
-        attribute \src "ls180.v:7720.3-7724.6"
+        attribute \src "ls180.v:7708.3-7712.6"
         switch 1'0
-          attribute \src "ls180.v:7722.7-7722.11"
+          attribute \src "ls180.v:7710.7-7710.11"
           case 
             assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:7725.6-7725.10"
+      attribute \src "ls180.v:7713.6-7713.10"
       case 
-        attribute \src "ls180.v:7726.3-7731.6"
-        switch $not$ls180.v:7726$2482_Y
-          attribute \src "ls180.v:7726.7-7726.47"
+        attribute \src "ls180.v:7714.3-7719.6"
+        switch $not$ls180.v:7714$2470_Y
+          attribute \src "ls180.v:7714.7-7714.47"
           case 1'1
-            assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7727$2483_Y
-            attribute \src "ls180.v:7728.4-7730.7"
-            switch $eq$ls180.v:7728$2484_Y
-              attribute \src "ls180.v:7728.8-7728.55"
+            assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7715$2471_Y
+            attribute \src "ls180.v:7716.4-7718.7"
+            switch $eq$ls180.v:7716$2472_Y
+              attribute \src "ls180.v:7716.8-7716.55"
               case 1'1
                 assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1
               case 
@@ -127572,60 +127404,60 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7734.2-7741.5"
+    attribute \src "ls180.v:7722.2-7729.5"
     switch \main_sdram_bankmachine3_row_close
-      attribute \src "ls180.v:7734.6-7734.39"
+      attribute \src "ls180.v:7722.6-7722.39"
       case 1'1
         assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0
-      attribute \src "ls180.v:7736.6-7736.10"
+      attribute \src "ls180.v:7724.6-7724.10"
       case 
-        attribute \src "ls180.v:7737.3-7740.6"
+        attribute \src "ls180.v:7725.3-7728.6"
         switch \main_sdram_bankmachine3_row_open
-          attribute \src "ls180.v:7737.7-7737.39"
+          attribute \src "ls180.v:7725.7-7725.39"
           case 1'1
             assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1
             assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
           case 
         end
     end
-    attribute \src "ls180.v:7742.2-7744.5"
-    switch $and$ls180.v:7742$2487_Y
-      attribute \src "ls180.v:7742.6-7742.191"
+    attribute \src "ls180.v:7730.2-7732.5"
+    switch $and$ls180.v:7730$2475_Y
+      attribute \src "ls180.v:7730.6-7730.191"
       case 1'1
-        assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7743$2488_Y
+        assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7731$2476_Y
       case 
     end
-    attribute \src "ls180.v:7745.2-7747.5"
+    attribute \src "ls180.v:7733.2-7735.5"
     switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
-      attribute \src "ls180.v:7745.6-7745.58"
+      attribute \src "ls180.v:7733.6-7733.58"
       case 1'1
-        assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7746$2489_Y
+        assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7734$2477_Y
       case 
     end
-    attribute \src "ls180.v:7748.2-7756.5"
-    switch $and$ls180.v:7748$2492_Y
-      attribute \src "ls180.v:7748.6-7748.191"
+    attribute \src "ls180.v:7736.2-7744.5"
+    switch $and$ls180.v:7736$2480_Y
+      attribute \src "ls180.v:7736.6-7736.191"
       case 1'1
-        attribute \src "ls180.v:7749.3-7751.6"
-        switch $not$ls180.v:7749$2493_Y
-          attribute \src "ls180.v:7749.7-7749.62"
+        attribute \src "ls180.v:7737.3-7739.6"
+        switch $not$ls180.v:7737$2481_Y
+          attribute \src "ls180.v:7737.7-7737.62"
           case 1'1
-            assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7750$2494_Y
+            assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7738$2482_Y
           case 
         end
-      attribute \src "ls180.v:7752.6-7752.10"
+      attribute \src "ls180.v:7740.6-7740.10"
       case 
-        attribute \src "ls180.v:7753.3-7755.6"
+        attribute \src "ls180.v:7741.3-7743.6"
         switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
-          attribute \src "ls180.v:7753.7-7753.59"
+          attribute \src "ls180.v:7741.7-7741.59"
           case 1'1
-            assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7754$2495_Y
+            assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7742$2483_Y
           case 
         end
     end
-    attribute \src "ls180.v:7757.2-7763.5"
-    switch $or$ls180.v:7757$2497_Y
-      attribute \src "ls180.v:7757.6-7757.108"
+    attribute \src "ls180.v:7745.2-7751.5"
+    switch $or$ls180.v:7745$2485_Y
+      attribute \src "ls180.v:7745.6-7745.108"
       case 1'1
         assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid
         assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first
@@ -127634,27 +127466,27 @@ module \ls180
         assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr
       case 
     end
-    attribute \src "ls180.v:7764.2-7778.5"
+    attribute \src "ls180.v:7752.2-7766.5"
     switch \main_sdram_bankmachine3_twtpcon_valid
-      attribute \src "ls180.v:7764.6-7764.43"
+      attribute \src "ls180.v:7752.6-7752.43"
       case 1'1
         assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100
-        attribute \src "ls180.v:7766.3-7770.6"
+        attribute \src "ls180.v:7754.3-7758.6"
         switch 1'0
-          attribute \src "ls180.v:7768.7-7768.11"
+          attribute \src "ls180.v:7756.7-7756.11"
           case 
             assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:7771.6-7771.10"
+      attribute \src "ls180.v:7759.6-7759.10"
       case 
-        attribute \src "ls180.v:7772.3-7777.6"
-        switch $not$ls180.v:7772$2498_Y
-          attribute \src "ls180.v:7772.7-7772.47"
+        attribute \src "ls180.v:7760.3-7765.6"
+        switch $not$ls180.v:7760$2486_Y
+          attribute \src "ls180.v:7760.7-7760.47"
           case 1'1
-            assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7773$2499_Y
-            attribute \src "ls180.v:7774.4-7776.7"
-            switch $eq$ls180.v:7774$2500_Y
-              attribute \src "ls180.v:7774.8-7774.55"
+            assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7761$2487_Y
+            attribute \src "ls180.v:7762.4-7764.7"
+            switch $eq$ls180.v:7762$2488_Y
+              attribute \src "ls180.v:7762.8-7762.55"
               case 1'1
                 assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1
               case 
@@ -127662,61 +127494,61 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7780.2-7786.5"
-    switch $not$ls180.v:7780$2501_Y
-      attribute \src "ls180.v:7780.6-7780.23"
+    attribute \src "ls180.v:7768.2-7774.5"
+    switch $not$ls180.v:7768$2489_Y
+      attribute \src "ls180.v:7768.6-7768.23"
       case 1'1
         assign $0\main_sdram_time0[4:0] 5'11111
-      attribute \src "ls180.v:7782.6-7782.10"
+      attribute \src "ls180.v:7770.6-7770.10"
       case 
-        attribute \src "ls180.v:7783.3-7785.6"
-        switch $not$ls180.v:7783$2502_Y
-          attribute \src "ls180.v:7783.7-7783.30"
+        attribute \src "ls180.v:7771.3-7773.6"
+        switch $not$ls180.v:7771$2490_Y
+          attribute \src "ls180.v:7771.7-7771.30"
           case 1'1
-            assign $0\main_sdram_time0[4:0] $sub$ls180.v:7784$2503_Y
+            assign $0\main_sdram_time0[4:0] $sub$ls180.v:7772$2491_Y
           case 
         end
     end
-    attribute \src "ls180.v:7787.2-7793.5"
-    switch $not$ls180.v:7787$2504_Y
-      attribute \src "ls180.v:7787.6-7787.23"
+    attribute \src "ls180.v:7775.2-7781.5"
+    switch $not$ls180.v:7775$2492_Y
+      attribute \src "ls180.v:7775.6-7775.23"
       case 1'1
         assign $0\main_sdram_time1[3:0] 4'1111
-      attribute \src "ls180.v:7789.6-7789.10"
+      attribute \src "ls180.v:7777.6-7777.10"
       case 
-        attribute \src "ls180.v:7790.3-7792.6"
-        switch $not$ls180.v:7790$2505_Y
-          attribute \src "ls180.v:7790.7-7790.30"
+        attribute \src "ls180.v:7778.3-7780.6"
+        switch $not$ls180.v:7778$2493_Y
+          attribute \src "ls180.v:7778.7-7778.30"
           case 1'1
-            assign $0\main_sdram_time1[3:0] $sub$ls180.v:7791$2506_Y
+            assign $0\main_sdram_time1[3:0] $sub$ls180.v:7779$2494_Y
           case 
         end
     end
-    attribute \src "ls180.v:7794.2-7849.5"
+    attribute \src "ls180.v:7782.2-7837.5"
     switch \main_sdram_choose_cmd_ce
-      attribute \src "ls180.v:7794.6-7794.30"
+      attribute \src "ls180.v:7782.6-7782.30"
       case 1'1
-        attribute \src "ls180.v:7795.3-7848.10"
+        attribute \src "ls180.v:7783.3-7836.10"
         switch \main_sdram_choose_cmd_grant
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
-            attribute \src "ls180.v:7797.5-7807.8"
+            attribute \src "ls180.v:7785.5-7795.8"
             switch \main_sdram_choose_cmd_request [1]
-              attribute \src "ls180.v:7797.9-7797.41"
+              attribute \src "ls180.v:7785.9-7785.41"
               case 1'1
                 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
-              attribute \src "ls180.v:7799.9-7799.13"
+              attribute \src "ls180.v:7787.9-7787.13"
               case 
-                attribute \src "ls180.v:7800.6-7806.9"
+                attribute \src "ls180.v:7788.6-7794.9"
                 switch \main_sdram_choose_cmd_request [2]
-                  attribute \src "ls180.v:7800.10-7800.42"
+                  attribute \src "ls180.v:7788.10-7788.42"
                   case 1'1
                     assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
-                  attribute \src "ls180.v:7802.10-7802.14"
+                  attribute \src "ls180.v:7790.10-7790.14"
                   case 
-                    attribute \src "ls180.v:7803.7-7805.10"
+                    attribute \src "ls180.v:7791.7-7793.10"
                     switch \main_sdram_choose_cmd_request [3]
-                      attribute \src "ls180.v:7803.11-7803.43"
+                      attribute \src "ls180.v:7791.11-7791.43"
                       case 1'1
                         assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
                       case 
@@ -127725,23 +127557,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'01
-            attribute \src "ls180.v:7810.5-7820.8"
+            attribute \src "ls180.v:7798.5-7808.8"
             switch \main_sdram_choose_cmd_request [2]
-              attribute \src "ls180.v:7810.9-7810.41"
+              attribute \src "ls180.v:7798.9-7798.41"
               case 1'1
                 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
-              attribute \src "ls180.v:7812.9-7812.13"
+              attribute \src "ls180.v:7800.9-7800.13"
               case 
-                attribute \src "ls180.v:7813.6-7819.9"
+                attribute \src "ls180.v:7801.6-7807.9"
                 switch \main_sdram_choose_cmd_request [3]
-                  attribute \src "ls180.v:7813.10-7813.42"
+                  attribute \src "ls180.v:7801.10-7801.42"
                   case 1'1
                     assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
-                  attribute \src "ls180.v:7815.10-7815.14"
+                  attribute \src "ls180.v:7803.10-7803.14"
                   case 
-                    attribute \src "ls180.v:7816.7-7818.10"
+                    attribute \src "ls180.v:7804.7-7806.10"
                     switch \main_sdram_choose_cmd_request [0]
-                      attribute \src "ls180.v:7816.11-7816.43"
+                      attribute \src "ls180.v:7804.11-7804.43"
                       case 1'1
                         assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
                       case 
@@ -127750,23 +127582,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'10
-            attribute \src "ls180.v:7823.5-7833.8"
+            attribute \src "ls180.v:7811.5-7821.8"
             switch \main_sdram_choose_cmd_request [3]
-              attribute \src "ls180.v:7823.9-7823.41"
+              attribute \src "ls180.v:7811.9-7811.41"
               case 1'1
                 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
-              attribute \src "ls180.v:7825.9-7825.13"
+              attribute \src "ls180.v:7813.9-7813.13"
               case 
-                attribute \src "ls180.v:7826.6-7832.9"
+                attribute \src "ls180.v:7814.6-7820.9"
                 switch \main_sdram_choose_cmd_request [0]
-                  attribute \src "ls180.v:7826.10-7826.42"
+                  attribute \src "ls180.v:7814.10-7814.42"
                   case 1'1
                     assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
-                  attribute \src "ls180.v:7828.10-7828.14"
+                  attribute \src "ls180.v:7816.10-7816.14"
                   case 
-                    attribute \src "ls180.v:7829.7-7831.10"
+                    attribute \src "ls180.v:7817.7-7819.10"
                     switch \main_sdram_choose_cmd_request [1]
-                      attribute \src "ls180.v:7829.11-7829.43"
+                      attribute \src "ls180.v:7817.11-7817.43"
                       case 1'1
                         assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
                       case 
@@ -127775,23 +127607,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'11
-            attribute \src "ls180.v:7836.5-7846.8"
+            attribute \src "ls180.v:7824.5-7834.8"
             switch \main_sdram_choose_cmd_request [0]
-              attribute \src "ls180.v:7836.9-7836.41"
+              attribute \src "ls180.v:7824.9-7824.41"
               case 1'1
                 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
-              attribute \src "ls180.v:7838.9-7838.13"
+              attribute \src "ls180.v:7826.9-7826.13"
               case 
-                attribute \src "ls180.v:7839.6-7845.9"
+                attribute \src "ls180.v:7827.6-7833.9"
                 switch \main_sdram_choose_cmd_request [1]
-                  attribute \src "ls180.v:7839.10-7839.42"
+                  attribute \src "ls180.v:7827.10-7827.42"
                   case 1'1
                     assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
-                  attribute \src "ls180.v:7841.10-7841.14"
+                  attribute \src "ls180.v:7829.10-7829.14"
                   case 
-                    attribute \src "ls180.v:7842.7-7844.10"
+                    attribute \src "ls180.v:7830.7-7832.10"
                     switch \main_sdram_choose_cmd_request [2]
-                      attribute \src "ls180.v:7842.11-7842.43"
+                      attribute \src "ls180.v:7830.11-7830.43"
                       case 1'1
                         assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
                       case 
@@ -127802,31 +127634,31 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:7850.2-7905.5"
+    attribute \src "ls180.v:7838.2-7893.5"
     switch \main_sdram_choose_req_ce
-      attribute \src "ls180.v:7850.6-7850.30"
+      attribute \src "ls180.v:7838.6-7838.30"
       case 1'1
-        attribute \src "ls180.v:7851.3-7904.10"
+        attribute \src "ls180.v:7839.3-7892.10"
         switch \main_sdram_choose_req_grant
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
-            attribute \src "ls180.v:7853.5-7863.8"
+            attribute \src "ls180.v:7841.5-7851.8"
             switch \main_sdram_choose_req_request [1]
-              attribute \src "ls180.v:7853.9-7853.41"
+              attribute \src "ls180.v:7841.9-7841.41"
               case 1'1
                 assign $0\main_sdram_choose_req_grant[1:0] 2'01
-              attribute \src "ls180.v:7855.9-7855.13"
+              attribute \src "ls180.v:7843.9-7843.13"
               case 
-                attribute \src "ls180.v:7856.6-7862.9"
+                attribute \src "ls180.v:7844.6-7850.9"
                 switch \main_sdram_choose_req_request [2]
-                  attribute \src "ls180.v:7856.10-7856.42"
+                  attribute \src "ls180.v:7844.10-7844.42"
                   case 1'1
                     assign $0\main_sdram_choose_req_grant[1:0] 2'10
-                  attribute \src "ls180.v:7858.10-7858.14"
+                  attribute \src "ls180.v:7846.10-7846.14"
                   case 
-                    attribute \src "ls180.v:7859.7-7861.10"
+                    attribute \src "ls180.v:7847.7-7849.10"
                     switch \main_sdram_choose_req_request [3]
-                      attribute \src "ls180.v:7859.11-7859.43"
+                      attribute \src "ls180.v:7847.11-7847.43"
                       case 1'1
                         assign $0\main_sdram_choose_req_grant[1:0] 2'11
                       case 
@@ -127835,23 +127667,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'01
-            attribute \src "ls180.v:7866.5-7876.8"
+            attribute \src "ls180.v:7854.5-7864.8"
             switch \main_sdram_choose_req_request [2]
-              attribute \src "ls180.v:7866.9-7866.41"
+              attribute \src "ls180.v:7854.9-7854.41"
               case 1'1
                 assign $0\main_sdram_choose_req_grant[1:0] 2'10
-              attribute \src "ls180.v:7868.9-7868.13"
+              attribute \src "ls180.v:7856.9-7856.13"
               case 
-                attribute \src "ls180.v:7869.6-7875.9"
+                attribute \src "ls180.v:7857.6-7863.9"
                 switch \main_sdram_choose_req_request [3]
-                  attribute \src "ls180.v:7869.10-7869.42"
+                  attribute \src "ls180.v:7857.10-7857.42"
                   case 1'1
                     assign $0\main_sdram_choose_req_grant[1:0] 2'11
-                  attribute \src "ls180.v:7871.10-7871.14"
+                  attribute \src "ls180.v:7859.10-7859.14"
                   case 
-                    attribute \src "ls180.v:7872.7-7874.10"
+                    attribute \src "ls180.v:7860.7-7862.10"
                     switch \main_sdram_choose_req_request [0]
-                      attribute \src "ls180.v:7872.11-7872.43"
+                      attribute \src "ls180.v:7860.11-7860.43"
                       case 1'1
                         assign $0\main_sdram_choose_req_grant[1:0] 2'00
                       case 
@@ -127860,23 +127692,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'10
-            attribute \src "ls180.v:7879.5-7889.8"
+            attribute \src "ls180.v:7867.5-7877.8"
             switch \main_sdram_choose_req_request [3]
-              attribute \src "ls180.v:7879.9-7879.41"
+              attribute \src "ls180.v:7867.9-7867.41"
               case 1'1
                 assign $0\main_sdram_choose_req_grant[1:0] 2'11
-              attribute \src "ls180.v:7881.9-7881.13"
+              attribute \src "ls180.v:7869.9-7869.13"
               case 
-                attribute \src "ls180.v:7882.6-7888.9"
+                attribute \src "ls180.v:7870.6-7876.9"
                 switch \main_sdram_choose_req_request [0]
-                  attribute \src "ls180.v:7882.10-7882.42"
+                  attribute \src "ls180.v:7870.10-7870.42"
                   case 1'1
                     assign $0\main_sdram_choose_req_grant[1:0] 2'00
-                  attribute \src "ls180.v:7884.10-7884.14"
+                  attribute \src "ls180.v:7872.10-7872.14"
                   case 
-                    attribute \src "ls180.v:7885.7-7887.10"
+                    attribute \src "ls180.v:7873.7-7875.10"
                     switch \main_sdram_choose_req_request [1]
-                      attribute \src "ls180.v:7885.11-7885.43"
+                      attribute \src "ls180.v:7873.11-7873.43"
                       case 1'1
                         assign $0\main_sdram_choose_req_grant[1:0] 2'01
                       case 
@@ -127885,23 +127717,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'11
-            attribute \src "ls180.v:7892.5-7902.8"
+            attribute \src "ls180.v:7880.5-7890.8"
             switch \main_sdram_choose_req_request [0]
-              attribute \src "ls180.v:7892.9-7892.41"
+              attribute \src "ls180.v:7880.9-7880.41"
               case 1'1
                 assign $0\main_sdram_choose_req_grant[1:0] 2'00
-              attribute \src "ls180.v:7894.9-7894.13"
+              attribute \src "ls180.v:7882.9-7882.13"
               case 
-                attribute \src "ls180.v:7895.6-7901.9"
+                attribute \src "ls180.v:7883.6-7889.9"
                 switch \main_sdram_choose_req_request [1]
-                  attribute \src "ls180.v:7895.10-7895.42"
+                  attribute \src "ls180.v:7883.10-7883.42"
                   case 1'1
                     assign $0\main_sdram_choose_req_grant[1:0] 2'01
-                  attribute \src "ls180.v:7897.10-7897.14"
+                  attribute \src "ls180.v:7885.10-7885.14"
                   case 
-                    attribute \src "ls180.v:7898.7-7900.10"
+                    attribute \src "ls180.v:7886.7-7888.10"
                     switch \main_sdram_choose_req_request [2]
-                      attribute \src "ls180.v:7898.11-7898.43"
+                      attribute \src "ls180.v:7886.11-7886.43"
                       case 1'1
                         assign $0\main_sdram_choose_req_grant[1:0] 2'10
                       case 
@@ -127912,28 +127744,28 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:7914.2-7928.5"
+    attribute \src "ls180.v:7902.2-7916.5"
     switch \main_sdram_tccdcon_valid
-      attribute \src "ls180.v:7914.6-7914.30"
+      attribute \src "ls180.v:7902.6-7902.30"
       case 1'1
         assign $0\main_sdram_tccdcon_count[0:0] 1'0
-        attribute \src "ls180.v:7916.3-7920.6"
+        attribute \src "ls180.v:7904.3-7908.6"
         switch 1'1
-          attribute \src "ls180.v:7916.7-7916.11"
+          attribute \src "ls180.v:7904.7-7904.11"
           case 1'1
             assign $0\main_sdram_tccdcon_ready[0:0] 1'1
           case 
         end
-      attribute \src "ls180.v:7921.6-7921.10"
+      attribute \src "ls180.v:7909.6-7909.10"
       case 
-        attribute \src "ls180.v:7922.3-7927.6"
-        switch $not$ls180.v:7922$2510_Y
-          attribute \src "ls180.v:7922.7-7922.34"
+        attribute \src "ls180.v:7910.3-7915.6"
+        switch $not$ls180.v:7910$2498_Y
+          attribute \src "ls180.v:7910.7-7910.34"
           case 1'1
-            assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7923$2511_Y
-            attribute \src "ls180.v:7924.4-7926.7"
-            switch $eq$ls180.v:7924$2512_Y
-              attribute \src "ls180.v:7924.8-7924.42"
+            assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7911$2499_Y
+            attribute \src "ls180.v:7912.4-7914.7"
+            switch $eq$ls180.v:7912$2500_Y
+              attribute \src "ls180.v:7912.8-7912.42"
               case 1'1
                 assign $0\main_sdram_tccdcon_ready[0:0] 1'1
               case 
@@ -127941,27 +127773,27 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7929.2-7943.5"
+    attribute \src "ls180.v:7917.2-7931.5"
     switch \main_sdram_twtrcon_valid
-      attribute \src "ls180.v:7929.6-7929.30"
+      attribute \src "ls180.v:7917.6-7917.30"
       case 1'1
         assign $0\main_sdram_twtrcon_count[2:0] 3'100
-        attribute \src "ls180.v:7931.3-7935.6"
+        attribute \src "ls180.v:7919.3-7923.6"
         switch 1'0
-          attribute \src "ls180.v:7933.7-7933.11"
+          attribute \src "ls180.v:7921.7-7921.11"
           case 
             assign $0\main_sdram_twtrcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:7936.6-7936.10"
+      attribute \src "ls180.v:7924.6-7924.10"
       case 
-        attribute \src "ls180.v:7937.3-7942.6"
-        switch $not$ls180.v:7937$2513_Y
-          attribute \src "ls180.v:7937.7-7937.34"
+        attribute \src "ls180.v:7925.3-7930.6"
+        switch $not$ls180.v:7925$2501_Y
+          attribute \src "ls180.v:7925.7-7925.34"
           case 1'1
-            assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7938$2514_Y
-            attribute \src "ls180.v:7939.4-7941.7"
-            switch $eq$ls180.v:7939$2515_Y
-              attribute \src "ls180.v:7939.8-7939.42"
+            assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7926$2502_Y
+            attribute \src "ls180.v:7927.4-7929.7"
+            switch $eq$ls180.v:7927$2503_Y
+              attribute \src "ls180.v:7927.8-7927.42"
               case 1'1
                 assign $0\main_sdram_twtrcon_ready[0:0] 1'1
               case 
@@ -127969,81 +127801,81 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7950.2-7952.5"
-    switch $or$ls180.v:7950$2540_Y
-      attribute \src "ls180.v:7950.6-7950.50"
+    attribute \src "ls180.v:7938.2-7940.5"
+    switch $or$ls180.v:7938$2528_Y
+      attribute \src "ls180.v:7938.6-7938.50"
       case 1'1
         assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r
       case 
     end
-    attribute \src "ls180.v:7954.2-7956.5"
+    attribute \src "ls180.v:7942.2-7944.5"
     switch \main_converter_counter_converter_next_value_ce
-      attribute \src "ls180.v:7954.6-7954.52"
+      attribute \src "ls180.v:7942.6-7942.52"
       case 1'1
         assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value
       case 
     end
-    attribute \src "ls180.v:7957.2-7960.5"
+    attribute \src "ls180.v:7945.2-7948.5"
     switch \main_converter_reset
-      attribute \src "ls180.v:7957.6-7957.26"
+      attribute \src "ls180.v:7945.6-7945.26"
       case 1'1
         assign $0\main_converter_counter[0:0] 1'0
         assign $0\builder_converter_state[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:7961.2-7971.5"
+    attribute \src "ls180.v:7949.2-7959.5"
     switch \main_litedram_wb_ack
-      attribute \src "ls180.v:7961.6-7961.26"
+      attribute \src "ls180.v:7949.6-7949.26"
       case 1'1
         assign $0\main_cmd_consumed[0:0] 1'0
         assign $0\main_wdata_consumed[0:0] 1'0
-      attribute \src "ls180.v:7964.6-7964.10"
+      attribute \src "ls180.v:7952.6-7952.10"
       case 
-        attribute \src "ls180.v:7965.3-7967.6"
-        switch $and$ls180.v:7965$2541_Y
-          attribute \src "ls180.v:7965.7-7965.50"
+        attribute \src "ls180.v:7953.3-7955.6"
+        switch $and$ls180.v:7953$2529_Y
+          attribute \src "ls180.v:7953.7-7953.50"
           case 1'1
             assign $0\main_cmd_consumed[0:0] 1'1
           case 
         end
-        attribute \src "ls180.v:7968.3-7970.6"
-        switch $and$ls180.v:7968$2542_Y
-          attribute \src "ls180.v:7968.7-7968.54"
+        attribute \src "ls180.v:7956.3-7958.6"
+        switch $and$ls180.v:7956$2530_Y
+          attribute \src "ls180.v:7956.7-7956.54"
           case 1'1
             assign $0\main_wdata_consumed[0:0] 1'1
           case 
         end
     end
-    attribute \src "ls180.v:7973.2-7994.5"
-    switch $and$ls180.v:7973$2546_Y
-      attribute \src "ls180.v:7973.6-7973.91"
+    attribute \src "ls180.v:7961.2-7982.5"
+    switch $and$ls180.v:7961$2534_Y
+      attribute \src "ls180.v:7961.6-7961.91"
       case 1'1
         assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data
         assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000
         assign $0\main_uart_phy_tx_busy[0:0] 1'1
         assign $0\uart_tx[0:0] 1'0
-      attribute \src "ls180.v:7978.6-7978.10"
+      attribute \src "ls180.v:7966.6-7966.10"
       case 
-        attribute \src "ls180.v:7979.3-7993.6"
-        switch $and$ls180.v:7979$2547_Y
-          attribute \src "ls180.v:7979.7-7979.60"
+        attribute \src "ls180.v:7967.3-7981.6"
+        switch $and$ls180.v:7967$2535_Y
+          attribute \src "ls180.v:7967.7-7967.60"
           case 1'1
-            assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7980$2548_Y
-            attribute \src "ls180.v:7981.4-7992.7"
-            switch $eq$ls180.v:7981$2549_Y
-              attribute \src "ls180.v:7981.8-7981.43"
+            assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7968$2536_Y
+            attribute \src "ls180.v:7969.4-7980.7"
+            switch $eq$ls180.v:7969$2537_Y
+              attribute \src "ls180.v:7969.8-7969.43"
               case 1'1
                 assign $0\uart_tx[0:0] 1'1
-              attribute \src "ls180.v:7983.8-7983.12"
+              attribute \src "ls180.v:7971.8-7971.12"
               case 
-                attribute \src "ls180.v:7984.5-7991.8"
-                switch $eq$ls180.v:7984$2550_Y
-                  attribute \src "ls180.v:7984.9-7984.44"
+                attribute \src "ls180.v:7972.5-7979.8"
+                switch $eq$ls180.v:7972$2538_Y
+                  attribute \src "ls180.v:7972.9-7972.44"
                   case 1'1
                     assign $0\uart_tx[0:0] 1'1
                     assign $0\main_uart_phy_tx_busy[0:0] 1'0
                     assign $0\main_uart_phy_sink_ready[0:0] 1'1
-                  attribute \src "ls180.v:7988.9-7988.13"
+                  attribute \src "ls180.v:7976.9-7976.13"
                   case 
                     assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0]
                     assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] }
@@ -128052,61 +127884,61 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:7995.2-7999.5"
+    attribute \src "ls180.v:7983.2-7987.5"
     switch \main_uart_phy_tx_busy
-      attribute \src "ls180.v:7995.6-7995.27"
+      attribute \src "ls180.v:7983.6-7983.27"
       case 1'1
-        assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7996$2551_Y
-      attribute \src "ls180.v:7997.6-7997.10"
+        assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7984$2539_Y
+      attribute \src "ls180.v:7985.6-7985.10"
       case 
         assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage }
     end
-    attribute \src "ls180.v:8002.2-8026.5"
-    switch $not$ls180.v:8002$2552_Y
-      attribute \src "ls180.v:8002.6-8002.30"
+    attribute \src "ls180.v:7990.2-8014.5"
+    switch $not$ls180.v:7990$2540_Y
+      attribute \src "ls180.v:7990.6-7990.30"
       case 1'1
-        attribute \src "ls180.v:8003.3-8006.6"
-        switch $and$ls180.v:8003$2554_Y
-          attribute \src "ls180.v:8003.7-8003.49"
+        attribute \src "ls180.v:7991.3-7994.6"
+        switch $and$ls180.v:7991$2542_Y
+          attribute \src "ls180.v:7991.7-7991.49"
           case 1'1
             assign $0\main_uart_phy_rx_busy[0:0] 1'1
             assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000
           case 
         end
-      attribute \src "ls180.v:8007.6-8007.10"
+      attribute \src "ls180.v:7995.6-7995.10"
       case 
-        attribute \src "ls180.v:8008.3-8025.6"
+        attribute \src "ls180.v:7996.3-8013.6"
         switch \main_uart_phy_uart_clk_rxen
-          attribute \src "ls180.v:8008.7-8008.34"
+          attribute \src "ls180.v:7996.7-7996.34"
           case 1'1
-            assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8009$2555_Y
-            attribute \src "ls180.v:8010.4-8024.7"
-            switch $eq$ls180.v:8010$2556_Y
-              attribute \src "ls180.v:8010.8-8010.43"
+            assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:7997$2543_Y
+            attribute \src "ls180.v:7998.4-8012.7"
+            switch $eq$ls180.v:7998$2544_Y
+              attribute \src "ls180.v:7998.8-7998.43"
               case 1'1
-                attribute \src "ls180.v:8011.5-8013.8"
+                attribute \src "ls180.v:7999.5-8001.8"
                 switch \main_uart_phy_rx
-                  attribute \src "ls180.v:8011.9-8011.25"
+                  attribute \src "ls180.v:7999.9-7999.25"
                   case 1'1
                     assign $0\main_uart_phy_rx_busy[0:0] 1'0
                   case 
                 end
-              attribute \src "ls180.v:8014.8-8014.12"
+              attribute \src "ls180.v:8002.8-8002.12"
               case 
-                attribute \src "ls180.v:8015.5-8023.8"
-                switch $eq$ls180.v:8015$2557_Y
-                  attribute \src "ls180.v:8015.9-8015.44"
+                attribute \src "ls180.v:8003.5-8011.8"
+                switch $eq$ls180.v:8003$2545_Y
+                  attribute \src "ls180.v:8003.9-8003.44"
                   case 1'1
                     assign $0\main_uart_phy_rx_busy[0:0] 1'0
-                    attribute \src "ls180.v:8017.6-8020.9"
+                    attribute \src "ls180.v:8005.6-8008.9"
                     switch \main_uart_phy_rx
-                      attribute \src "ls180.v:8017.10-8017.26"
+                      attribute \src "ls180.v:8005.10-8005.26"
                       case 1'1
                         assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg
                         assign $0\main_uart_phy_source_valid[0:0] 1'1
                       case 
                     end
-                  attribute \src "ls180.v:8021.9-8021.13"
+                  attribute \src "ls180.v:8009.9-8009.13"
                   case 
                     assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] }
                 end
@@ -128114,146 +127946,146 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:8027.2-8031.5"
+    attribute \src "ls180.v:8015.2-8019.5"
     switch \main_uart_phy_rx_busy
-      attribute \src "ls180.v:8027.6-8027.27"
+      attribute \src "ls180.v:8015.6-8015.27"
       case 1'1
-        assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8028$2558_Y
-      attribute \src "ls180.v:8029.6-8029.10"
+        assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8016$2546_Y
+      attribute \src "ls180.v:8017.6-8017.10"
       case 
         assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000
     end
-    attribute \src "ls180.v:8032.2-8034.5"
+    attribute \src "ls180.v:8020.2-8022.5"
     switch \main_uart_tx_clear
-      attribute \src "ls180.v:8032.6-8032.24"
+      attribute \src "ls180.v:8020.6-8020.24"
       case 1'1
         assign $0\main_uart_tx_pending[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8036.2-8038.5"
-    switch $and$ls180.v:8036$2560_Y
-      attribute \src "ls180.v:8036.6-8036.58"
+    attribute \src "ls180.v:8024.2-8026.5"
+    switch $and$ls180.v:8024$2548_Y
+      attribute \src "ls180.v:8024.6-8024.58"
       case 1'1
         assign $0\main_uart_tx_pending[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:8039.2-8041.5"
+    attribute \src "ls180.v:8027.2-8029.5"
     switch \main_uart_rx_clear
-      attribute \src "ls180.v:8039.6-8039.24"
+      attribute \src "ls180.v:8027.6-8027.24"
       case 1'1
         assign $0\main_uart_rx_pending[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8043.2-8045.5"
-    switch $and$ls180.v:8043$2562_Y
-      attribute \src "ls180.v:8043.6-8043.58"
+    attribute \src "ls180.v:8031.2-8033.5"
+    switch $and$ls180.v:8031$2550_Y
+      attribute \src "ls180.v:8031.6-8031.58"
       case 1'1
         assign $0\main_uart_rx_pending[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:8046.2-8052.5"
+    attribute \src "ls180.v:8034.2-8040.5"
     switch \main_uart_tx_fifo_syncfifo_re
-      attribute \src "ls180.v:8046.6-8046.35"
+      attribute \src "ls180.v:8034.6-8034.35"
       case 1'1
         assign $0\main_uart_tx_fifo_readable[0:0] 1'1
-      attribute \src "ls180.v:8048.6-8048.10"
+      attribute \src "ls180.v:8036.6-8036.10"
       case 
-        attribute \src "ls180.v:8049.3-8051.6"
+        attribute \src "ls180.v:8037.3-8039.6"
         switch \main_uart_tx_fifo_re
-          attribute \src "ls180.v:8049.7-8049.27"
+          attribute \src "ls180.v:8037.7-8037.27"
           case 1'1
             assign $0\main_uart_tx_fifo_readable[0:0] 1'0
           case 
         end
     end
-    attribute \src "ls180.v:8053.2-8055.5"
-    switch $and$ls180.v:8053$2565_Y
-      attribute \src "ls180.v:8053.6-8053.108"
+    attribute \src "ls180.v:8041.2-8043.5"
+    switch $and$ls180.v:8041$2553_Y
+      attribute \src "ls180.v:8041.6-8041.108"
       case 1'1
-        assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8054$2566_Y
+        assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8042$2554_Y
       case 
     end
-    attribute \src "ls180.v:8056.2-8058.5"
+    attribute \src "ls180.v:8044.2-8046.5"
     switch \main_uart_tx_fifo_do_read
-      attribute \src "ls180.v:8056.6-8056.31"
+      attribute \src "ls180.v:8044.6-8044.31"
       case 1'1
-        assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8057$2567_Y
+        assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8045$2555_Y
       case 
     end
-    attribute \src "ls180.v:8059.2-8067.5"
-    switch $and$ls180.v:8059$2570_Y
-      attribute \src "ls180.v:8059.6-8059.108"
+    attribute \src "ls180.v:8047.2-8055.5"
+    switch $and$ls180.v:8047$2558_Y
+      attribute \src "ls180.v:8047.6-8047.108"
       case 1'1
-        attribute \src "ls180.v:8060.3-8062.6"
-        switch $not$ls180.v:8060$2571_Y
-          attribute \src "ls180.v:8060.7-8060.35"
+        attribute \src "ls180.v:8048.3-8050.6"
+        switch $not$ls180.v:8048$2559_Y
+          attribute \src "ls180.v:8048.7-8048.35"
           case 1'1
-            assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8061$2572_Y
+            assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8049$2560_Y
           case 
         end
-      attribute \src "ls180.v:8063.6-8063.10"
+      attribute \src "ls180.v:8051.6-8051.10"
       case 
-        attribute \src "ls180.v:8064.3-8066.6"
+        attribute \src "ls180.v:8052.3-8054.6"
         switch \main_uart_tx_fifo_do_read
-          attribute \src "ls180.v:8064.7-8064.32"
+          attribute \src "ls180.v:8052.7-8052.32"
           case 1'1
-            assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8065$2573_Y
+            assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8053$2561_Y
           case 
         end
     end
-    attribute \src "ls180.v:8068.2-8074.5"
+    attribute \src "ls180.v:8056.2-8062.5"
     switch \main_uart_rx_fifo_syncfifo_re
-      attribute \src "ls180.v:8068.6-8068.35"
+      attribute \src "ls180.v:8056.6-8056.35"
       case 1'1
         assign $0\main_uart_rx_fifo_readable[0:0] 1'1
-      attribute \src "ls180.v:8070.6-8070.10"
+      attribute \src "ls180.v:8058.6-8058.10"
       case 
-        attribute \src "ls180.v:8071.3-8073.6"
+        attribute \src "ls180.v:8059.3-8061.6"
         switch \main_uart_rx_fifo_re
-          attribute \src "ls180.v:8071.7-8071.27"
+          attribute \src "ls180.v:8059.7-8059.27"
           case 1'1
             assign $0\main_uart_rx_fifo_readable[0:0] 1'0
           case 
         end
     end
-    attribute \src "ls180.v:8075.2-8077.5"
-    switch $and$ls180.v:8075$2576_Y
-      attribute \src "ls180.v:8075.6-8075.108"
+    attribute \src "ls180.v:8063.2-8065.5"
+    switch $and$ls180.v:8063$2564_Y
+      attribute \src "ls180.v:8063.6-8063.108"
       case 1'1
-        assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8076$2577_Y
+        assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8064$2565_Y
       case 
     end
-    attribute \src "ls180.v:8078.2-8080.5"
+    attribute \src "ls180.v:8066.2-8068.5"
     switch \main_uart_rx_fifo_do_read
-      attribute \src "ls180.v:8078.6-8078.31"
+      attribute \src "ls180.v:8066.6-8066.31"
       case 1'1
-        assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8079$2578_Y
+        assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8067$2566_Y
       case 
     end
-    attribute \src "ls180.v:8081.2-8089.5"
-    switch $and$ls180.v:8081$2581_Y
-      attribute \src "ls180.v:8081.6-8081.108"
+    attribute \src "ls180.v:8069.2-8077.5"
+    switch $and$ls180.v:8069$2569_Y
+      attribute \src "ls180.v:8069.6-8069.108"
       case 1'1
-        attribute \src "ls180.v:8082.3-8084.6"
-        switch $not$ls180.v:8082$2582_Y
-          attribute \src "ls180.v:8082.7-8082.35"
+        attribute \src "ls180.v:8070.3-8072.6"
+        switch $not$ls180.v:8070$2570_Y
+          attribute \src "ls180.v:8070.7-8070.35"
           case 1'1
-            assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8083$2583_Y
+            assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8071$2571_Y
           case 
         end
-      attribute \src "ls180.v:8085.6-8085.10"
+      attribute \src "ls180.v:8073.6-8073.10"
       case 
-        attribute \src "ls180.v:8086.3-8088.6"
+        attribute \src "ls180.v:8074.3-8076.6"
         switch \main_uart_rx_fifo_do_read
-          attribute \src "ls180.v:8086.7-8086.32"
+          attribute \src "ls180.v:8074.7-8074.32"
           case 1'1
-            assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8087$2584_Y
+            assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8075$2572_Y
           case 
         end
     end
-    attribute \src "ls180.v:8090.2-8103.5"
+    attribute \src "ls180.v:8078.2-8091.5"
     switch \main_uart_reset
-      attribute \src "ls180.v:8090.6-8090.21"
+      attribute \src "ls180.v:8078.6-8078.21"
       case 1'1
         assign $0\main_uart_tx_pending[0:0] 1'0
         assign $0\main_uart_tx_old_trigger[0:0] 1'0
@@ -128269,38 +128101,38 @@ module \ls180
         assign $0\main_uart_rx_fifo_consume[3:0] 4'0000
       case 
     end
-    attribute \src "ls180.v:8105.2-8112.5"
+    attribute \src "ls180.v:8093.2-8100.5"
     switch \main_spimaster31_clk_rise
-      attribute \src "ls180.v:8105.6-8105.31"
+      attribute \src "ls180.v:8093.6-8093.31"
       case 1'1
         assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable
-      attribute \src "ls180.v:8107.6-8107.10"
+      attribute \src "ls180.v:8095.6-8095.10"
       case 
-        attribute \src "ls180.v:8108.3-8111.6"
+        attribute \src "ls180.v:8096.3-8099.6"
         switch \main_spimaster32_clk_fall
-          attribute \src "ls180.v:8108.7-8108.32"
+          attribute \src "ls180.v:8096.7-8096.32"
           case 1'1
             assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000
             assign $0\spisdcard_clk[0:0] 1'0
           case 
         end
     end
-    attribute \src "ls180.v:8114.2-8124.5"
+    attribute \src "ls180.v:8102.2-8112.5"
     switch \main_spimaster28_mosi_latch
-      attribute \src "ls180.v:8114.6-8114.33"
+      attribute \src "ls180.v:8102.6-8102.33"
       case 1'1
         assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi
         assign $0\main_spimaster34_mosi_sel[2:0] 3'111
-      attribute \src "ls180.v:8117.6-8117.10"
+      attribute \src "ls180.v:8105.6-8105.10"
       case 
-        attribute \src "ls180.v:8118.3-8123.6"
+        attribute \src "ls180.v:8106.3-8111.6"
         switch \main_spimaster32_clk_fall
-          attribute \src "ls180.v:8118.7-8118.32"
+          attribute \src "ls180.v:8106.7-8106.32"
           case 1'1
-            assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8122$2589_Y
-            attribute \src "ls180.v:8119.4-8121.7"
+            assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8110$2577_Y
+            attribute \src "ls180.v:8107.4-8109.7"
             switch \main_spimaster26_cs_enable
-              attribute \src "ls180.v:8119.8-8119.34"
+              attribute \src "ls180.v:8107.8-8107.34"
               case 1'1
                 assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0
               case 
@@ -128308,67 +128140,67 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:8125.2-8131.5"
+    attribute \src "ls180.v:8113.2-8119.5"
     switch \main_spimaster31_clk_rise
-      attribute \src "ls180.v:8125.6-8125.31"
+      attribute \src "ls180.v:8113.6-8113.31"
       case 1'1
-        attribute \src "ls180.v:8126.3-8130.6"
+        attribute \src "ls180.v:8114.3-8118.6"
         switch \main_spimaster7_loopback
-          attribute \src "ls180.v:8126.7-8126.31"
+          attribute \src "ls180.v:8114.7-8114.31"
           case 1'1
             assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi }
-          attribute \src "ls180.v:8128.7-8128.11"
+          attribute \src "ls180.v:8116.7-8116.11"
           case 
             assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso }
         end
       case 
     end
-    attribute \src "ls180.v:8132.2-8134.5"
+    attribute \src "ls180.v:8120.2-8122.5"
     switch \main_spimaster29_miso_latch
-      attribute \src "ls180.v:8132.6-8132.33"
+      attribute \src "ls180.v:8120.6-8120.33"
       case 1'1
         assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data
       case 
     end
-    attribute \src "ls180.v:8136.2-8138.5"
+    attribute \src "ls180.v:8124.2-8126.5"
     switch \main_spimaster27_count_spimaster0_next_value_ce
-      attribute \src "ls180.v:8136.6-8136.53"
+      attribute \src "ls180.v:8124.6-8124.53"
       case 1'1
         assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value
       case 
     end
-    attribute \src "ls180.v:8140.2-8147.5"
+    attribute \src "ls180.v:8128.2-8135.5"
     switch \main_spisdcard_clk_rise
-      attribute \src "ls180.v:8140.6-8140.29"
+      attribute \src "ls180.v:8128.6-8128.29"
       case 1'1
         assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable
-      attribute \src "ls180.v:8142.6-8142.10"
+      attribute \src "ls180.v:8130.6-8130.10"
       case 
-        attribute \src "ls180.v:8143.3-8146.6"
+        attribute \src "ls180.v:8131.3-8134.6"
         switch \main_spisdcard_clk_fall
-          attribute \src "ls180.v:8143.7-8143.30"
+          attribute \src "ls180.v:8131.7-8131.30"
           case 1'1
             assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000
             assign $0\spimaster_clk[0:0] 1'0
           case 
         end
     end
-    attribute \src "ls180.v:8149.2-8159.5"
+    attribute \src "ls180.v:8137.2-8147.5"
     switch \main_spisdcard_mosi_latch
-      attribute \src "ls180.v:8149.6-8149.31"
+      attribute \src "ls180.v:8137.6-8137.31"
       case 1'1
         assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi
         assign $0\main_spisdcard_mosi_sel[2:0] 3'111
-      attribute \src "ls180.v:8152.6-8152.10"
+      attribute \src "ls180.v:8140.6-8140.10"
       case 
-        attribute \src "ls180.v:8153.3-8158.6"
+        attribute \src "ls180.v:8141.3-8146.6"
         switch \main_spisdcard_clk_fall
-          attribute \src "ls180.v:8153.7-8153.30"
+          attribute \src "ls180.v:8141.7-8141.30"
           case 1'1
-            assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8157$2594_Y
-            attribute \src "ls180.v:8154.4-8156.7"
+            assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8145$2582_Y
+            attribute \src "ls180.v:8142.4-8144.7"
             switch \main_spisdcard_cs_enable
-              attribute \src "ls180.v:8154.8-8154.32"
+              attribute \src "ls180.v:8142.8-8142.32"
               case 1'1
                 assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1
               case 
@@ -128376,169 +128208,169 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:8160.2-8166.5"
+    attribute \src "ls180.v:8148.2-8154.5"
     switch \main_spisdcard_clk_rise
-      attribute \src "ls180.v:8160.6-8160.29"
+      attribute \src "ls180.v:8148.6-8148.29"
       case 1'1
-        attribute \src "ls180.v:8161.3-8165.6"
+        attribute \src "ls180.v:8149.3-8153.6"
         switch \main_spisdcard_loopback
-          attribute \src "ls180.v:8161.7-8161.30"
+          attribute \src "ls180.v:8149.7-8149.30"
           case 1'1
             assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi }
-          attribute \src "ls180.v:8163.7-8163.11"
+          attribute \src "ls180.v:8151.7-8151.11"
           case 
             assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso }
         end
       case 
     end
-    attribute \src "ls180.v:8167.2-8169.5"
+    attribute \src "ls180.v:8155.2-8157.5"
     switch \main_spisdcard_miso_latch
-      attribute \src "ls180.v:8167.6-8167.31"
+      attribute \src "ls180.v:8155.6-8155.31"
       case 1'1
         assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data
       case 
     end
-    attribute \src "ls180.v:8171.2-8173.5"
+    attribute \src "ls180.v:8159.2-8161.5"
     switch \main_spisdcard_count_spimaster1_next_value_ce
-      attribute \src "ls180.v:8171.6-8171.51"
+      attribute \src "ls180.v:8159.6-8159.51"
       case 1'1
         assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value
       case 
     end
-    attribute \src "ls180.v:8174.2-8187.5"
+    attribute \src "ls180.v:8162.2-8175.5"
     switch \main_pwm0_enable
-      attribute \src "ls180.v:8174.6-8174.22"
+      attribute \src "ls180.v:8162.6-8162.22"
       case 1'1
-        assign $0\main_pwm0_counter[31:0] $add$ls180.v:8175$2595_Y
-        attribute \src "ls180.v:8176.3-8180.6"
-        switch $lt$ls180.v:8176$2596_Y
-          attribute \src "ls180.v:8176.7-8176.44"
+        assign $0\main_pwm0_counter[31:0] $add$ls180.v:8163$2583_Y
+        attribute \src "ls180.v:8164.3-8168.6"
+        switch $lt$ls180.v:8164$2584_Y
+          attribute \src "ls180.v:8164.7-8164.44"
           case 1'1
             assign $0\pwm[1:0] [0] 1'1
-          attribute \src "ls180.v:8178.7-8178.11"
+          attribute \src "ls180.v:8166.7-8166.11"
           case 
             assign $0\pwm[1:0] [0] 1'0
         end
-        attribute \src "ls180.v:8181.3-8183.6"
-        switch $ge$ls180.v:8181$2598_Y
-          attribute \src "ls180.v:8181.7-8181.55"
+        attribute \src "ls180.v:8169.3-8171.6"
+        switch $ge$ls180.v:8169$2586_Y
+          attribute \src "ls180.v:8169.7-8169.55"
           case 1'1
             assign $0\main_pwm0_counter[31:0] 0
           case 
         end
-      attribute \src "ls180.v:8184.6-8184.10"
+      attribute \src "ls180.v:8172.6-8172.10"
       case 
         assign $0\main_pwm0_counter[31:0] 0
         assign $0\pwm[1:0] [0] 1'0
     end
-    attribute \src "ls180.v:8188.2-8201.5"
+    attribute \src "ls180.v:8176.2-8189.5"
     switch \main_pwm1_enable
-      attribute \src "ls180.v:8188.6-8188.22"
+      attribute \src "ls180.v:8176.6-8176.22"
       case 1'1
-        assign $0\main_pwm1_counter[31:0] $add$ls180.v:8189$2599_Y
-        attribute \src "ls180.v:8190.3-8194.6"
-        switch $lt$ls180.v:8190$2600_Y
-          attribute \src "ls180.v:8190.7-8190.44"
+        assign $0\main_pwm1_counter[31:0] $add$ls180.v:8177$2587_Y
+        attribute \src "ls180.v:8178.3-8182.6"
+        switch $lt$ls180.v:8178$2588_Y
+          attribute \src "ls180.v:8178.7-8178.44"
           case 1'1
             assign $0\pwm[1:0] [1] 1'1
-          attribute \src "ls180.v:8192.7-8192.11"
+          attribute \src "ls180.v:8180.7-8180.11"
           case 
             assign $0\pwm[1:0] [1] 1'0
         end
-        attribute \src "ls180.v:8195.3-8197.6"
-        switch $ge$ls180.v:8195$2602_Y
-          attribute \src "ls180.v:8195.7-8195.55"
+        attribute \src "ls180.v:8183.3-8185.6"
+        switch $ge$ls180.v:8183$2590_Y
+          attribute \src "ls180.v:8183.7-8183.55"
           case 1'1
             assign $0\main_pwm1_counter[31:0] 0
           case 
         end
-      attribute \src "ls180.v:8198.6-8198.10"
+      attribute \src "ls180.v:8186.6-8186.10"
       case 
         assign $0\main_pwm1_counter[31:0] 0
         assign $0\pwm[1:0] [1] 1'0
     end
-    attribute \src "ls180.v:8202.2-8204.5"
-    switch $not$ls180.v:8202$2603_Y
-      attribute \src "ls180.v:8202.6-8202.32"
+    attribute \src "ls180.v:8190.2-8192.5"
+    switch $not$ls180.v:8190$2591_Y
+      attribute \src "ls180.v:8190.6-8190.32"
       case 1'1
-        assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8203$2604_Y
+        assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8191$2592_Y
       case 
     end
-    attribute \src "ls180.v:8208.2-8210.5"
+    attribute \src "ls180.v:8196.2-8198.5"
     switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce
-      attribute \src "ls180.v:8208.6-8208.57"
+      attribute \src "ls180.v:8196.6-8196.57"
       case 1'1
         assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value
       case 
     end
-    attribute \src "ls180.v:8212.2-8214.5"
+    attribute \src "ls180.v:8200.2-8202.5"
     switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce
-      attribute \src "ls180.v:8212.6-8212.57"
+      attribute \src "ls180.v:8200.6-8200.57"
       case 1'1
         assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value
       case 
     end
-    attribute \src "ls180.v:8215.2-8217.5"
+    attribute \src "ls180.v:8203.2-8205.5"
     switch \main_sdphy_cmdr_cmdr_pads_in_valid
-      attribute \src "ls180.v:8215.6-8215.40"
+      attribute \src "ls180.v:8203.6-8203.40"
       case 1'1
-        assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8216$2605_Y
+        assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8204$2593_Y
       case 
     end
-    attribute \src "ls180.v:8218.2-8220.5"
+    attribute \src "ls180.v:8206.2-8208.5"
     switch \main_sdphy_cmdr_cmdr_converter_source_ready
-      attribute \src "ls180.v:8218.6-8218.49"
+      attribute \src "ls180.v:8206.6-8206.49"
       case 1'1
         assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8221.2-8228.5"
+    attribute \src "ls180.v:8209.2-8216.5"
     switch \main_sdphy_cmdr_cmdr_converter_load_part
-      attribute \src "ls180.v:8221.6-8221.46"
+      attribute \src "ls180.v:8209.6-8209.46"
       case 1'1
-        attribute \src "ls180.v:8222.3-8227.6"
-        switch $or$ls180.v:8222$2607_Y
-          attribute \src "ls180.v:8222.7-8222.98"
+        attribute \src "ls180.v:8210.3-8215.6"
+        switch $or$ls180.v:8210$2595_Y
+          attribute \src "ls180.v:8210.7-8210.98"
           case 1'1
             assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
             assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1
-          attribute \src "ls180.v:8225.7-8225.11"
+          attribute \src "ls180.v:8213.7-8213.11"
           case 
-            assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8226$2608_Y
+            assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8214$2596_Y
         end
       case 
     end
-    attribute \src "ls180.v:8229.2-8242.5"
-    switch $and$ls180.v:8229$2609_Y
-      attribute \src "ls180.v:8229.6-8229.97"
+    attribute \src "ls180.v:8217.2-8230.5"
+    switch $and$ls180.v:8217$2597_Y
+      attribute \src "ls180.v:8217.6-8217.97"
       case 1'1
-        attribute \src "ls180.v:8230.3-8236.6"
-        switch $and$ls180.v:8230$2610_Y
-          attribute \src "ls180.v:8230.7-8230.94"
+        attribute \src "ls180.v:8218.3-8224.6"
+        switch $and$ls180.v:8218$2598_Y
+          attribute \src "ls180.v:8218.7-8218.94"
           case 1'1
             assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first
             assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last
-          attribute \src "ls180.v:8233.7-8233.11"
+          attribute \src "ls180.v:8221.7-8221.11"
           case 
             assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0
             assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0
         end
-      attribute \src "ls180.v:8237.6-8237.10"
+      attribute \src "ls180.v:8225.6-8225.10"
       case 
-        attribute \src "ls180.v:8238.3-8241.6"
-        switch $and$ls180.v:8238$2611_Y
-          attribute \src "ls180.v:8238.7-8238.94"
+        attribute \src "ls180.v:8226.3-8229.6"
+        switch $and$ls180.v:8226$2599_Y
+          attribute \src "ls180.v:8226.7-8226.94"
           case 1'1
-            assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8239$2612_Y
-            assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8240$2613_Y
+            assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8227$2600_Y
+            assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8228$2601_Y
           case 
         end
     end
-    attribute \src "ls180.v:8243.2-8270.5"
+    attribute \src "ls180.v:8231.2-8258.5"
     switch \main_sdphy_cmdr_cmdr_converter_load_part
-      attribute \src "ls180.v:8243.6-8243.46"
+      attribute \src "ls180.v:8231.6-8231.46"
       case 1'1
-        attribute \src "ls180.v:8244.3-8269.10"
+        attribute \src "ls180.v:8232.3-8257.10"
         switch \main_sdphy_cmdr_cmdr_converter_demux
           attribute \src "ls180.v:0.0-0.0"
           case 3'000
@@ -128568,16 +128400,16 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8271.2-8273.5"
+    attribute \src "ls180.v:8259.2-8261.5"
     switch \main_sdphy_cmdr_cmdr_converter_load_part
-      attribute \src "ls180.v:8271.6-8271.46"
+      attribute \src "ls180.v:8259.6-8259.46"
       case 1'1
-        assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8272$2614_Y
+        assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8260$2602_Y
       case 
     end
-    attribute \src "ls180.v:8274.2-8279.5"
-    switch $or$ls180.v:8274$2616_Y
-      attribute \src "ls180.v:8274.6-8274.88"
+    attribute \src "ls180.v:8262.2-8267.5"
+    switch $or$ls180.v:8262$2604_Y
+      attribute \src "ls180.v:8262.6-8262.88"
       case 1'1
         assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid
         assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first
@@ -128585,9 +128417,9 @@ module \ls180
         assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data
       case 
     end
-    attribute \src "ls180.v:8280.2-8285.5"
+    attribute \src "ls180.v:8268.2-8273.5"
     switch \main_sdphy_cmdr_cmdr_reset
-      attribute \src "ls180.v:8280.6-8280.32"
+      attribute \src "ls180.v:8268.6-8268.32"
       case 1'1
         assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0
         assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
@@ -128595,88 +128427,88 @@ module \ls180
         assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8287.2-8289.5"
+    attribute \src "ls180.v:8275.2-8277.5"
     switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0
-      attribute \src "ls180.v:8287.6-8287.58"
+      attribute \src "ls180.v:8275.6-8275.58"
       case 1'1
         assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0
       case 
     end
-    attribute \src "ls180.v:8290.2-8292.5"
+    attribute \src "ls180.v:8278.2-8280.5"
     switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1
-      attribute \src "ls180.v:8290.6-8290.60"
+      attribute \src "ls180.v:8278.6-8278.60"
       case 1'1
         assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1
       case 
     end
-    attribute \src "ls180.v:8293.2-8295.5"
+    attribute \src "ls180.v:8281.2-8283.5"
     switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2
-      attribute \src "ls180.v:8293.6-8293.63"
+      attribute \src "ls180.v:8281.6-8281.63"
       case 1'1
         assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2
       case 
     end
-    attribute \src "ls180.v:8296.2-8298.5"
+    attribute \src "ls180.v:8284.2-8286.5"
     switch \main_sdphy_dataw_crcr_pads_in_valid
-      attribute \src "ls180.v:8296.6-8296.41"
+      attribute \src "ls180.v:8284.6-8284.41"
       case 1'1
-        assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8297$2617_Y
+        assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8285$2605_Y
       case 
     end
-    attribute \src "ls180.v:8299.2-8301.5"
+    attribute \src "ls180.v:8287.2-8289.5"
     switch \main_sdphy_dataw_crcr_converter_source_ready
-      attribute \src "ls180.v:8299.6-8299.50"
+      attribute \src "ls180.v:8287.6-8287.50"
       case 1'1
         assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8302.2-8309.5"
+    attribute \src "ls180.v:8290.2-8297.5"
     switch \main_sdphy_dataw_crcr_converter_load_part
-      attribute \src "ls180.v:8302.6-8302.47"
+      attribute \src "ls180.v:8290.6-8290.47"
       case 1'1
-        attribute \src "ls180.v:8303.3-8308.6"
-        switch $or$ls180.v:8303$2619_Y
-          attribute \src "ls180.v:8303.7-8303.100"
+        attribute \src "ls180.v:8291.3-8296.6"
+        switch $or$ls180.v:8291$2607_Y
+          attribute \src "ls180.v:8291.7-8291.100"
           case 1'1
             assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
             assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1
-          attribute \src "ls180.v:8306.7-8306.11"
+          attribute \src "ls180.v:8294.7-8294.11"
           case 
-            assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8307$2620_Y
+            assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8295$2608_Y
         end
       case 
     end
-    attribute \src "ls180.v:8310.2-8323.5"
-    switch $and$ls180.v:8310$2621_Y
-      attribute \src "ls180.v:8310.6-8310.99"
+    attribute \src "ls180.v:8298.2-8311.5"
+    switch $and$ls180.v:8298$2609_Y
+      attribute \src "ls180.v:8298.6-8298.99"
       case 1'1
-        attribute \src "ls180.v:8311.3-8317.6"
-        switch $and$ls180.v:8311$2622_Y
-          attribute \src "ls180.v:8311.7-8311.96"
+        attribute \src "ls180.v:8299.3-8305.6"
+        switch $and$ls180.v:8299$2610_Y
+          attribute \src "ls180.v:8299.7-8299.96"
           case 1'1
             assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first
             assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last
-          attribute \src "ls180.v:8314.7-8314.11"
+          attribute \src "ls180.v:8302.7-8302.11"
           case 
             assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0
             assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0
         end
-      attribute \src "ls180.v:8318.6-8318.10"
+      attribute \src "ls180.v:8306.6-8306.10"
       case 
-        attribute \src "ls180.v:8319.3-8322.6"
-        switch $and$ls180.v:8319$2623_Y
-          attribute \src "ls180.v:8319.7-8319.96"
+        attribute \src "ls180.v:8307.3-8310.6"
+        switch $and$ls180.v:8307$2611_Y
+          attribute \src "ls180.v:8307.7-8307.96"
           case 1'1
-            assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8320$2624_Y
-            assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8321$2625_Y
+            assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8308$2612_Y
+            assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8309$2613_Y
           case 
         end
     end
-    attribute \src "ls180.v:8324.2-8351.5"
+    attribute \src "ls180.v:8312.2-8339.5"
     switch \main_sdphy_dataw_crcr_converter_load_part
-      attribute \src "ls180.v:8324.6-8324.47"
+      attribute \src "ls180.v:8312.6-8312.47"
       case 1'1
-        attribute \src "ls180.v:8325.3-8350.10"
+        attribute \src "ls180.v:8313.3-8338.10"
         switch \main_sdphy_dataw_crcr_converter_demux
           attribute \src "ls180.v:0.0-0.0"
           case 3'000
@@ -128706,16 +128538,16 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8352.2-8354.5"
+    attribute \src "ls180.v:8340.2-8342.5"
     switch \main_sdphy_dataw_crcr_converter_load_part
-      attribute \src "ls180.v:8352.6-8352.47"
+      attribute \src "ls180.v:8340.6-8340.47"
       case 1'1
-        assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8353$2626_Y
+        assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8341$2614_Y
       case 
     end
-    attribute \src "ls180.v:8355.2-8360.5"
-    switch $or$ls180.v:8355$2628_Y
-      attribute \src "ls180.v:8355.6-8355.90"
+    attribute \src "ls180.v:8343.2-8348.5"
+    switch $or$ls180.v:8343$2616_Y
+      attribute \src "ls180.v:8343.6-8343.90"
       case 1'1
         assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid
         assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first
@@ -128723,9 +128555,9 @@ module \ls180
         assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data
       case 
     end
-    attribute \src "ls180.v:8361.2-8366.5"
+    attribute \src "ls180.v:8349.2-8354.5"
     switch \main_sdphy_dataw_crcr_reset
-      attribute \src "ls180.v:8361.6-8361.33"
+      attribute \src "ls180.v:8349.6-8349.33"
       case 1'1
         assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0
         assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
@@ -128733,81 +128565,81 @@ module \ls180
         assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8368.2-8370.5"
+    attribute \src "ls180.v:8356.2-8358.5"
     switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce
-      attribute \src "ls180.v:8368.6-8368.63"
+      attribute \src "ls180.v:8356.6-8356.63"
       case 1'1
         assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value
       case 
     end
-    attribute \src "ls180.v:8372.2-8374.5"
+    attribute \src "ls180.v:8360.2-8362.5"
     switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce
-      attribute \src "ls180.v:8372.6-8372.52"
+      attribute \src "ls180.v:8360.6-8360.52"
       case 1'1
         assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value
       case 
     end
-    attribute \src "ls180.v:8375.2-8377.5"
+    attribute \src "ls180.v:8363.2-8365.5"
     switch \main_sdphy_datar_datar_pads_in_valid
-      attribute \src "ls180.v:8375.6-8375.42"
+      attribute \src "ls180.v:8363.6-8363.42"
       case 1'1
-        assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8376$2629_Y
+        assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8364$2617_Y
       case 
     end
-    attribute \src "ls180.v:8378.2-8380.5"
+    attribute \src "ls180.v:8366.2-8368.5"
     switch \main_sdphy_datar_datar_converter_source_ready
-      attribute \src "ls180.v:8378.6-8378.51"
+      attribute \src "ls180.v:8366.6-8366.51"
       case 1'1
         assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8381.2-8388.5"
+    attribute \src "ls180.v:8369.2-8376.5"
     switch \main_sdphy_datar_datar_converter_load_part
-      attribute \src "ls180.v:8381.6-8381.48"
+      attribute \src "ls180.v:8369.6-8369.48"
       case 1'1
-        attribute \src "ls180.v:8382.3-8387.6"
-        switch $or$ls180.v:8382$2631_Y
-          attribute \src "ls180.v:8382.7-8382.102"
+        attribute \src "ls180.v:8370.3-8375.6"
+        switch $or$ls180.v:8370$2619_Y
+          attribute \src "ls180.v:8370.7-8370.102"
           case 1'1
             assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0
             assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1
-          attribute \src "ls180.v:8385.7-8385.11"
+          attribute \src "ls180.v:8373.7-8373.11"
           case 
-            assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8386$2632_Y
+            assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8374$2620_Y
         end
       case 
     end
-    attribute \src "ls180.v:8389.2-8402.5"
-    switch $and$ls180.v:8389$2633_Y
-      attribute \src "ls180.v:8389.6-8389.101"
+    attribute \src "ls180.v:8377.2-8390.5"
+    switch $and$ls180.v:8377$2621_Y
+      attribute \src "ls180.v:8377.6-8377.101"
       case 1'1
-        attribute \src "ls180.v:8390.3-8396.6"
-        switch $and$ls180.v:8390$2634_Y
-          attribute \src "ls180.v:8390.7-8390.98"
+        attribute \src "ls180.v:8378.3-8384.6"
+        switch $and$ls180.v:8378$2622_Y
+          attribute \src "ls180.v:8378.7-8378.98"
           case 1'1
             assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first
             assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last
-          attribute \src "ls180.v:8393.7-8393.11"
+          attribute \src "ls180.v:8381.7-8381.11"
           case 
             assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0
             assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0
         end
-      attribute \src "ls180.v:8397.6-8397.10"
+      attribute \src "ls180.v:8385.6-8385.10"
       case 
-        attribute \src "ls180.v:8398.3-8401.6"
-        switch $and$ls180.v:8398$2635_Y
-          attribute \src "ls180.v:8398.7-8398.98"
+        attribute \src "ls180.v:8386.3-8389.6"
+        switch $and$ls180.v:8386$2623_Y
+          attribute \src "ls180.v:8386.7-8386.98"
           case 1'1
-            assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8399$2636_Y
-            assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8400$2637_Y
+            assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8387$2624_Y
+            assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8388$2625_Y
           case 
         end
     end
-    attribute \src "ls180.v:8403.2-8412.5"
+    attribute \src "ls180.v:8391.2-8400.5"
     switch \main_sdphy_datar_datar_converter_load_part
-      attribute \src "ls180.v:8403.6-8403.48"
+      attribute \src "ls180.v:8391.6-8391.48"
       case 1'1
-        attribute \src "ls180.v:8404.3-8411.10"
+        attribute \src "ls180.v:8392.3-8399.10"
         switch \main_sdphy_datar_datar_converter_demux
           attribute \src "ls180.v:0.0-0.0"
           case 1'0
@@ -128819,16 +128651,16 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8413.2-8415.5"
+    attribute \src "ls180.v:8401.2-8403.5"
     switch \main_sdphy_datar_datar_converter_load_part
-      attribute \src "ls180.v:8413.6-8413.48"
+      attribute \src "ls180.v:8401.6-8401.48"
       case 1'1
-        assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8414$2638_Y
+        assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8402$2626_Y
       case 
     end
-    attribute \src "ls180.v:8416.2-8421.5"
-    switch $or$ls180.v:8416$2640_Y
-      attribute \src "ls180.v:8416.6-8416.92"
+    attribute \src "ls180.v:8404.2-8409.5"
+    switch $or$ls180.v:8404$2628_Y
+      attribute \src "ls180.v:8404.6-8404.92"
       case 1'1
         assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid
         assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first
@@ -128836,9 +128668,9 @@ module \ls180
         assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data
       case 
     end
-    attribute \src "ls180.v:8422.2-8427.5"
+    attribute \src "ls180.v:8410.2-8415.5"
     switch \main_sdphy_datar_datar_reset
-      attribute \src "ls180.v:8422.6-8422.34"
+      attribute \src "ls180.v:8410.6-8410.34"
       case 1'1
         assign $0\main_sdphy_datar_datar_run[0:0] 1'0
         assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0
@@ -128846,434 +128678,434 @@ module \ls180
         assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8429.2-8431.5"
+    attribute \src "ls180.v:8417.2-8419.5"
     switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0
-      attribute \src "ls180.v:8429.6-8429.60"
+      attribute \src "ls180.v:8417.6-8417.60"
       case 1'1
         assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0
       case 
     end
-    attribute \src "ls180.v:8432.2-8434.5"
+    attribute \src "ls180.v:8420.2-8422.5"
     switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1
-      attribute \src "ls180.v:8432.6-8432.62"
+      attribute \src "ls180.v:8420.6-8420.62"
       case 1'1
         assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1
       case 
     end
-    attribute \src "ls180.v:8435.2-8437.5"
+    attribute \src "ls180.v:8423.2-8425.5"
     switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2
-      attribute \src "ls180.v:8435.6-8435.66"
+      attribute \src "ls180.v:8423.6-8423.66"
       case 1'1
         assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2
       case 
     end
-    attribute \src "ls180.v:8438.2-8444.5"
+    attribute \src "ls180.v:8426.2-8432.5"
     switch \main_sdcore_crc7_inserter_clr
-      attribute \src "ls180.v:8438.6-8438.35"
+      attribute \src "ls180.v:8426.6-8426.35"
       case 1'1
         assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000
-      attribute \src "ls180.v:8440.6-8440.10"
+      attribute \src "ls180.v:8428.6-8428.10"
       case 
-        attribute \src "ls180.v:8441.3-8443.6"
+        attribute \src "ls180.v:8429.3-8431.6"
         switch \main_sdcore_crc7_inserter_enable
-          attribute \src "ls180.v:8441.7-8441.39"
+          attribute \src "ls180.v:8429.7-8429.39"
           case 1'1
             assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40
           case 
         end
     end
-    attribute \src "ls180.v:8445.2-8451.5"
+    attribute \src "ls180.v:8433.2-8439.5"
     switch \main_sdcore_crc16_inserter_crc0_clr
-      attribute \src "ls180.v:8445.6-8445.41"
+      attribute \src "ls180.v:8433.6-8433.41"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8447.6-8447.10"
+      attribute \src "ls180.v:8435.6-8435.10"
       case 
-        attribute \src "ls180.v:8448.3-8450.6"
+        attribute \src "ls180.v:8436.3-8438.6"
         switch \main_sdcore_crc16_inserter_crc0_enable
-          attribute \src "ls180.v:8448.7-8448.45"
+          attribute \src "ls180.v:8436.7-8436.45"
           case 1'1
             assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8452.2-8458.5"
+    attribute \src "ls180.v:8440.2-8446.5"
     switch \main_sdcore_crc16_inserter_crc1_clr
-      attribute \src "ls180.v:8452.6-8452.41"
+      attribute \src "ls180.v:8440.6-8440.41"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8454.6-8454.10"
+      attribute \src "ls180.v:8442.6-8442.10"
       case 
-        attribute \src "ls180.v:8455.3-8457.6"
+        attribute \src "ls180.v:8443.3-8445.6"
         switch \main_sdcore_crc16_inserter_crc1_enable
-          attribute \src "ls180.v:8455.7-8455.45"
+          attribute \src "ls180.v:8443.7-8443.45"
           case 1'1
             assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8459.2-8465.5"
+    attribute \src "ls180.v:8447.2-8453.5"
     switch \main_sdcore_crc16_inserter_crc2_clr
-      attribute \src "ls180.v:8459.6-8459.41"
+      attribute \src "ls180.v:8447.6-8447.41"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8461.6-8461.10"
+      attribute \src "ls180.v:8449.6-8449.10"
       case 
-        attribute \src "ls180.v:8462.3-8464.6"
+        attribute \src "ls180.v:8450.3-8452.6"
         switch \main_sdcore_crc16_inserter_crc2_enable
-          attribute \src "ls180.v:8462.7-8462.45"
+          attribute \src "ls180.v:8450.7-8450.45"
           case 1'1
             assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8466.2-8472.5"
+    attribute \src "ls180.v:8454.2-8460.5"
     switch \main_sdcore_crc16_inserter_crc3_clr
-      attribute \src "ls180.v:8466.6-8466.41"
+      attribute \src "ls180.v:8454.6-8454.41"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8468.6-8468.10"
+      attribute \src "ls180.v:8456.6-8456.10"
       case 
-        attribute \src "ls180.v:8469.3-8471.6"
+        attribute \src "ls180.v:8457.3-8459.6"
         switch \main_sdcore_crc16_inserter_crc3_enable
-          attribute \src "ls180.v:8469.7-8469.45"
+          attribute \src "ls180.v:8457.7-8457.45"
           case 1'1
             assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8474.2-8476.5"
+    attribute \src "ls180.v:8462.2-8464.5"
     switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0
-      attribute \src "ls180.v:8474.6-8474.82"
+      attribute \src "ls180.v:8462.6-8462.82"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0
       case 
     end
-    attribute \src "ls180.v:8477.2-8479.5"
+    attribute \src "ls180.v:8465.2-8467.5"
     switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1
-      attribute \src "ls180.v:8477.6-8477.82"
+      attribute \src "ls180.v:8465.6-8465.82"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1
       case 
     end
-    attribute \src "ls180.v:8480.2-8482.5"
+    attribute \src "ls180.v:8468.2-8470.5"
     switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2
-      attribute \src "ls180.v:8480.6-8480.82"
+      attribute \src "ls180.v:8468.6-8468.82"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2
       case 
     end
-    attribute \src "ls180.v:8483.2-8485.5"
+    attribute \src "ls180.v:8471.2-8473.5"
     switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3
-      attribute \src "ls180.v:8483.6-8483.82"
+      attribute \src "ls180.v:8471.6-8471.82"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3
       case 
     end
-    attribute \src "ls180.v:8486.2-8488.5"
+    attribute \src "ls180.v:8474.2-8476.5"
     switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4
-      attribute \src "ls180.v:8486.6-8486.78"
+      attribute \src "ls180.v:8474.6-8474.78"
       case 1'1
         assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4
       case 
     end
-    attribute \src "ls180.v:8489.2-8491.5"
-    switch $and$ls180.v:8489$2641_Y
-      attribute \src "ls180.v:8489.6-8489.83"
+    attribute \src "ls180.v:8477.2-8479.5"
+    switch $and$ls180.v:8477$2629_Y
+      attribute \src "ls180.v:8477.6-8477.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc
       case 
     end
-    attribute \src "ls180.v:8492.2-8494.5"
-    switch $and$ls180.v:8492$2642_Y
-      attribute \src "ls180.v:8492.6-8492.83"
+    attribute \src "ls180.v:8480.2-8482.5"
+    switch $and$ls180.v:8480$2630_Y
+      attribute \src "ls180.v:8480.6-8480.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc
       case 
     end
-    attribute \src "ls180.v:8495.2-8497.5"
-    switch $and$ls180.v:8495$2643_Y
-      attribute \src "ls180.v:8495.6-8495.83"
+    attribute \src "ls180.v:8483.2-8485.5"
+    switch $and$ls180.v:8483$2631_Y
+      attribute \src "ls180.v:8483.6-8483.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc
       case 
     end
-    attribute \src "ls180.v:8498.2-8500.5"
-    switch $and$ls180.v:8498$2644_Y
-      attribute \src "ls180.v:8498.6-8498.83"
+    attribute \src "ls180.v:8486.2-8488.5"
+    switch $and$ls180.v:8486$2632_Y
+      attribute \src "ls180.v:8486.6-8486.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc
       case 
     end
-    attribute \src "ls180.v:8501.2-8505.5"
-    switch $and$ls180.v:8501$2645_Y
-      attribute \src "ls180.v:8501.6-8501.83"
+    attribute \src "ls180.v:8489.2-8493.5"
+    switch $and$ls180.v:8489$2633_Y
+      attribute \src "ls180.v:8489.6-8489.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] }
         assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13]
         assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12]
       case 
     end
-    attribute \src "ls180.v:8506.2-8510.5"
-    switch $and$ls180.v:8506$2646_Y
-      attribute \src "ls180.v:8506.6-8506.83"
+    attribute \src "ls180.v:8494.2-8498.5"
+    switch $and$ls180.v:8494$2634_Y
+      attribute \src "ls180.v:8494.6-8494.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] }
         assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13]
         assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12]
       case 
     end
-    attribute \src "ls180.v:8511.2-8515.5"
-    switch $and$ls180.v:8511$2647_Y
-      attribute \src "ls180.v:8511.6-8511.83"
+    attribute \src "ls180.v:8499.2-8503.5"
+    switch $and$ls180.v:8499$2635_Y
+      attribute \src "ls180.v:8499.6-8499.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] }
         assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13]
         assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12]
       case 
     end
-    attribute \src "ls180.v:8516.2-8520.5"
-    switch $and$ls180.v:8516$2648_Y
-      attribute \src "ls180.v:8516.6-8516.83"
+    attribute \src "ls180.v:8504.2-8508.5"
+    switch $and$ls180.v:8504$2636_Y
+      attribute \src "ls180.v:8504.6-8504.83"
       case 1'1
         assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] }
         assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13]
         assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12]
       case 
     end
-    attribute \src "ls180.v:8521.2-8529.5"
-    switch $and$ls180.v:8521$2649_Y
-      attribute \src "ls180.v:8521.6-8521.83"
+    attribute \src "ls180.v:8509.2-8517.5"
+    switch $and$ls180.v:8509$2637_Y
+      attribute \src "ls180.v:8509.6-8509.83"
       case 1'1
-        attribute \src "ls180.v:8522.3-8528.6"
+        attribute \src "ls180.v:8510.3-8516.6"
         switch \main_sdcore_crc16_checker_sink_last
-          attribute \src "ls180.v:8522.7-8522.42"
+          attribute \src "ls180.v:8510.7-8510.42"
           case 1'1
             assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000
-          attribute \src "ls180.v:8524.7-8524.11"
+          attribute \src "ls180.v:8512.7-8512.11"
           case 
-            attribute \src "ls180.v:8525.4-8527.7"
-            switch $ne$ls180.v:8525$2650_Y
-              attribute \src "ls180.v:8525.8-8525.48"
+            attribute \src "ls180.v:8513.4-8515.7"
+            switch $ne$ls180.v:8513$2638_Y
+              attribute \src "ls180.v:8513.8-8513.48"
               case 1'1
-                assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8526$2651_Y
+                assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8514$2639_Y
               case 
             end
         end
       case 
     end
-    attribute \src "ls180.v:8530.2-8536.5"
+    attribute \src "ls180.v:8518.2-8524.5"
     switch \main_sdcore_crc16_checker_crc0_clr
-      attribute \src "ls180.v:8530.6-8530.40"
+      attribute \src "ls180.v:8518.6-8518.40"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8532.6-8532.10"
+      attribute \src "ls180.v:8520.6-8520.10"
       case 
-        attribute \src "ls180.v:8533.3-8535.6"
+        attribute \src "ls180.v:8521.3-8523.6"
         switch \main_sdcore_crc16_checker_crc0_enable
-          attribute \src "ls180.v:8533.7-8533.44"
+          attribute \src "ls180.v:8521.7-8521.44"
           case 1'1
             assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8537.2-8543.5"
+    attribute \src "ls180.v:8525.2-8531.5"
     switch \main_sdcore_crc16_checker_crc1_clr
-      attribute \src "ls180.v:8537.6-8537.40"
+      attribute \src "ls180.v:8525.6-8525.40"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8539.6-8539.10"
+      attribute \src "ls180.v:8527.6-8527.10"
       case 
-        attribute \src "ls180.v:8540.3-8542.6"
+        attribute \src "ls180.v:8528.3-8530.6"
         switch \main_sdcore_crc16_checker_crc1_enable
-          attribute \src "ls180.v:8540.7-8540.44"
+          attribute \src "ls180.v:8528.7-8528.44"
           case 1'1
             assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8544.2-8550.5"
+    attribute \src "ls180.v:8532.2-8538.5"
     switch \main_sdcore_crc16_checker_crc2_clr
-      attribute \src "ls180.v:8544.6-8544.40"
+      attribute \src "ls180.v:8532.6-8532.40"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8546.6-8546.10"
+      attribute \src "ls180.v:8534.6-8534.10"
       case 
-        attribute \src "ls180.v:8547.3-8549.6"
+        attribute \src "ls180.v:8535.3-8537.6"
         switch \main_sdcore_crc16_checker_crc2_enable
-          attribute \src "ls180.v:8547.7-8547.44"
+          attribute \src "ls180.v:8535.7-8535.44"
           case 1'1
             assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8551.2-8557.5"
+    attribute \src "ls180.v:8539.2-8545.5"
     switch \main_sdcore_crc16_checker_crc3_clr
-      attribute \src "ls180.v:8551.6-8551.40"
+      attribute \src "ls180.v:8539.6-8539.40"
       case 1'1
         assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
-      attribute \src "ls180.v:8553.6-8553.10"
+      attribute \src "ls180.v:8541.6-8541.10"
       case 
-        attribute \src "ls180.v:8554.3-8556.6"
+        attribute \src "ls180.v:8542.3-8544.6"
         switch \main_sdcore_crc16_checker_crc3_enable
-          attribute \src "ls180.v:8554.7-8554.44"
+          attribute \src "ls180.v:8542.7-8542.44"
           case 1'1
             assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2
           case 
         end
     end
-    attribute \src "ls180.v:8559.2-8561.5"
+    attribute \src "ls180.v:8547.2-8549.5"
     switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0
-      attribute \src "ls180.v:8559.6-8559.52"
+      attribute \src "ls180.v:8547.6-8547.52"
       case 1'1
         assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0
       case 
     end
-    attribute \src "ls180.v:8562.2-8564.5"
+    attribute \src "ls180.v:8550.2-8552.5"
     switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1
-      attribute \src "ls180.v:8562.6-8562.53"
+      attribute \src "ls180.v:8550.6-8550.53"
       case 1'1
         assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1
       case 
     end
-    attribute \src "ls180.v:8565.2-8567.5"
+    attribute \src "ls180.v:8553.2-8555.5"
     switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2
-      attribute \src "ls180.v:8565.6-8565.53"
+      attribute \src "ls180.v:8553.6-8553.53"
       case 1'1
         assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2
       case 
     end
-    attribute \src "ls180.v:8568.2-8570.5"
+    attribute \src "ls180.v:8556.2-8558.5"
     switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3
-      attribute \src "ls180.v:8568.6-8568.54"
+      attribute \src "ls180.v:8556.6-8556.54"
       case 1'1
         assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3
       case 
     end
-    attribute \src "ls180.v:8571.2-8573.5"
+    attribute \src "ls180.v:8559.2-8561.5"
     switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4
-      attribute \src "ls180.v:8571.6-8571.53"
+      attribute \src "ls180.v:8559.6-8559.53"
       case 1'1
         assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4
       case 
     end
-    attribute \src "ls180.v:8574.2-8576.5"
+    attribute \src "ls180.v:8562.2-8564.5"
     switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5
-      attribute \src "ls180.v:8574.6-8574.55"
+      attribute \src "ls180.v:8562.6-8562.55"
       case 1'1
         assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5
       case 
     end
-    attribute \src "ls180.v:8577.2-8579.5"
+    attribute \src "ls180.v:8565.2-8567.5"
     switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6
-      attribute \src "ls180.v:8577.6-8577.54"
+      attribute \src "ls180.v:8565.6-8565.54"
       case 1'1
         assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6
       case 
     end
-    attribute \src "ls180.v:8580.2-8582.5"
+    attribute \src "ls180.v:8568.2-8570.5"
     switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7
-      attribute \src "ls180.v:8580.6-8580.56"
+      attribute \src "ls180.v:8568.6-8568.56"
       case 1'1
         assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7
       case 
     end
-    attribute \src "ls180.v:8583.2-8585.5"
+    attribute \src "ls180.v:8571.2-8573.5"
     switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8
-      attribute \src "ls180.v:8583.6-8583.63"
+      attribute \src "ls180.v:8571.6-8571.63"
       case 1'1
         assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8
       case 
     end
-    attribute \src "ls180.v:8586.2-8588.5"
-    switch $and$ls180.v:8586$2654_Y
-      attribute \src "ls180.v:8586.6-8586.120"
+    attribute \src "ls180.v:8574.2-8576.5"
+    switch $and$ls180.v:8574$2642_Y
+      attribute \src "ls180.v:8574.6-8574.120"
       case 1'1
-        assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8587$2655_Y
+        assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8575$2643_Y
       case 
     end
-    attribute \src "ls180.v:8589.2-8591.5"
+    attribute \src "ls180.v:8577.2-8579.5"
     switch \main_sdblock2mem_fifo_do_read
-      attribute \src "ls180.v:8589.6-8589.35"
+      attribute \src "ls180.v:8577.6-8577.35"
       case 1'1
-        assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8590$2656_Y
+        assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8578$2644_Y
       case 
     end
-    attribute \src "ls180.v:8592.2-8600.5"
-    switch $and$ls180.v:8592$2659_Y
-      attribute \src "ls180.v:8592.6-8592.120"
+    attribute \src "ls180.v:8580.2-8588.5"
+    switch $and$ls180.v:8580$2647_Y
+      attribute \src "ls180.v:8580.6-8580.120"
       case 1'1
-        attribute \src "ls180.v:8593.3-8595.6"
-        switch $not$ls180.v:8593$2660_Y
-          attribute \src "ls180.v:8593.7-8593.39"
+        attribute \src "ls180.v:8581.3-8583.6"
+        switch $not$ls180.v:8581$2648_Y
+          attribute \src "ls180.v:8581.7-8581.39"
           case 1'1
-            assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8594$2661_Y
+            assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8582$2649_Y
           case 
         end
-      attribute \src "ls180.v:8596.6-8596.10"
+      attribute \src "ls180.v:8584.6-8584.10"
       case 
-        attribute \src "ls180.v:8597.3-8599.6"
+        attribute \src "ls180.v:8585.3-8587.6"
         switch \main_sdblock2mem_fifo_do_read
-          attribute \src "ls180.v:8597.7-8597.36"
+          attribute \src "ls180.v:8585.7-8585.36"
           case 1'1
-            assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8598$2662_Y
+            assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8586$2650_Y
           case 
         end
     end
-    attribute \src "ls180.v:8601.2-8603.5"
+    attribute \src "ls180.v:8589.2-8591.5"
     switch \main_sdblock2mem_converter_source_ready
-      attribute \src "ls180.v:8601.6-8601.45"
+      attribute \src "ls180.v:8589.6-8589.45"
       case 1'1
         assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:8604.2-8611.5"
+    attribute \src "ls180.v:8592.2-8599.5"
     switch \main_sdblock2mem_converter_load_part
-      attribute \src "ls180.v:8604.6-8604.42"
+      attribute \src "ls180.v:8592.6-8592.42"
       case 1'1
-        attribute \src "ls180.v:8605.3-8610.6"
-        switch $or$ls180.v:8605$2664_Y
-          attribute \src "ls180.v:8605.7-8605.90"
+        attribute \src "ls180.v:8593.3-8598.6"
+        switch $or$ls180.v:8593$2652_Y
+          attribute \src "ls180.v:8593.7-8593.90"
           case 1'1
             assign $0\main_sdblock2mem_converter_demux[1:0] 2'00
             assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1
-          attribute \src "ls180.v:8608.7-8608.11"
+          attribute \src "ls180.v:8596.7-8596.11"
           case 
-            assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8609$2665_Y
+            assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8597$2653_Y
         end
       case 
     end
-    attribute \src "ls180.v:8612.2-8625.5"
-    switch $and$ls180.v:8612$2666_Y
-      attribute \src "ls180.v:8612.6-8612.89"
+    attribute \src "ls180.v:8600.2-8613.5"
+    switch $and$ls180.v:8600$2654_Y
+      attribute \src "ls180.v:8600.6-8600.89"
       case 1'1
-        attribute \src "ls180.v:8613.3-8619.6"
-        switch $and$ls180.v:8613$2667_Y
-          attribute \src "ls180.v:8613.7-8613.86"
+        attribute \src "ls180.v:8601.3-8607.6"
+        switch $and$ls180.v:8601$2655_Y
+          attribute \src "ls180.v:8601.7-8601.86"
           case 1'1
             assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first
             assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last
-          attribute \src "ls180.v:8616.7-8616.11"
+          attribute \src "ls180.v:8604.7-8604.11"
           case 
             assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0
             assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0
         end
-      attribute \src "ls180.v:8620.6-8620.10"
+      attribute \src "ls180.v:8608.6-8608.10"
       case 
-        attribute \src "ls180.v:8621.3-8624.6"
-        switch $and$ls180.v:8621$2668_Y
-          attribute \src "ls180.v:8621.7-8621.86"
+        attribute \src "ls180.v:8609.3-8612.6"
+        switch $and$ls180.v:8609$2656_Y
+          attribute \src "ls180.v:8609.7-8609.86"
           case 1'1
-            assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8622$2669_Y
-            assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8623$2670_Y
+            assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8610$2657_Y
+            assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8611$2658_Y
           case 
         end
     end
-    attribute \src "ls180.v:8626.2-8641.5"
+    attribute \src "ls180.v:8614.2-8629.5"
     switch \main_sdblock2mem_converter_load_part
-      attribute \src "ls180.v:8626.6-8626.42"
+      attribute \src "ls180.v:8614.6-8614.42"
       case 1'1
-        attribute \src "ls180.v:8627.3-8640.10"
+        attribute \src "ls180.v:8615.3-8628.10"
         switch \main_sdblock2mem_converter_demux
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
@@ -129291,153 +129123,153 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8642.2-8644.5"
+    attribute \src "ls180.v:8630.2-8632.5"
     switch \main_sdblock2mem_converter_load_part
-      attribute \src "ls180.v:8642.6-8642.42"
+      attribute \src "ls180.v:8630.6-8630.42"
       case 1'1
-        assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8643$2671_Y
+        assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8631$2659_Y
       case 
     end
-    attribute \src "ls180.v:8646.2-8648.5"
+    attribute \src "ls180.v:8634.2-8636.5"
     switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce
-      attribute \src "ls180.v:8646.6-8646.76"
+      attribute \src "ls180.v:8634.6-8634.76"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value
       case 
     end
-    attribute \src "ls180.v:8649.2-8652.5"
+    attribute \src "ls180.v:8637.2-8640.5"
     switch \main_sdblock2mem_wishbonedmawriter_reset
-      attribute \src "ls180.v:8649.6-8649.46"
+      attribute \src "ls180.v:8637.6-8637.46"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0
         assign $0\builder_sdblock2memdma_state[1:0] 2'00
       case 
     end
-    attribute \src "ls180.v:8654.2-8656.5"
+    attribute \src "ls180.v:8642.2-8644.5"
     switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce
-      attribute \src "ls180.v:8654.6-8654.64"
+      attribute \src "ls180.v:8642.6-8642.64"
       case 1'1
         assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value
       case 
     end
-    attribute \src "ls180.v:8658.2-8660.5"
+    attribute \src "ls180.v:8646.2-8648.5"
     switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce
-      attribute \src "ls180.v:8658.6-8658.76"
+      attribute \src "ls180.v:8646.6-8646.76"
       case 1'1
         assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value
       case 
     end
-    attribute \src "ls180.v:8661.2-8664.5"
+    attribute \src "ls180.v:8649.2-8652.5"
     switch \main_sdmem2block_dma_reset
-      attribute \src "ls180.v:8661.6-8661.32"
+      attribute \src "ls180.v:8649.6-8649.32"
       case 1'1
         assign $0\main_sdmem2block_dma_offset[31:0] 0
         assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
       case 
     end
-    attribute \src "ls180.v:8665.2-8671.5"
-    switch $and$ls180.v:8665$2672_Y
-      attribute \src "ls180.v:8665.6-8665.89"
+    attribute \src "ls180.v:8653.2-8659.5"
+    switch $and$ls180.v:8653$2660_Y
+      attribute \src "ls180.v:8653.6-8653.89"
       case 1'1
-        attribute \src "ls180.v:8666.3-8670.6"
+        attribute \src "ls180.v:8654.3-8658.6"
         switch \main_sdmem2block_converter_last
-          attribute \src "ls180.v:8666.7-8666.38"
+          attribute \src "ls180.v:8654.7-8654.38"
           case 1'1
             assign $0\main_sdmem2block_converter_mux[1:0] 2'00
-          attribute \src "ls180.v:8668.7-8668.11"
+          attribute \src "ls180.v:8656.7-8656.11"
           case 
-            assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8669$2673_Y
+            assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8657$2661_Y
         end
       case 
     end
-    attribute \src "ls180.v:8672.2-8674.5"
-    switch $and$ls180.v:8672$2676_Y
-      attribute \src "ls180.v:8672.6-8672.120"
+    attribute \src "ls180.v:8660.2-8662.5"
+    switch $and$ls180.v:8660$2664_Y
+      attribute \src "ls180.v:8660.6-8660.120"
       case 1'1
-        assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8673$2677_Y
+        assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8661$2665_Y
       case 
     end
-    attribute \src "ls180.v:8675.2-8677.5"
+    attribute \src "ls180.v:8663.2-8665.5"
     switch \main_sdmem2block_fifo_do_read
-      attribute \src "ls180.v:8675.6-8675.35"
+      attribute \src "ls180.v:8663.6-8663.35"
       case 1'1
-        assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8676$2678_Y
+        assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8664$2666_Y
       case 
     end
-    attribute \src "ls180.v:8678.2-8686.5"
-    switch $and$ls180.v:8678$2681_Y
-      attribute \src "ls180.v:8678.6-8678.120"
+    attribute \src "ls180.v:8666.2-8674.5"
+    switch $and$ls180.v:8666$2669_Y
+      attribute \src "ls180.v:8666.6-8666.120"
       case 1'1
-        attribute \src "ls180.v:8679.3-8681.6"
-        switch $not$ls180.v:8679$2682_Y
-          attribute \src "ls180.v:8679.7-8679.39"
+        attribute \src "ls180.v:8667.3-8669.6"
+        switch $not$ls180.v:8667$2670_Y
+          attribute \src "ls180.v:8667.7-8667.39"
           case 1'1
-            assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8680$2683_Y
+            assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8668$2671_Y
           case 
         end
-      attribute \src "ls180.v:8682.6-8682.10"
+      attribute \src "ls180.v:8670.6-8670.10"
       case 
-        attribute \src "ls180.v:8683.3-8685.6"
+        attribute \src "ls180.v:8671.3-8673.6"
         switch \main_sdmem2block_fifo_do_read
-          attribute \src "ls180.v:8683.7-8683.36"
+          attribute \src "ls180.v:8671.7-8671.36"
           case 1'1
-            assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8684$2684_Y
+            assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8672$2672_Y
           case 
         end
     end
-    attribute \src "ls180.v:8688.2-8690.5"
+    attribute \src "ls180.v:8676.2-8678.5"
     switch \builder_libresocsim_dat_w_next_value_ce0
-      attribute \src "ls180.v:8688.6-8688.46"
+      attribute \src "ls180.v:8676.6-8676.46"
       case 1'1
         assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0
       case 
     end
-    attribute \src "ls180.v:8691.2-8693.5"
+    attribute \src "ls180.v:8679.2-8681.5"
     switch \builder_libresocsim_adr_next_value_ce1
-      attribute \src "ls180.v:8691.6-8691.44"
+      attribute \src "ls180.v:8679.6-8679.44"
       case 1'1
         assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1
       case 
     end
-    attribute \src "ls180.v:8694.2-8696.5"
+    attribute \src "ls180.v:8682.2-8684.5"
     switch \builder_libresocsim_we_next_value_ce2
-      attribute \src "ls180.v:8694.6-8694.43"
+      attribute \src "ls180.v:8682.6-8682.43"
       case 1'1
         assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2
       case 
     end
-    attribute \src "ls180.v:8697.2-8793.9"
+    attribute \src "ls180.v:8685.2-8781.9"
     switch \builder_grant
       attribute \src "ls180.v:0.0-0.0"
       case 3'000
-        attribute \src "ls180.v:8699.4-8715.7"
-        switch $not$ls180.v:8699$2685_Y
-          attribute \src "ls180.v:8699.8-8699.29"
+        attribute \src "ls180.v:8687.4-8703.7"
+        switch $not$ls180.v:8687$2673_Y
+          attribute \src "ls180.v:8687.8-8687.29"
           case 1'1
-            attribute \src "ls180.v:8700.5-8714.8"
+            attribute \src "ls180.v:8688.5-8702.8"
             switch \builder_request [1]
-              attribute \src "ls180.v:8700.9-8700.27"
+              attribute \src "ls180.v:8688.9-8688.27"
               case 1'1
                 assign $0\builder_grant[2:0] 3'001
-              attribute \src "ls180.v:8702.9-8702.13"
+              attribute \src "ls180.v:8690.9-8690.13"
               case 
-                attribute \src "ls180.v:8703.6-8713.9"
+                attribute \src "ls180.v:8691.6-8701.9"
                 switch \builder_request [2]
-                  attribute \src "ls180.v:8703.10-8703.28"
+                  attribute \src "ls180.v:8691.10-8691.28"
                   case 1'1
                     assign $0\builder_grant[2:0] 3'010
-                  attribute \src "ls180.v:8705.10-8705.14"
+                  attribute \src "ls180.v:8693.10-8693.14"
                   case 
-                    attribute \src "ls180.v:8706.7-8712.10"
+                    attribute \src "ls180.v:8694.7-8700.10"
                     switch \builder_request [3]
-                      attribute \src "ls180.v:8706.11-8706.29"
+                      attribute \src "ls180.v:8694.11-8694.29"
                       case 1'1
                         assign $0\builder_grant[2:0] 3'011
-                      attribute \src "ls180.v:8708.11-8708.15"
+                      attribute \src "ls180.v:8696.11-8696.15"
                       case 
-                        attribute \src "ls180.v:8709.8-8711.11"
+                        attribute \src "ls180.v:8697.8-8699.11"
                         switch \builder_request [4]
-                          attribute \src "ls180.v:8709.12-8709.30"
+                          attribute \src "ls180.v:8697.12-8697.30"
                           case 1'1
                             assign $0\builder_grant[2:0] 3'100
                           case 
@@ -129449,34 +129281,34 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
-        attribute \src "ls180.v:8718.4-8734.7"
-        switch $not$ls180.v:8718$2686_Y
-          attribute \src "ls180.v:8718.8-8718.29"
+        attribute \src "ls180.v:8706.4-8722.7"
+        switch $not$ls180.v:8706$2674_Y
+          attribute \src "ls180.v:8706.8-8706.29"
           case 1'1
-            attribute \src "ls180.v:8719.5-8733.8"
+            attribute \src "ls180.v:8707.5-8721.8"
             switch \builder_request [2]
-              attribute \src "ls180.v:8719.9-8719.27"
+              attribute \src "ls180.v:8707.9-8707.27"
               case 1'1
                 assign $0\builder_grant[2:0] 3'010
-              attribute \src "ls180.v:8721.9-8721.13"
+              attribute \src "ls180.v:8709.9-8709.13"
               case 
-                attribute \src "ls180.v:8722.6-8732.9"
+                attribute \src "ls180.v:8710.6-8720.9"
                 switch \builder_request [3]
-                  attribute \src "ls180.v:8722.10-8722.28"
+                  attribute \src "ls180.v:8710.10-8710.28"
                   case 1'1
                     assign $0\builder_grant[2:0] 3'011
-                  attribute \src "ls180.v:8724.10-8724.14"
+                  attribute \src "ls180.v:8712.10-8712.14"
                   case 
-                    attribute \src "ls180.v:8725.7-8731.10"
+                    attribute \src "ls180.v:8713.7-8719.10"
                     switch \builder_request [4]
-                      attribute \src "ls180.v:8725.11-8725.29"
+                      attribute \src "ls180.v:8713.11-8713.29"
                       case 1'1
                         assign $0\builder_grant[2:0] 3'100
-                      attribute \src "ls180.v:8727.11-8727.15"
+                      attribute \src "ls180.v:8715.11-8715.15"
                       case 
-                        attribute \src "ls180.v:8728.8-8730.11"
+                        attribute \src "ls180.v:8716.8-8718.11"
                         switch \builder_request [0]
-                          attribute \src "ls180.v:8728.12-8728.30"
+                          attribute \src "ls180.v:8716.12-8716.30"
                           case 1'1
                             assign $0\builder_grant[2:0] 3'000
                           case 
@@ -129488,34 +129320,34 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'010
-        attribute \src "ls180.v:8737.4-8753.7"
-        switch $not$ls180.v:8737$2687_Y
-          attribute \src "ls180.v:8737.8-8737.29"
+        attribute \src "ls180.v:8725.4-8741.7"
+        switch $not$ls180.v:8725$2675_Y
+          attribute \src "ls180.v:8725.8-8725.29"
           case 1'1
-            attribute \src "ls180.v:8738.5-8752.8"
+            attribute \src "ls180.v:8726.5-8740.8"
             switch \builder_request [3]
-              attribute \src "ls180.v:8738.9-8738.27"
+              attribute \src "ls180.v:8726.9-8726.27"
               case 1'1
                 assign $0\builder_grant[2:0] 3'011
-              attribute \src "ls180.v:8740.9-8740.13"
+              attribute \src "ls180.v:8728.9-8728.13"
               case 
-                attribute \src "ls180.v:8741.6-8751.9"
+                attribute \src "ls180.v:8729.6-8739.9"
                 switch \builder_request [4]
-                  attribute \src "ls180.v:8741.10-8741.28"
+                  attribute \src "ls180.v:8729.10-8729.28"
                   case 1'1
                     assign $0\builder_grant[2:0] 3'100
-                  attribute \src "ls180.v:8743.10-8743.14"
+                  attribute \src "ls180.v:8731.10-8731.14"
                   case 
-                    attribute \src "ls180.v:8744.7-8750.10"
+                    attribute \src "ls180.v:8732.7-8738.10"
                     switch \builder_request [0]
-                      attribute \src "ls180.v:8744.11-8744.29"
+                      attribute \src "ls180.v:8732.11-8732.29"
                       case 1'1
                         assign $0\builder_grant[2:0] 3'000
-                      attribute \src "ls180.v:8746.11-8746.15"
+                      attribute \src "ls180.v:8734.11-8734.15"
                       case 
-                        attribute \src "ls180.v:8747.8-8749.11"
+                        attribute \src "ls180.v:8735.8-8737.11"
                         switch \builder_request [1]
-                          attribute \src "ls180.v:8747.12-8747.30"
+                          attribute \src "ls180.v:8735.12-8735.30"
                           case 1'1
                             assign $0\builder_grant[2:0] 3'001
                           case 
@@ -129527,34 +129359,34 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'011
-        attribute \src "ls180.v:8756.4-8772.7"
-        switch $not$ls180.v:8756$2688_Y
-          attribute \src "ls180.v:8756.8-8756.29"
+        attribute \src "ls180.v:8744.4-8760.7"
+        switch $not$ls180.v:8744$2676_Y
+          attribute \src "ls180.v:8744.8-8744.29"
           case 1'1
-            attribute \src "ls180.v:8757.5-8771.8"
+            attribute \src "ls180.v:8745.5-8759.8"
             switch \builder_request [4]
-              attribute \src "ls180.v:8757.9-8757.27"
+              attribute \src "ls180.v:8745.9-8745.27"
               case 1'1
                 assign $0\builder_grant[2:0] 3'100
-              attribute \src "ls180.v:8759.9-8759.13"
+              attribute \src "ls180.v:8747.9-8747.13"
               case 
-                attribute \src "ls180.v:8760.6-8770.9"
+                attribute \src "ls180.v:8748.6-8758.9"
                 switch \builder_request [0]
-                  attribute \src "ls180.v:8760.10-8760.28"
+                  attribute \src "ls180.v:8748.10-8748.28"
                   case 1'1
                     assign $0\builder_grant[2:0] 3'000
-                  attribute \src "ls180.v:8762.10-8762.14"
+                  attribute \src "ls180.v:8750.10-8750.14"
                   case 
-                    attribute \src "ls180.v:8763.7-8769.10"
+                    attribute \src "ls180.v:8751.7-8757.10"
                     switch \builder_request [1]
-                      attribute \src "ls180.v:8763.11-8763.29"
+                      attribute \src "ls180.v:8751.11-8751.29"
                       case 1'1
                         assign $0\builder_grant[2:0] 3'001
-                      attribute \src "ls180.v:8765.11-8765.15"
+                      attribute \src "ls180.v:8753.11-8753.15"
                       case 
-                        attribute \src "ls180.v:8766.8-8768.11"
+                        attribute \src "ls180.v:8754.8-8756.11"
                         switch \builder_request [2]
-                          attribute \src "ls180.v:8766.12-8766.30"
+                          attribute \src "ls180.v:8754.12-8754.30"
                           case 1'1
                             assign $0\builder_grant[2:0] 3'010
                           case 
@@ -129566,34 +129398,34 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'100
-        attribute \src "ls180.v:8775.4-8791.7"
-        switch $not$ls180.v:8775$2689_Y
-          attribute \src "ls180.v:8775.8-8775.29"
+        attribute \src "ls180.v:8763.4-8779.7"
+        switch $not$ls180.v:8763$2677_Y
+          attribute \src "ls180.v:8763.8-8763.29"
           case 1'1
-            attribute \src "ls180.v:8776.5-8790.8"
+            attribute \src "ls180.v:8764.5-8778.8"
             switch \builder_request [0]
-              attribute \src "ls180.v:8776.9-8776.27"
+              attribute \src "ls180.v:8764.9-8764.27"
               case 1'1
                 assign $0\builder_grant[2:0] 3'000
-              attribute \src "ls180.v:8778.9-8778.13"
+              attribute \src "ls180.v:8766.9-8766.13"
               case 
-                attribute \src "ls180.v:8779.6-8789.9"
+                attribute \src "ls180.v:8767.6-8777.9"
                 switch \builder_request [1]
-                  attribute \src "ls180.v:8779.10-8779.28"
+                  attribute \src "ls180.v:8767.10-8767.28"
                   case 1'1
                     assign $0\builder_grant[2:0] 3'001
-                  attribute \src "ls180.v:8781.10-8781.14"
+                  attribute \src "ls180.v:8769.10-8769.14"
                   case 
-                    attribute \src "ls180.v:8782.7-8788.10"
+                    attribute \src "ls180.v:8770.7-8776.10"
                     switch \builder_request [2]
-                      attribute \src "ls180.v:8782.11-8782.29"
+                      attribute \src "ls180.v:8770.11-8770.29"
                       case 1'1
                         assign $0\builder_grant[2:0] 3'010
-                      attribute \src "ls180.v:8784.11-8784.15"
+                      attribute \src "ls180.v:8772.11-8772.15"
                       case 
-                        attribute \src "ls180.v:8785.8-8787.11"
+                        attribute \src "ls180.v:8773.8-8775.11"
                         switch \builder_request [3]
-                          attribute \src "ls180.v:8785.12-8785.30"
+                          attribute \src "ls180.v:8773.12-8773.30"
                           case 1'1
                             assign $0\builder_grant[2:0] 3'011
                           case 
@@ -129605,26 +129437,26 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8795.2-8801.5"
+    attribute \src "ls180.v:8783.2-8789.5"
     switch \builder_wait
-      attribute \src "ls180.v:8795.6-8795.18"
+      attribute \src "ls180.v:8783.6-8783.18"
       case 1'1
-        attribute \src "ls180.v:8796.3-8798.6"
-        switch $not$ls180.v:8796$2690_Y
-          attribute \src "ls180.v:8796.7-8796.22"
+        attribute \src "ls180.v:8784.3-8786.6"
+        switch $not$ls180.v:8784$2678_Y
+          attribute \src "ls180.v:8784.7-8784.22"
           case 1'1
-            assign $0\builder_count[19:0] $sub$ls180.v:8797$2691_Y
+            assign $0\builder_count[19:0] $sub$ls180.v:8785$2679_Y
           case 
         end
-      attribute \src "ls180.v:8799.6-8799.10"
+      attribute \src "ls180.v:8787.6-8787.10"
       case 
         assign $0\builder_count[19:0] 20'11110100001001000000
     end
-    attribute \src "ls180.v:8803.2-8833.5"
+    attribute \src "ls180.v:8791.2-8821.5"
     switch \builder_csrbank0_sel
-      attribute \src "ls180.v:8803.6-8803.26"
+      attribute \src "ls180.v:8791.6-8791.26"
       case 1'1
-        attribute \src "ls180.v:8804.3-8832.10"
+        attribute \src "ls180.v:8792.3-8820.10"
         switch \builder_interface0_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -129657,46 +129489,46 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8834.2-8836.5"
+    attribute \src "ls180.v:8822.2-8824.5"
     switch \builder_csrbank0_reset0_re
-      attribute \src "ls180.v:8834.6-8834.32"
+      attribute \src "ls180.v:8822.6-8822.32"
       case 1'1
         assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r
       case 
     end
-    attribute \src "ls180.v:8838.2-8840.5"
+    attribute \src "ls180.v:8826.2-8828.5"
     switch \builder_csrbank0_scratch3_re
-      attribute \src "ls180.v:8838.6-8838.34"
+      attribute \src "ls180.v:8826.6-8826.34"
       case 1'1
         assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r
       case 
     end
-    attribute \src "ls180.v:8841.2-8843.5"
+    attribute \src "ls180.v:8829.2-8831.5"
     switch \builder_csrbank0_scratch2_re
-      attribute \src "ls180.v:8841.6-8841.34"
+      attribute \src "ls180.v:8829.6-8829.34"
       case 1'1
         assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r
       case 
     end
-    attribute \src "ls180.v:8844.2-8846.5"
+    attribute \src "ls180.v:8832.2-8834.5"
     switch \builder_csrbank0_scratch1_re
-      attribute \src "ls180.v:8844.6-8844.34"
+      attribute \src "ls180.v:8832.6-8832.34"
       case 1'1
         assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r
       case 
     end
-    attribute \src "ls180.v:8847.2-8849.5"
+    attribute \src "ls180.v:8835.2-8837.5"
     switch \builder_csrbank0_scratch0_re
-      attribute \src "ls180.v:8847.6-8847.34"
+      attribute \src "ls180.v:8835.6-8835.34"
       case 1'1
         assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r
       case 
     end
-    attribute \src "ls180.v:8852.2-8873.5"
+    attribute \src "ls180.v:8840.2-8861.5"
     switch \builder_csrbank1_sel
-      attribute \src "ls180.v:8852.6-8852.26"
+      attribute \src "ls180.v:8840.6-8840.26"
       case 1'1
-        attribute \src "ls180.v:8853.3-8872.10"
+        attribute \src "ls180.v:8841.3-8860.10"
         switch \builder_interface1_bank_bus_adr [2:0]
           attribute \src "ls180.v:0.0-0.0"
           case 3'000
@@ -129720,39 +129552,39 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8874.2-8876.5"
+    attribute \src "ls180.v:8862.2-8864.5"
     switch \builder_csrbank1_oe1_re
-      attribute \src "ls180.v:8874.6-8874.29"
+      attribute \src "ls180.v:8862.6-8862.29"
       case 1'1
         assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r
       case 
     end
-    attribute \src "ls180.v:8877.2-8879.5"
+    attribute \src "ls180.v:8865.2-8867.5"
     switch \builder_csrbank1_oe0_re
-      attribute \src "ls180.v:8877.6-8877.29"
+      attribute \src "ls180.v:8865.6-8865.29"
       case 1'1
         assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r
       case 
     end
-    attribute \src "ls180.v:8881.2-8883.5"
+    attribute \src "ls180.v:8869.2-8871.5"
     switch \builder_csrbank1_out1_re
-      attribute \src "ls180.v:8881.6-8881.30"
+      attribute \src "ls180.v:8869.6-8869.30"
       case 1'1
         assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r
       case 
     end
-    attribute \src "ls180.v:8884.2-8886.5"
+    attribute \src "ls180.v:8872.2-8874.5"
     switch \builder_csrbank1_out0_re
-      attribute \src "ls180.v:8884.6-8884.30"
+      attribute \src "ls180.v:8872.6-8872.30"
       case 1'1
         assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r
       case 
     end
-    attribute \src "ls180.v:8889.2-8898.5"
+    attribute \src "ls180.v:8877.2-8886.5"
     switch \builder_csrbank2_sel
-      attribute \src "ls180.v:8889.6-8889.26"
+      attribute \src "ls180.v:8877.6-8877.26"
       case 1'1
-        attribute \src "ls180.v:8890.3-8897.10"
+        attribute \src "ls180.v:8878.3-8885.10"
         switch \builder_interface2_bank_bus_adr [0]
           attribute \src "ls180.v:0.0-0.0"
           case 1'0
@@ -129764,18 +129596,18 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8899.2-8901.5"
+    attribute \src "ls180.v:8887.2-8889.5"
     switch \builder_csrbank2_w0_re
-      attribute \src "ls180.v:8899.6-8899.28"
+      attribute \src "ls180.v:8887.6-8887.28"
       case 1'1
         assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r
       case 
     end
-    attribute \src "ls180.v:8904.2-8934.5"
+    attribute \src "ls180.v:8892.2-8922.5"
     switch \builder_csrbank3_sel
-      attribute \src "ls180.v:8904.6-8904.26"
+      attribute \src "ls180.v:8892.6-8892.26"
       case 1'1
-        attribute \src "ls180.v:8905.3-8933.10"
+        attribute \src "ls180.v:8893.3-8921.10"
         switch \builder_interface3_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -129808,74 +129640,74 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8935.2-8937.5"
+    attribute \src "ls180.v:8923.2-8925.5"
     switch \builder_csrbank3_enable0_re
-      attribute \src "ls180.v:8935.6-8935.33"
+      attribute \src "ls180.v:8923.6-8923.33"
       case 1'1
         assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r
       case 
     end
-    attribute \src "ls180.v:8939.2-8941.5"
+    attribute \src "ls180.v:8927.2-8929.5"
     switch \builder_csrbank3_width3_re
-      attribute \src "ls180.v:8939.6-8939.32"
+      attribute \src "ls180.v:8927.6-8927.32"
       case 1'1
         assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r
       case 
     end
-    attribute \src "ls180.v:8942.2-8944.5"
+    attribute \src "ls180.v:8930.2-8932.5"
     switch \builder_csrbank3_width2_re
-      attribute \src "ls180.v:8942.6-8942.32"
+      attribute \src "ls180.v:8930.6-8930.32"
       case 1'1
         assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r
       case 
     end
-    attribute \src "ls180.v:8945.2-8947.5"
+    attribute \src "ls180.v:8933.2-8935.5"
     switch \builder_csrbank3_width1_re
-      attribute \src "ls180.v:8945.6-8945.32"
+      attribute \src "ls180.v:8933.6-8933.32"
       case 1'1
         assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r
       case 
     end
-    attribute \src "ls180.v:8948.2-8950.5"
+    attribute \src "ls180.v:8936.2-8938.5"
     switch \builder_csrbank3_width0_re
-      attribute \src "ls180.v:8948.6-8948.32"
+      attribute \src "ls180.v:8936.6-8936.32"
       case 1'1
         assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r
       case 
     end
-    attribute \src "ls180.v:8952.2-8954.5"
+    attribute \src "ls180.v:8940.2-8942.5"
     switch \builder_csrbank3_period3_re
-      attribute \src "ls180.v:8952.6-8952.33"
+      attribute \src "ls180.v:8940.6-8940.33"
       case 1'1
         assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r
       case 
     end
-    attribute \src "ls180.v:8955.2-8957.5"
+    attribute \src "ls180.v:8943.2-8945.5"
     switch \builder_csrbank3_period2_re
-      attribute \src "ls180.v:8955.6-8955.33"
+      attribute \src "ls180.v:8943.6-8943.33"
       case 1'1
         assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r
       case 
     end
-    attribute \src "ls180.v:8958.2-8960.5"
+    attribute \src "ls180.v:8946.2-8948.5"
     switch \builder_csrbank3_period1_re
-      attribute \src "ls180.v:8958.6-8958.33"
+      attribute \src "ls180.v:8946.6-8946.33"
       case 1'1
         assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r
       case 
     end
-    attribute \src "ls180.v:8961.2-8963.5"
+    attribute \src "ls180.v:8949.2-8951.5"
     switch \builder_csrbank3_period0_re
-      attribute \src "ls180.v:8961.6-8961.33"
+      attribute \src "ls180.v:8949.6-8949.33"
       case 1'1
         assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r
       case 
     end
-    attribute \src "ls180.v:8966.2-8996.5"
+    attribute \src "ls180.v:8954.2-8984.5"
     switch \builder_csrbank4_sel
-      attribute \src "ls180.v:8966.6-8966.26"
+      attribute \src "ls180.v:8954.6-8954.26"
       case 1'1
-        attribute \src "ls180.v:8967.3-8995.10"
+        attribute \src "ls180.v:8955.3-8983.10"
         switch \builder_interface4_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -129908,74 +129740,74 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:8997.2-8999.5"
+    attribute \src "ls180.v:8985.2-8987.5"
     switch \builder_csrbank4_enable0_re
-      attribute \src "ls180.v:8997.6-8997.33"
+      attribute \src "ls180.v:8985.6-8985.33"
       case 1'1
         assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r
       case 
     end
-    attribute \src "ls180.v:9001.2-9003.5"
+    attribute \src "ls180.v:8989.2-8991.5"
     switch \builder_csrbank4_width3_re
-      attribute \src "ls180.v:9001.6-9001.32"
+      attribute \src "ls180.v:8989.6-8989.32"
       case 1'1
         assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r
       case 
     end
-    attribute \src "ls180.v:9004.2-9006.5"
+    attribute \src "ls180.v:8992.2-8994.5"
     switch \builder_csrbank4_width2_re
-      attribute \src "ls180.v:9004.6-9004.32"
+      attribute \src "ls180.v:8992.6-8992.32"
       case 1'1
         assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r
       case 
     end
-    attribute \src "ls180.v:9007.2-9009.5"
+    attribute \src "ls180.v:8995.2-8997.5"
     switch \builder_csrbank4_width1_re
-      attribute \src "ls180.v:9007.6-9007.32"
+      attribute \src "ls180.v:8995.6-8995.32"
       case 1'1
         assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r
       case 
     end
-    attribute \src "ls180.v:9010.2-9012.5"
+    attribute \src "ls180.v:8998.2-9000.5"
     switch \builder_csrbank4_width0_re
-      attribute \src "ls180.v:9010.6-9010.32"
+      attribute \src "ls180.v:8998.6-8998.32"
       case 1'1
         assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r
       case 
     end
-    attribute \src "ls180.v:9014.2-9016.5"
+    attribute \src "ls180.v:9002.2-9004.5"
     switch \builder_csrbank4_period3_re
-      attribute \src "ls180.v:9014.6-9014.33"
+      attribute \src "ls180.v:9002.6-9002.33"
       case 1'1
         assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r
       case 
     end
-    attribute \src "ls180.v:9017.2-9019.5"
+    attribute \src "ls180.v:9005.2-9007.5"
     switch \builder_csrbank4_period2_re
-      attribute \src "ls180.v:9017.6-9017.33"
+      attribute \src "ls180.v:9005.6-9005.33"
       case 1'1
         assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r
       case 
     end
-    attribute \src "ls180.v:9020.2-9022.5"
+    attribute \src "ls180.v:9008.2-9010.5"
     switch \builder_csrbank4_period1_re
-      attribute \src "ls180.v:9020.6-9020.33"
+      attribute \src "ls180.v:9008.6-9008.33"
       case 1'1
         assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r
       case 
     end
-    attribute \src "ls180.v:9023.2-9025.5"
+    attribute \src "ls180.v:9011.2-9013.5"
     switch \builder_csrbank4_period0_re
-      attribute \src "ls180.v:9023.6-9023.33"
+      attribute \src "ls180.v:9011.6-9011.33"
       case 1'1
         assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r
       case 
     end
-    attribute \src "ls180.v:9028.2-9076.5"
+    attribute \src "ls180.v:9016.2-9064.5"
     switch \builder_csrbank5_sel
-      attribute \src "ls180.v:9028.6-9028.26"
+      attribute \src "ls180.v:9016.6-9016.26"
       case 1'1
-        attribute \src "ls180.v:9029.3-9075.10"
+        attribute \src "ls180.v:9017.3-9063.10"
         switch \builder_interface5_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -130026,109 +129858,109 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9077.2-9079.5"
+    attribute \src "ls180.v:9065.2-9067.5"
     switch \builder_csrbank5_dma_base7_re
-      attribute \src "ls180.v:9077.6-9077.35"
+      attribute \src "ls180.v:9065.6-9065.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r
       case 
     end
-    attribute \src "ls180.v:9080.2-9082.5"
+    attribute \src "ls180.v:9068.2-9070.5"
     switch \builder_csrbank5_dma_base6_re
-      attribute \src "ls180.v:9080.6-9080.35"
+      attribute \src "ls180.v:9068.6-9068.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r
       case 
     end
-    attribute \src "ls180.v:9083.2-9085.5"
+    attribute \src "ls180.v:9071.2-9073.5"
     switch \builder_csrbank5_dma_base5_re
-      attribute \src "ls180.v:9083.6-9083.35"
+      attribute \src "ls180.v:9071.6-9071.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r
       case 
     end
-    attribute \src "ls180.v:9086.2-9088.5"
+    attribute \src "ls180.v:9074.2-9076.5"
     switch \builder_csrbank5_dma_base4_re
-      attribute \src "ls180.v:9086.6-9086.35"
+      attribute \src "ls180.v:9074.6-9074.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r
       case 
     end
-    attribute \src "ls180.v:9089.2-9091.5"
+    attribute \src "ls180.v:9077.2-9079.5"
     switch \builder_csrbank5_dma_base3_re
-      attribute \src "ls180.v:9089.6-9089.35"
+      attribute \src "ls180.v:9077.6-9077.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r
       case 
     end
-    attribute \src "ls180.v:9092.2-9094.5"
+    attribute \src "ls180.v:9080.2-9082.5"
     switch \builder_csrbank5_dma_base2_re
-      attribute \src "ls180.v:9092.6-9092.35"
+      attribute \src "ls180.v:9080.6-9080.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r
       case 
     end
-    attribute \src "ls180.v:9095.2-9097.5"
+    attribute \src "ls180.v:9083.2-9085.5"
     switch \builder_csrbank5_dma_base1_re
-      attribute \src "ls180.v:9095.6-9095.35"
+      attribute \src "ls180.v:9083.6-9083.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r
       case 
     end
-    attribute \src "ls180.v:9098.2-9100.5"
+    attribute \src "ls180.v:9086.2-9088.5"
     switch \builder_csrbank5_dma_base0_re
-      attribute \src "ls180.v:9098.6-9098.35"
+      attribute \src "ls180.v:9086.6-9086.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r
       case 
     end
-    attribute \src "ls180.v:9102.2-9104.5"
+    attribute \src "ls180.v:9090.2-9092.5"
     switch \builder_csrbank5_dma_length3_re
-      attribute \src "ls180.v:9102.6-9102.37"
+      attribute \src "ls180.v:9090.6-9090.37"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r
       case 
     end
-    attribute \src "ls180.v:9105.2-9107.5"
+    attribute \src "ls180.v:9093.2-9095.5"
     switch \builder_csrbank5_dma_length2_re
-      attribute \src "ls180.v:9105.6-9105.37"
+      attribute \src "ls180.v:9093.6-9093.37"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r
       case 
     end
-    attribute \src "ls180.v:9108.2-9110.5"
+    attribute \src "ls180.v:9096.2-9098.5"
     switch \builder_csrbank5_dma_length1_re
-      attribute \src "ls180.v:9108.6-9108.37"
+      attribute \src "ls180.v:9096.6-9096.37"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r
       case 
     end
-    attribute \src "ls180.v:9111.2-9113.5"
+    attribute \src "ls180.v:9099.2-9101.5"
     switch \builder_csrbank5_dma_length0_re
-      attribute \src "ls180.v:9111.6-9111.37"
+      attribute \src "ls180.v:9099.6-9099.37"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r
       case 
     end
-    attribute \src "ls180.v:9115.2-9117.5"
+    attribute \src "ls180.v:9103.2-9105.5"
     switch \builder_csrbank5_dma_enable0_re
-      attribute \src "ls180.v:9115.6-9115.37"
+      attribute \src "ls180.v:9103.6-9103.37"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r
       case 
     end
-    attribute \src "ls180.v:9119.2-9121.5"
+    attribute \src "ls180.v:9107.2-9109.5"
     switch \builder_csrbank5_dma_loop0_re
-      attribute \src "ls180.v:9119.6-9119.35"
+      attribute \src "ls180.v:9107.6-9107.35"
       case 1'1
         assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r
       case 
     end
-    attribute \src "ls180.v:9124.2-9226.5"
+    attribute \src "ls180.v:9112.2-9214.5"
     switch \builder_csrbank6_sel
-      attribute \src "ls180.v:9124.6-9124.26"
+      attribute \src "ls180.v:9112.6-9112.26"
       case 1'1
-        attribute \src "ls180.v:9125.3-9225.10"
+        attribute \src "ls180.v:9113.3-9213.10"
         switch \builder_interface6_bank_bus_adr [5:0]
           attribute \src "ls180.v:0.0-0.0"
           case 6'000000
@@ -130233,109 +130065,109 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9227.2-9229.5"
+    attribute \src "ls180.v:9215.2-9217.5"
     switch \builder_csrbank6_cmd_argument3_re
-      attribute \src "ls180.v:9227.6-9227.39"
+      attribute \src "ls180.v:9215.6-9215.39"
       case 1'1
         assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r
       case 
     end
-    attribute \src "ls180.v:9230.2-9232.5"
+    attribute \src "ls180.v:9218.2-9220.5"
     switch \builder_csrbank6_cmd_argument2_re
-      attribute \src "ls180.v:9230.6-9230.39"
+      attribute \src "ls180.v:9218.6-9218.39"
       case 1'1
         assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r
       case 
     end
-    attribute \src "ls180.v:9233.2-9235.5"
+    attribute \src "ls180.v:9221.2-9223.5"
     switch \builder_csrbank6_cmd_argument1_re
-      attribute \src "ls180.v:9233.6-9233.39"
+      attribute \src "ls180.v:9221.6-9221.39"
       case 1'1
         assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r
       case 
     end
-    attribute \src "ls180.v:9236.2-9238.5"
+    attribute \src "ls180.v:9224.2-9226.5"
     switch \builder_csrbank6_cmd_argument0_re
-      attribute \src "ls180.v:9236.6-9236.39"
+      attribute \src "ls180.v:9224.6-9224.39"
       case 1'1
         assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r
       case 
     end
-    attribute \src "ls180.v:9240.2-9242.5"
+    attribute \src "ls180.v:9228.2-9230.5"
     switch \builder_csrbank6_cmd_command3_re
-      attribute \src "ls180.v:9240.6-9240.38"
+      attribute \src "ls180.v:9228.6-9228.38"
       case 1'1
         assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r
       case 
     end
-    attribute \src "ls180.v:9243.2-9245.5"
+    attribute \src "ls180.v:9231.2-9233.5"
     switch \builder_csrbank6_cmd_command2_re
-      attribute \src "ls180.v:9243.6-9243.38"
+      attribute \src "ls180.v:9231.6-9231.38"
       case 1'1
         assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r
       case 
     end
-    attribute \src "ls180.v:9246.2-9248.5"
+    attribute \src "ls180.v:9234.2-9236.5"
     switch \builder_csrbank6_cmd_command1_re
-      attribute \src "ls180.v:9246.6-9246.38"
+      attribute \src "ls180.v:9234.6-9234.38"
       case 1'1
         assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r
       case 
     end
-    attribute \src "ls180.v:9249.2-9251.5"
+    attribute \src "ls180.v:9237.2-9239.5"
     switch \builder_csrbank6_cmd_command0_re
-      attribute \src "ls180.v:9249.6-9249.38"
+      attribute \src "ls180.v:9237.6-9237.38"
       case 1'1
         assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r
       case 
     end
-    attribute \src "ls180.v:9253.2-9255.5"
+    attribute \src "ls180.v:9241.2-9243.5"
     switch \builder_csrbank6_block_length1_re
-      attribute \src "ls180.v:9253.6-9253.39"
+      attribute \src "ls180.v:9241.6-9241.39"
       case 1'1
         assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r
       case 
     end
-    attribute \src "ls180.v:9256.2-9258.5"
+    attribute \src "ls180.v:9244.2-9246.5"
     switch \builder_csrbank6_block_length0_re
-      attribute \src "ls180.v:9256.6-9256.39"
+      attribute \src "ls180.v:9244.6-9244.39"
       case 1'1
         assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r
       case 
     end
-    attribute \src "ls180.v:9260.2-9262.5"
+    attribute \src "ls180.v:9248.2-9250.5"
     switch \builder_csrbank6_block_count3_re
-      attribute \src "ls180.v:9260.6-9260.38"
+      attribute \src "ls180.v:9248.6-9248.38"
       case 1'1
         assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r
       case 
     end
-    attribute \src "ls180.v:9263.2-9265.5"
+    attribute \src "ls180.v:9251.2-9253.5"
     switch \builder_csrbank6_block_count2_re
-      attribute \src "ls180.v:9263.6-9263.38"
+      attribute \src "ls180.v:9251.6-9251.38"
       case 1'1
         assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r
       case 
     end
-    attribute \src "ls180.v:9266.2-9268.5"
+    attribute \src "ls180.v:9254.2-9256.5"
     switch \builder_csrbank6_block_count1_re
-      attribute \src "ls180.v:9266.6-9266.38"
+      attribute \src "ls180.v:9254.6-9254.38"
       case 1'1
         assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r
       case 
     end
-    attribute \src "ls180.v:9269.2-9271.5"
+    attribute \src "ls180.v:9257.2-9259.5"
     switch \builder_csrbank6_block_count0_re
-      attribute \src "ls180.v:9269.6-9269.38"
+      attribute \src "ls180.v:9257.6-9257.38"
       case 1'1
         assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r
       case 
     end
-    attribute \src "ls180.v:9274.2-9334.5"
+    attribute \src "ls180.v:9262.2-9322.5"
     switch \builder_csrbank7_sel
-      attribute \src "ls180.v:9274.6-9274.26"
+      attribute \src "ls180.v:9262.6-9262.26"
       case 1'1
-        attribute \src "ls180.v:9275.3-9333.10"
+        attribute \src "ls180.v:9263.3-9321.10"
         switch \builder_interface7_bank_bus_adr [4:0]
           attribute \src "ls180.v:0.0-0.0"
           case 5'00000
@@ -130398,109 +130230,109 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9335.2-9337.5"
+    attribute \src "ls180.v:9323.2-9325.5"
     switch \builder_csrbank7_dma_base7_re
-      attribute \src "ls180.v:9335.6-9335.35"
+      attribute \src "ls180.v:9323.6-9323.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r
       case 
     end
-    attribute \src "ls180.v:9338.2-9340.5"
+    attribute \src "ls180.v:9326.2-9328.5"
     switch \builder_csrbank7_dma_base6_re
-      attribute \src "ls180.v:9338.6-9338.35"
+      attribute \src "ls180.v:9326.6-9326.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r
       case 
     end
-    attribute \src "ls180.v:9341.2-9343.5"
+    attribute \src "ls180.v:9329.2-9331.5"
     switch \builder_csrbank7_dma_base5_re
-      attribute \src "ls180.v:9341.6-9341.35"
+      attribute \src "ls180.v:9329.6-9329.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r
       case 
     end
-    attribute \src "ls180.v:9344.2-9346.5"
+    attribute \src "ls180.v:9332.2-9334.5"
     switch \builder_csrbank7_dma_base4_re
-      attribute \src "ls180.v:9344.6-9344.35"
+      attribute \src "ls180.v:9332.6-9332.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r
       case 
     end
-    attribute \src "ls180.v:9347.2-9349.5"
+    attribute \src "ls180.v:9335.2-9337.5"
     switch \builder_csrbank7_dma_base3_re
-      attribute \src "ls180.v:9347.6-9347.35"
+      attribute \src "ls180.v:9335.6-9335.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r
       case 
     end
-    attribute \src "ls180.v:9350.2-9352.5"
+    attribute \src "ls180.v:9338.2-9340.5"
     switch \builder_csrbank7_dma_base2_re
-      attribute \src "ls180.v:9350.6-9350.35"
+      attribute \src "ls180.v:9338.6-9338.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r
       case 
     end
-    attribute \src "ls180.v:9353.2-9355.5"
+    attribute \src "ls180.v:9341.2-9343.5"
     switch \builder_csrbank7_dma_base1_re
-      attribute \src "ls180.v:9353.6-9353.35"
+      attribute \src "ls180.v:9341.6-9341.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r
       case 
     end
-    attribute \src "ls180.v:9356.2-9358.5"
+    attribute \src "ls180.v:9344.2-9346.5"
     switch \builder_csrbank7_dma_base0_re
-      attribute \src "ls180.v:9356.6-9356.35"
+      attribute \src "ls180.v:9344.6-9344.35"
       case 1'1
         assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r
       case 
     end
-    attribute \src "ls180.v:9360.2-9362.5"
+    attribute \src "ls180.v:9348.2-9350.5"
     switch \builder_csrbank7_dma_length3_re
-      attribute \src "ls180.v:9360.6-9360.37"
+      attribute \src "ls180.v:9348.6-9348.37"
       case 1'1
         assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r
       case 
     end
-    attribute \src "ls180.v:9363.2-9365.5"
+    attribute \src "ls180.v:9351.2-9353.5"
     switch \builder_csrbank7_dma_length2_re
-      attribute \src "ls180.v:9363.6-9363.37"
+      attribute \src "ls180.v:9351.6-9351.37"
       case 1'1
         assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r
       case 
     end
-    attribute \src "ls180.v:9366.2-9368.5"
+    attribute \src "ls180.v:9354.2-9356.5"
     switch \builder_csrbank7_dma_length1_re
-      attribute \src "ls180.v:9366.6-9366.37"
+      attribute \src "ls180.v:9354.6-9354.37"
       case 1'1
         assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r
       case 
     end
-    attribute \src "ls180.v:9369.2-9371.5"
+    attribute \src "ls180.v:9357.2-9359.5"
     switch \builder_csrbank7_dma_length0_re
-      attribute \src "ls180.v:9369.6-9369.37"
+      attribute \src "ls180.v:9357.6-9357.37"
       case 1'1
         assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r
       case 
     end
-    attribute \src "ls180.v:9373.2-9375.5"
+    attribute \src "ls180.v:9361.2-9363.5"
     switch \builder_csrbank7_dma_enable0_re
-      attribute \src "ls180.v:9373.6-9373.37"
+      attribute \src "ls180.v:9361.6-9361.37"
       case 1'1
         assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r
       case 
     end
-    attribute \src "ls180.v:9377.2-9379.5"
+    attribute \src "ls180.v:9365.2-9367.5"
     switch \builder_csrbank7_dma_loop0_re
-      attribute \src "ls180.v:9377.6-9377.35"
+      attribute \src "ls180.v:9365.6-9365.35"
       case 1'1
         assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r
       case 
     end
-    attribute \src "ls180.v:9382.2-9397.5"
+    attribute \src "ls180.v:9370.2-9385.5"
     switch \builder_csrbank8_sel
-      attribute \src "ls180.v:9382.6-9382.26"
+      attribute \src "ls180.v:9370.6-9370.26"
       case 1'1
-        attribute \src "ls180.v:9383.3-9396.10"
+        attribute \src "ls180.v:9371.3-9384.10"
         switch \builder_interface8_bank_bus_adr [1:0]
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
@@ -130518,25 +130350,25 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9398.2-9400.5"
+    attribute \src "ls180.v:9386.2-9388.5"
     switch \builder_csrbank8_clocker_divider1_re
-      attribute \src "ls180.v:9398.6-9398.42"
+      attribute \src "ls180.v:9386.6-9386.42"
       case 1'1
         assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r
       case 
     end
-    attribute \src "ls180.v:9401.2-9403.5"
+    attribute \src "ls180.v:9389.2-9391.5"
     switch \builder_csrbank8_clocker_divider0_re
-      attribute \src "ls180.v:9401.6-9401.42"
+      attribute \src "ls180.v:9389.6-9389.42"
       case 1'1
         assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r
       case 
     end
-    attribute \src "ls180.v:9406.2-9439.5"
+    attribute \src "ls180.v:9394.2-9427.5"
     switch \builder_csrbank9_sel
-      attribute \src "ls180.v:9406.6-9406.26"
+      attribute \src "ls180.v:9394.6-9394.26"
       case 1'1
-        attribute \src "ls180.v:9407.3-9438.10"
+        attribute \src "ls180.v:9395.3-9426.10"
         switch \builder_interface9_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -130572,60 +130404,60 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9440.2-9442.5"
+    attribute \src "ls180.v:9428.2-9430.5"
     switch \builder_csrbank9_dfii_control0_re
-      attribute \src "ls180.v:9440.6-9440.39"
+      attribute \src "ls180.v:9428.6-9428.39"
       case 1'1
         assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r
       case 
     end
-    attribute \src "ls180.v:9444.2-9446.5"
+    attribute \src "ls180.v:9432.2-9434.5"
     switch \builder_csrbank9_dfii_pi0_command0_re
-      attribute \src "ls180.v:9444.6-9444.43"
+      attribute \src "ls180.v:9432.6-9432.43"
       case 1'1
         assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r
       case 
     end
-    attribute \src "ls180.v:9448.2-9450.5"
+    attribute \src "ls180.v:9436.2-9438.5"
     switch \builder_csrbank9_dfii_pi0_address1_re
-      attribute \src "ls180.v:9448.6-9448.43"
+      attribute \src "ls180.v:9436.6-9436.43"
       case 1'1
         assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r
       case 
     end
-    attribute \src "ls180.v:9451.2-9453.5"
+    attribute \src "ls180.v:9439.2-9441.5"
     switch \builder_csrbank9_dfii_pi0_address0_re
-      attribute \src "ls180.v:9451.6-9451.43"
+      attribute \src "ls180.v:9439.6-9439.43"
       case 1'1
         assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r
       case 
     end
-    attribute \src "ls180.v:9455.2-9457.5"
+    attribute \src "ls180.v:9443.2-9445.5"
     switch \builder_csrbank9_dfii_pi0_baddress0_re
-      attribute \src "ls180.v:9455.6-9455.44"
+      attribute \src "ls180.v:9443.6-9443.44"
       case 1'1
         assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r
       case 
     end
-    attribute \src "ls180.v:9459.2-9461.5"
+    attribute \src "ls180.v:9447.2-9449.5"
     switch \builder_csrbank9_dfii_pi0_wrdata1_re
-      attribute \src "ls180.v:9459.6-9459.42"
+      attribute \src "ls180.v:9447.6-9447.42"
       case 1'1
         assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r
       case 
     end
-    attribute \src "ls180.v:9462.2-9464.5"
+    attribute \src "ls180.v:9450.2-9452.5"
     switch \builder_csrbank9_dfii_pi0_wrdata0_re
-      attribute \src "ls180.v:9462.6-9462.42"
+      attribute \src "ls180.v:9450.6-9450.42"
       case 1'1
         assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r
       case 
     end
-    attribute \src "ls180.v:9467.2-9491.5"
+    attribute \src "ls180.v:9455.2-9479.5"
     switch \builder_csrbank10_sel
-      attribute \src "ls180.v:9467.6-9467.27"
+      attribute \src "ls180.v:9455.6-9455.27"
       case 1'1
-        attribute \src "ls180.v:9468.3-9490.10"
+        attribute \src "ls180.v:9456.3-9478.10"
         switch \builder_interface10_bank_bus_adr [2:0]
           attribute \src "ls180.v:0.0-0.0"
           case 3'000
@@ -130652,46 +130484,46 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9492.2-9494.5"
+    attribute \src "ls180.v:9480.2-9482.5"
     switch \builder_csrbank10_control1_re
-      attribute \src "ls180.v:9492.6-9492.35"
+      attribute \src "ls180.v:9480.6-9480.35"
       case 1'1
         assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r
       case 
     end
-    attribute \src "ls180.v:9495.2-9497.5"
+    attribute \src "ls180.v:9483.2-9485.5"
     switch \builder_csrbank10_control0_re
-      attribute \src "ls180.v:9495.6-9495.35"
+      attribute \src "ls180.v:9483.6-9483.35"
       case 1'1
         assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r
       case 
     end
-    attribute \src "ls180.v:9499.2-9501.5"
+    attribute \src "ls180.v:9487.2-9489.5"
     switch \builder_csrbank10_mosi0_re
-      attribute \src "ls180.v:9499.6-9499.32"
+      attribute \src "ls180.v:9487.6-9487.32"
       case 1'1
         assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r
       case 
     end
-    attribute \src "ls180.v:9503.2-9505.5"
+    attribute \src "ls180.v:9491.2-9493.5"
     switch \builder_csrbank10_cs0_re
-      attribute \src "ls180.v:9503.6-9503.30"
+      attribute \src "ls180.v:9491.6-9491.30"
       case 1'1
         assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r
       case 
     end
-    attribute \src "ls180.v:9507.2-9509.5"
+    attribute \src "ls180.v:9495.2-9497.5"
     switch \builder_csrbank10_loopback0_re
-      attribute \src "ls180.v:9507.6-9507.36"
+      attribute \src "ls180.v:9495.6-9495.36"
       case 1'1
         assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r
       case 
     end
-    attribute \src "ls180.v:9512.2-9542.5"
+    attribute \src "ls180.v:9500.2-9530.5"
     switch \builder_csrbank11_sel
-      attribute \src "ls180.v:9512.6-9512.27"
+      attribute \src "ls180.v:9500.6-9500.27"
       case 1'1
-        attribute \src "ls180.v:9513.3-9541.10"
+        attribute \src "ls180.v:9501.3-9529.10"
         switch \builder_interface11_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -130724,60 +130556,60 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9543.2-9545.5"
+    attribute \src "ls180.v:9531.2-9533.5"
     switch \builder_csrbank11_control1_re
-      attribute \src "ls180.v:9543.6-9543.35"
+      attribute \src "ls180.v:9531.6-9531.35"
       case 1'1
         assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r
       case 
     end
-    attribute \src "ls180.v:9546.2-9548.5"
+    attribute \src "ls180.v:9534.2-9536.5"
     switch \builder_csrbank11_control0_re
-      attribute \src "ls180.v:9546.6-9546.35"
+      attribute \src "ls180.v:9534.6-9534.35"
       case 1'1
         assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r
       case 
     end
-    attribute \src "ls180.v:9550.2-9552.5"
+    attribute \src "ls180.v:9538.2-9540.5"
     switch \builder_csrbank11_mosi0_re
-      attribute \src "ls180.v:9550.6-9550.32"
+      attribute \src "ls180.v:9538.6-9538.32"
       case 1'1
         assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r
       case 
     end
-    attribute \src "ls180.v:9554.2-9556.5"
+    attribute \src "ls180.v:9542.2-9544.5"
     switch \builder_csrbank11_cs0_re
-      attribute \src "ls180.v:9554.6-9554.30"
+      attribute \src "ls180.v:9542.6-9542.30"
       case 1'1
         assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r
       case 
     end
-    attribute \src "ls180.v:9558.2-9560.5"
+    attribute \src "ls180.v:9546.2-9548.5"
     switch \builder_csrbank11_loopback0_re
-      attribute \src "ls180.v:9558.6-9558.36"
+      attribute \src "ls180.v:9546.6-9546.36"
       case 1'1
         assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r
       case 
     end
-    attribute \src "ls180.v:9562.2-9564.5"
+    attribute \src "ls180.v:9550.2-9552.5"
     switch \builder_csrbank11_clk_divider1_re
-      attribute \src "ls180.v:9562.6-9562.39"
+      attribute \src "ls180.v:9550.6-9550.39"
       case 1'1
         assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r
       case 
     end
-    attribute \src "ls180.v:9565.2-9567.5"
+    attribute \src "ls180.v:9553.2-9555.5"
     switch \builder_csrbank11_clk_divider0_re
-      attribute \src "ls180.v:9565.6-9565.39"
+      attribute \src "ls180.v:9553.6-9553.39"
       case 1'1
         assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r
       case 
     end
-    attribute \src "ls180.v:9570.2-9624.5"
+    attribute \src "ls180.v:9558.2-9612.5"
     switch \builder_csrbank12_sel
-      attribute \src "ls180.v:9570.6-9570.27"
+      attribute \src "ls180.v:9558.6-9558.27"
       case 1'1
-        attribute \src "ls180.v:9571.3-9623.10"
+        attribute \src "ls180.v:9559.3-9611.10"
         switch \builder_interface12_bank_bus_adr [4:0]
           attribute \src "ls180.v:0.0-0.0"
           case 5'00000
@@ -130834,88 +130666,88 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9625.2-9627.5"
+    attribute \src "ls180.v:9613.2-9615.5"
     switch \builder_csrbank12_load3_re
-      attribute \src "ls180.v:9625.6-9625.32"
+      attribute \src "ls180.v:9613.6-9613.32"
       case 1'1
         assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r
       case 
     end
-    attribute \src "ls180.v:9628.2-9630.5"
+    attribute \src "ls180.v:9616.2-9618.5"
     switch \builder_csrbank12_load2_re
-      attribute \src "ls180.v:9628.6-9628.32"
+      attribute \src "ls180.v:9616.6-9616.32"
       case 1'1
         assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r
       case 
     end
-    attribute \src "ls180.v:9631.2-9633.5"
+    attribute \src "ls180.v:9619.2-9621.5"
     switch \builder_csrbank12_load1_re
-      attribute \src "ls180.v:9631.6-9631.32"
+      attribute \src "ls180.v:9619.6-9619.32"
       case 1'1
         assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r
       case 
     end
-    attribute \src "ls180.v:9634.2-9636.5"
+    attribute \src "ls180.v:9622.2-9624.5"
     switch \builder_csrbank12_load0_re
-      attribute \src "ls180.v:9634.6-9634.32"
+      attribute \src "ls180.v:9622.6-9622.32"
       case 1'1
         assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r
       case 
     end
-    attribute \src "ls180.v:9638.2-9640.5"
+    attribute \src "ls180.v:9626.2-9628.5"
     switch \builder_csrbank12_reload3_re
-      attribute \src "ls180.v:9638.6-9638.34"
+      attribute \src "ls180.v:9626.6-9626.34"
       case 1'1
         assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r
       case 
     end
-    attribute \src "ls180.v:9641.2-9643.5"
+    attribute \src "ls180.v:9629.2-9631.5"
     switch \builder_csrbank12_reload2_re
-      attribute \src "ls180.v:9641.6-9641.34"
+      attribute \src "ls180.v:9629.6-9629.34"
       case 1'1
         assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r
       case 
     end
-    attribute \src "ls180.v:9644.2-9646.5"
+    attribute \src "ls180.v:9632.2-9634.5"
     switch \builder_csrbank12_reload1_re
-      attribute \src "ls180.v:9644.6-9644.34"
+      attribute \src "ls180.v:9632.6-9632.34"
       case 1'1
         assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r
       case 
     end
-    attribute \src "ls180.v:9647.2-9649.5"
+    attribute \src "ls180.v:9635.2-9637.5"
     switch \builder_csrbank12_reload0_re
-      attribute \src "ls180.v:9647.6-9647.34"
+      attribute \src "ls180.v:9635.6-9635.34"
       case 1'1
         assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r
       case 
     end
-    attribute \src "ls180.v:9651.2-9653.5"
+    attribute \src "ls180.v:9639.2-9641.5"
     switch \builder_csrbank12_en0_re
-      attribute \src "ls180.v:9651.6-9651.30"
+      attribute \src "ls180.v:9639.6-9639.30"
       case 1'1
         assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r
       case 
     end
-    attribute \src "ls180.v:9655.2-9657.5"
+    attribute \src "ls180.v:9643.2-9645.5"
     switch \builder_csrbank12_update_value0_re
-      attribute \src "ls180.v:9655.6-9655.40"
+      attribute \src "ls180.v:9643.6-9643.40"
       case 1'1
         assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r
       case 
     end
-    attribute \src "ls180.v:9659.2-9661.5"
+    attribute \src "ls180.v:9647.2-9649.5"
     switch \builder_csrbank12_ev_enable0_re
-      attribute \src "ls180.v:9659.6-9659.37"
+      attribute \src "ls180.v:9647.6-9647.37"
       case 1'1
         assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r
       case 
     end
-    attribute \src "ls180.v:9664.2-9691.5"
+    attribute \src "ls180.v:9652.2-9679.5"
     switch \builder_csrbank13_sel
-      attribute \src "ls180.v:9664.6-9664.27"
+      attribute \src "ls180.v:9652.6-9652.27"
       case 1'1
-        attribute \src "ls180.v:9665.3-9690.10"
+        attribute \src "ls180.v:9653.3-9678.10"
         switch \builder_interface13_bank_bus_adr [2:0]
           attribute \src "ls180.v:0.0-0.0"
           case 3'000
@@ -130945,18 +130777,18 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9692.2-9694.5"
+    attribute \src "ls180.v:9680.2-9682.5"
     switch \builder_csrbank13_ev_enable0_re
-      attribute \src "ls180.v:9692.6-9692.37"
+      attribute \src "ls180.v:9680.6-9680.37"
       case 1'1
         assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r
       case 
     end
-    attribute \src "ls180.v:9697.2-9712.5"
+    attribute \src "ls180.v:9685.2-9700.5"
     switch \builder_csrbank14_sel
-      attribute \src "ls180.v:9697.6-9697.27"
+      attribute \src "ls180.v:9685.6-9685.27"
       case 1'1
-        attribute \src "ls180.v:9698.3-9711.10"
+        attribute \src "ls180.v:9686.3-9699.10"
         switch \builder_interface14_bank_bus_adr [1:0]
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
@@ -130974,51 +130806,51 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:9713.2-9715.5"
+    attribute \src "ls180.v:9701.2-9703.5"
     switch \builder_csrbank14_tuning_word3_re
-      attribute \src "ls180.v:9713.6-9713.39"
+      attribute \src "ls180.v:9701.6-9701.39"
       case 1'1
         assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r
       case 
     end
-    attribute \src "ls180.v:9716.2-9718.5"
+    attribute \src "ls180.v:9704.2-9706.5"
     switch \builder_csrbank14_tuning_word2_re
-      attribute \src "ls180.v:9716.6-9716.39"
+      attribute \src "ls180.v:9704.6-9704.39"
       case 1'1
         assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r
       case 
     end
-    attribute \src "ls180.v:9719.2-9721.5"
+    attribute \src "ls180.v:9707.2-9709.5"
     switch \builder_csrbank14_tuning_word1_re
-      attribute \src "ls180.v:9719.6-9719.39"
+      attribute \src "ls180.v:9707.6-9707.39"
       case 1'1
         assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r
       case 
     end
-    attribute \src "ls180.v:9722.2-9724.5"
+    attribute \src "ls180.v:9710.2-9712.5"
     switch \builder_csrbank14_tuning_word0_re
-      attribute \src "ls180.v:9722.6-9722.39"
+      attribute \src "ls180.v:9710.6-9710.39"
       case 1'1
         assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r
       case 
     end
-    attribute \src "ls180.v:9726.2-10020.5"
+    attribute \src "ls180.v:9714.2-10008.5"
     switch \sys_rst_1
-      attribute \src "ls180.v:9726.6-9726.15"
+      attribute \src "ls180.v:9714.6-9714.15"
       case 1'1
         assign $0\main_libresocsim_reset_storage[0:0] 1'0
         assign $0\main_libresocsim_reset_re[0:0] 1'0
         assign $0\main_libresocsim_scratch_storage[31:0] 305419896
         assign $0\main_libresocsim_scratch_re[0:0] 1'0
         assign $0\main_libresocsim_bus_errors[31:0] 0
+        assign $0\spisdcard_clk[0:0] 1'0
+        assign $0\spisdcard_mosi[0:0] 1'0
+        assign $0\spisdcard_cs_n[0:0] 1'0
         assign $0\uart_tx[0:0] 1'1
         assign $0\pwm[1:0] 2'00
         assign $0\spimaster_clk[0:0] 1'0
         assign $0\spimaster_mosi[0:0] 1'0
         assign $0\spimaster_cs_n[0:0] 1'0
-        assign $0\spisdcard_clk[0:0] 1'0
-        assign $0\spisdcard_mosi[0:0] 1'0
-        assign $0\spisdcard_cs_n[0:0] 1'0
         assign $0\main_libresocsim_converter0_counter[0:0] 1'0
         assign $0\main_libresocsim_converter1_counter[0:0] 1'0
         assign $0\main_libresocsim_converter2_counter[0:0] 1'0
@@ -131159,7 +130991,7 @@ module \ls180
         assign $0\main_spisdcard_miso_data[7:0] 8'00000000
         assign $0\main_spimaster1_storage[15:0] 16'0000000001111101
         assign $0\main_spimaster1_re[0:0] 1'0
-        assign $0\main_dummy[35:0] 36'000000000000000000000000000000000000
+        assign $0\main_dummy[23:0] 24'000000000000000000000000
         assign $0\main_pwm0_enable_storage[0:0] 1'0
         assign $0\main_pwm0_enable_re[0:0] 1'0
         assign $0\main_pwm0_width_re[0:0] 1'0
@@ -131302,14 +131134,14 @@ module \ls180
       case 
     end
     sync posedge \sys_clk_1
+      update \spisdcard_clk $0\spisdcard_clk[0:0]
+      update \spisdcard_mosi $0\spisdcard_mosi[0:0]
+      update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
       update \uart_tx $0\uart_tx[0:0]
       update \pwm $0\pwm[1:0]
       update \spimaster_clk $0\spimaster_clk[0:0]
       update \spimaster_mosi $0\spimaster_mosi[0:0]
       update \spimaster_cs_n $0\spimaster_cs_n[0:0]
-      update \spisdcard_clk $0\spisdcard_clk[0:0]
-      update \spisdcard_mosi $0\spisdcard_mosi[0:0]
-      update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
       update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0]
       update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0]
       update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0]
@@ -131492,7 +131324,7 @@ module \ls180
       update \main_spisdcard_miso_data $0\main_spisdcard_miso_data[7:0]
       update \main_spimaster1_storage $0\main_spimaster1_storage[15:0]
       update \main_spimaster1_re $0\main_spimaster1_re[0:0]
-      update \main_dummy $0\main_dummy[35:0]
+      update \main_dummy $0\main_dummy[23:0]
       update \main_pwm0_counter $0\main_pwm0_counter[31:0]
       update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0]
       update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0]
@@ -131716,7 +131548,7 @@ module \ls180
       update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0]
   end
   attribute \src "ls180.v:745.5-745.43"
-  process $proc$ls180.v:745$3052
+  process $proc$ls180.v:745$3040
     assign { } { }
     assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0
     sync always
@@ -131724,7 +131556,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:748.5-748.49"
-  process $proc$ls180.v:748$3053
+  process $proc$ls180.v:748$3041
     assign { } { }
     assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
     sync always
@@ -131732,7 +131564,7 @@ module \ls180
       update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0]
   end
   attribute \src "ls180.v:749.5-749.49"
-  process $proc$ls180.v:749$3054
+  process $proc$ls180.v:749$3042
     assign { } { }
     assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
     sync always
@@ -131740,7 +131572,7 @@ module \ls180
       update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0]
   end
   attribute \src "ls180.v:750.5-750.48"
-  process $proc$ls180.v:750$3055
+  process $proc$ls180.v:750$3043
     assign { } { }
     assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0
     sync always
@@ -131748,7 +131580,7 @@ module \ls180
       update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0]
   end
   attribute \src "ls180.v:754.11-754.46"
-  process $proc$ls180.v:754$3056
+  process $proc$ls180.v:754$3044
     assign { } { }
     assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000
     sync always
@@ -131756,7 +131588,7 @@ module \ls180
       update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0]
   end
   attribute \src "ls180.v:756.11-756.45"
-  process $proc$ls180.v:756$3057
+  process $proc$ls180.v:756$3045
     assign { } { }
     assign $1\main_sdram_choose_cmd_grant[1:0] 2'00
     sync always
@@ -131764,7 +131596,7 @@ module \ls180
       update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0]
   end
   attribute \src "ls180.v:758.5-758.44"
-  process $proc$ls180.v:758$3058
+  process $proc$ls180.v:758$3046
     assign { } { }
     assign $1\main_sdram_choose_req_want_reads[0:0] 1'0
     sync always
@@ -131772,7 +131604,7 @@ module \ls180
       update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0]
   end
   attribute \src "ls180.v:759.5-759.45"
-  process $proc$ls180.v:759$3059
+  process $proc$ls180.v:759$3047
     assign { } { }
     assign $1\main_sdram_choose_req_want_writes[0:0] 1'0
     sync always
@@ -131780,7 +131612,7 @@ module \ls180
       update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0]
   end
   attribute \src "ls180.v:76.5-76.46"
-  process $proc$ls180.v:76$2782
+  process $proc$ls180.v:76$2770
     assign { } { }
     assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0
     sync always
@@ -131788,7 +131620,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:761.5-761.48"
-  process $proc$ls180.v:761$3060
+  process $proc$ls180.v:761$3048
     assign { } { }
     assign $1\main_sdram_choose_req_want_activates[0:0] 1'0
     sync always
@@ -131796,7 +131628,7 @@ module \ls180
       update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0]
   end
   attribute \src "ls180.v:763.5-763.43"
-  process $proc$ls180.v:763$3061
+  process $proc$ls180.v:763$3049
     assign { } { }
     assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0
     sync always
@@ -131804,7 +131636,7 @@ module \ls180
       update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0]
   end
   attribute \src "ls180.v:766.5-766.49"
-  process $proc$ls180.v:766$3062
+  process $proc$ls180.v:766$3050
     assign { } { }
     assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0
     sync always
@@ -131812,7 +131644,7 @@ module \ls180
       update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0]
   end
   attribute \src "ls180.v:767.5-767.49"
-  process $proc$ls180.v:767$3063
+  process $proc$ls180.v:767$3051
     assign { } { }
     assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0
     sync always
@@ -131820,7 +131652,7 @@ module \ls180
       update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0]
   end
   attribute \src "ls180.v:768.5-768.48"
-  process $proc$ls180.v:768$3064
+  process $proc$ls180.v:768$3052
     assign { } { }
     assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0
     sync always
@@ -131828,7 +131660,7 @@ module \ls180
       update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0]
   end
   attribute \src "ls180.v:772.11-772.46"
-  process $proc$ls180.v:772$3065
+  process $proc$ls180.v:772$3053
     assign { } { }
     assign $1\main_sdram_choose_req_valids[3:0] 4'0000
     sync always
@@ -131836,7 +131668,7 @@ module \ls180
       update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0]
   end
   attribute \src "ls180.v:774.11-774.45"
-  process $proc$ls180.v:774$3066
+  process $proc$ls180.v:774$3054
     assign { } { }
     assign $1\main_sdram_choose_req_grant[1:0] 2'00
     sync always
@@ -131844,7 +131676,7 @@ module \ls180
       update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0]
   end
   attribute \src "ls180.v:776.12-776.36"
-  process $proc$ls180.v:776$3067
+  process $proc$ls180.v:776$3055
     assign { } { }
     assign $0\main_sdram_nop_a[12:0] 13'0000000000000
     sync always
@@ -131852,7 +131684,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:777.11-777.35"
-  process $proc$ls180.v:777$3068
+  process $proc$ls180.v:777$3056
     assign { } { }
     assign $0\main_sdram_nop_ba[1:0] 2'00
     sync always
@@ -131860,7 +131692,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:778.11-778.40"
-  process $proc$ls180.v:778$3069
+  process $proc$ls180.v:778$3057
     assign { } { }
     assign $1\main_sdram_steerer_sel[1:0] 2'00
     sync always
@@ -131868,7 +131700,7 @@ module \ls180
       update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0]
   end
   attribute \src "ls180.v:779.5-779.31"
-  process $proc$ls180.v:779$3070
+  process $proc$ls180.v:779$3058
     assign { } { }
     assign $0\main_sdram_steerer0[0:0] 1'1
     sync always
@@ -131876,7 +131708,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:780.5-780.31"
-  process $proc$ls180.v:780$3071
+  process $proc$ls180.v:780$3059
     assign { } { }
     assign $0\main_sdram_steerer1[0:0] 1'1
     sync always
@@ -131884,7 +131716,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:782.32-782.63"
-  process $proc$ls180.v:782$3072
+  process $proc$ls180.v:782$3060
     assign { } { }
     assign $0\main_sdram_trrdcon_ready[0:0] 1'1
     sync always
@@ -131892,7 +131724,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:784.32-784.63"
-  process $proc$ls180.v:784$3073
+  process $proc$ls180.v:784$3061
     assign { } { }
     assign $0\main_sdram_tfawcon_ready[0:0] 1'1
     sync always
@@ -131900,7 +131732,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:786.32-786.63"
-  process $proc$ls180.v:786$3074
+  process $proc$ls180.v:786$3062
     assign { } { }
     assign $1\main_sdram_tccdcon_ready[0:0] 1'0
     sync always
@@ -131908,7 +131740,7 @@ module \ls180
       update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0]
   end
   attribute \src "ls180.v:787.5-787.36"
-  process $proc$ls180.v:787$3075
+  process $proc$ls180.v:787$3063
     assign { } { }
     assign $1\main_sdram_tccdcon_count[0:0] 1'0
     sync always
@@ -131916,7 +131748,7 @@ module \ls180
       update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0]
   end
   attribute \src "ls180.v:789.32-789.63"
-  process $proc$ls180.v:789$3076
+  process $proc$ls180.v:789$3064
     assign { } { }
     assign $1\main_sdram_twtrcon_ready[0:0] 1'0
     sync always
@@ -131924,7 +131756,7 @@ module \ls180
       update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0]
   end
   attribute \src "ls180.v:790.11-790.42"
-  process $proc$ls180.v:790$3077
+  process $proc$ls180.v:790$3065
     assign { } { }
     assign $1\main_sdram_twtrcon_count[2:0] 3'000
     sync always
@@ -131932,7 +131764,7 @@ module \ls180
       update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0]
   end
   attribute \src "ls180.v:793.5-793.26"
-  process $proc$ls180.v:793$3078
+  process $proc$ls180.v:793$3066
     assign { } { }
     assign $1\main_sdram_en0[0:0] 1'0
     sync always
@@ -131940,7 +131772,7 @@ module \ls180
       update \main_sdram_en0 $1\main_sdram_en0[0:0]
   end
   attribute \src "ls180.v:795.11-795.34"
-  process $proc$ls180.v:795$3079
+  process $proc$ls180.v:795$3067
     assign { } { }
     assign $1\main_sdram_time0[4:0] 5'00000
     sync always
@@ -131948,7 +131780,7 @@ module \ls180
       update \main_sdram_time0 $1\main_sdram_time0[4:0]
   end
   attribute \src "ls180.v:796.5-796.26"
-  process $proc$ls180.v:796$3080
+  process $proc$ls180.v:796$3068
     assign { } { }
     assign $1\main_sdram_en1[0:0] 1'0
     sync always
@@ -131956,7 +131788,7 @@ module \ls180
       update \main_sdram_en1 $1\main_sdram_en1[0:0]
   end
   attribute \src "ls180.v:798.11-798.34"
-  process $proc$ls180.v:798$3081
+  process $proc$ls180.v:798$3069
     assign { } { }
     assign $1\main_sdram_time1[3:0] 4'0000
     sync always
@@ -131964,7 +131796,7 @@ module \ls180
       update \main_sdram_time1 $1\main_sdram_time1[3:0]
   end
   attribute \src "ls180.v:819.5-819.29"
-  process $proc$ls180.v:819$3082
+  process $proc$ls180.v:819$3070
     assign { } { }
     assign $1\main_wb_sdram_ack[0:0] 1'0
     sync always
@@ -131972,7 +131804,7 @@ module \ls180
       update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0]
   end
   attribute \src "ls180.v:823.5-823.29"
-  process $proc$ls180.v:823$3083
+  process $proc$ls180.v:823$3071
     assign { } { }
     assign $0\main_wb_sdram_err[0:0] 1'0
     sync always
@@ -131980,7 +131812,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:824.12-824.40"
-  process $proc$ls180.v:824$3084
+  process $proc$ls180.v:824$3072
     assign { } { }
     assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000
     sync always
@@ -131988,7 +131820,7 @@ module \ls180
       update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0]
   end
   attribute \src "ls180.v:825.12-825.42"
-  process $proc$ls180.v:825$3085
+  process $proc$ls180.v:825$3073
     assign { } { }
     assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000
     sync always
@@ -131996,7 +131828,7 @@ module \ls180
       update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0]
   end
   attribute \src "ls180.v:827.11-827.38"
-  process $proc$ls180.v:827$3086
+  process $proc$ls180.v:827$3074
     assign { } { }
     assign $1\main_litedram_wb_sel[1:0] 2'00
     sync always
@@ -132004,7 +131836,7 @@ module \ls180
       update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0]
   end
   attribute \src "ls180.v:828.5-828.32"
-  process $proc$ls180.v:828$3087
+  process $proc$ls180.v:828$3075
     assign { } { }
     assign $1\main_litedram_wb_cyc[0:0] 1'0
     sync always
@@ -132012,7 +131844,7 @@ module \ls180
       update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0]
   end
   attribute \src "ls180.v:829.5-829.32"
-  process $proc$ls180.v:829$3088
+  process $proc$ls180.v:829$3076
     assign { } { }
     assign $1\main_litedram_wb_stb[0:0] 1'0
     sync always
@@ -132020,7 +131852,7 @@ module \ls180
       update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0]
   end
   attribute \src "ls180.v:83.5-83.46"
-  process $proc$ls180.v:83$2783
+  process $proc$ls180.v:83$2771
     assign { } { }
     assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0
     sync always
@@ -132028,7 +131860,7 @@ module \ls180
       update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0]
   end
   attribute \src "ls180.v:831.5-831.31"
-  process $proc$ls180.v:831$3089
+  process $proc$ls180.v:831$3077
     assign { } { }
     assign $1\main_litedram_wb_we[0:0] 1'0
     sync always
@@ -132036,7 +131868,7 @@ module \ls180
       update \main_litedram_wb_we $1\main_litedram_wb_we[0:0]
   end
   attribute \src "ls180.v:832.5-832.31"
-  process $proc$ls180.v:832$3090
+  process $proc$ls180.v:832$3078
     assign { } { }
     assign $1\main_converter_skip[0:0] 1'0
     sync always
@@ -132044,7 +131876,7 @@ module \ls180
       update \main_converter_skip $1\main_converter_skip[0:0]
   end
   attribute \src "ls180.v:833.5-833.34"
-  process $proc$ls180.v:833$3091
+  process $proc$ls180.v:833$3079
     assign { } { }
     assign $1\main_converter_counter[0:0] 1'0
     sync always
@@ -132052,7 +131884,7 @@ module \ls180
       update \main_converter_counter $1\main_converter_counter[0:0]
   end
   attribute \src "ls180.v:835.12-835.40"
-  process $proc$ls180.v:835$3092
+  process $proc$ls180.v:835$3080
     assign { } { }
     assign $1\main_converter_dat_r[31:0] 0
     sync always
@@ -132060,7 +131892,7 @@ module \ls180
       update \main_converter_dat_r $1\main_converter_dat_r[31:0]
   end
   attribute \src "ls180.v:836.5-836.29"
-  process $proc$ls180.v:836$3093
+  process $proc$ls180.v:836$3081
     assign { } { }
     assign $1\main_cmd_consumed[0:0] 1'0
     sync always
@@ -132068,7 +131900,7 @@ module \ls180
       update \main_cmd_consumed $1\main_cmd_consumed[0:0]
   end
   attribute \src "ls180.v:837.5-837.31"
-  process $proc$ls180.v:837$3094
+  process $proc$ls180.v:837$3082
     assign { } { }
     assign $1\main_wdata_consumed[0:0] 1'0
     sync always
@@ -132076,7 +131908,7 @@ module \ls180
       update \main_wdata_consumed $1\main_wdata_consumed[0:0]
   end
   attribute \src "ls180.v:841.12-841.47"
-  process $proc$ls180.v:841$3095
+  process $proc$ls180.v:841$3083
     assign { } { }
     assign $1\main_uart_phy_storage[31:0] 9895604
     sync always
@@ -132084,7 +131916,7 @@ module \ls180
       update \main_uart_phy_storage $1\main_uart_phy_storage[31:0]
   end
   attribute \src "ls180.v:842.5-842.28"
-  process $proc$ls180.v:842$3096
+  process $proc$ls180.v:842$3084
     assign { } { }
     assign $1\main_uart_phy_re[0:0] 1'0
     sync always
@@ -132092,7 +131924,7 @@ module \ls180
       update \main_uart_phy_re $1\main_uart_phy_re[0:0]
   end
   attribute \src "ls180.v:844.5-844.36"
-  process $proc$ls180.v:844$3097
+  process $proc$ls180.v:844$3085
     assign { } { }
     assign $1\main_uart_phy_sink_ready[0:0] 1'0
     sync always
@@ -132100,7 +131932,7 @@ module \ls180
       update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0]
   end
   attribute \src "ls180.v:848.5-848.39"
-  process $proc$ls180.v:848$3098
+  process $proc$ls180.v:848$3086
     assign { } { }
     assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0
     sync always
@@ -132108,7 +131940,7 @@ module \ls180
       update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0]
   end
   attribute \src "ls180.v:849.12-849.54"
-  process $proc$ls180.v:849$3099
+  process $proc$ls180.v:849$3087
     assign { } { }
     assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0
     sync always
@@ -132116,7 +131948,7 @@ module \ls180
       update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0]
   end
   attribute \src "ls180.v:850.11-850.38"
-  process $proc$ls180.v:850$3100
+  process $proc$ls180.v:850$3088
     assign { } { }
     assign $1\main_uart_phy_tx_reg[7:0] 8'00000000
     sync always
@@ -132124,7 +131956,7 @@ module \ls180
       update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0]
   end
   attribute \src "ls180.v:851.11-851.43"
-  process $proc$ls180.v:851$3101
+  process $proc$ls180.v:851$3089
     assign { } { }
     assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000
     sync always
@@ -132132,7 +131964,7 @@ module \ls180
       update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0]
   end
   attribute \src "ls180.v:852.5-852.33"
-  process $proc$ls180.v:852$3102
+  process $proc$ls180.v:852$3090
     assign { } { }
     assign $1\main_uart_phy_tx_busy[0:0] 1'0
     sync always
@@ -132140,7 +131972,7 @@ module \ls180
       update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0]
   end
   attribute \src "ls180.v:853.5-853.38"
-  process $proc$ls180.v:853$3103
+  process $proc$ls180.v:853$3091
     assign { } { }
     assign $1\main_uart_phy_source_valid[0:0] 1'0
     sync always
@@ -132148,7 +131980,7 @@ module \ls180
       update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0]
   end
   attribute \src "ls180.v:855.5-855.38"
-  process $proc$ls180.v:855$3104
+  process $proc$ls180.v:855$3092
     assign { } { }
     assign $0\main_uart_phy_source_first[0:0] 1'0
     sync always
@@ -132156,7 +131988,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:856.5-856.37"
-  process $proc$ls180.v:856$3105
+  process $proc$ls180.v:856$3093
     assign { } { }
     assign $0\main_uart_phy_source_last[0:0] 1'0
     sync always
@@ -132164,7 +131996,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:857.11-857.51"
-  process $proc$ls180.v:857$3106
+  process $proc$ls180.v:857$3094
     assign { } { }
     assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000
     sync always
@@ -132172,7 +132004,7 @@ module \ls180
       update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0]
   end
   attribute \src "ls180.v:858.5-858.39"
-  process $proc$ls180.v:858$3107
+  process $proc$ls180.v:858$3095
     assign { } { }
     assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0
     sync always
@@ -132180,7 +132012,7 @@ module \ls180
       update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0]
   end
   attribute \src "ls180.v:859.12-859.54"
-  process $proc$ls180.v:859$3108
+  process $proc$ls180.v:859$3096
     assign { } { }
     assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0
     sync always
@@ -132188,7 +132020,7 @@ module \ls180
       update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0]
   end
   attribute \src "ls180.v:861.5-861.30"
-  process $proc$ls180.v:861$3109
+  process $proc$ls180.v:861$3097
     assign { } { }
     assign $1\main_uart_phy_rx_r[0:0] 1'0
     sync always
@@ -132196,7 +132028,7 @@ module \ls180
       update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0]
   end
   attribute \src "ls180.v:862.11-862.38"
-  process $proc$ls180.v:862$3110
+  process $proc$ls180.v:862$3098
     assign { } { }
     assign $1\main_uart_phy_rx_reg[7:0] 8'00000000
     sync always
@@ -132204,7 +132036,7 @@ module \ls180
       update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0]
   end
   attribute \src "ls180.v:863.11-863.43"
-  process $proc$ls180.v:863$3111
+  process $proc$ls180.v:863$3099
     assign { } { }
     assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000
     sync always
@@ -132212,7 +132044,7 @@ module \ls180
       update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0]
   end
   attribute \src "ls180.v:864.5-864.33"
-  process $proc$ls180.v:864$3112
+  process $proc$ls180.v:864$3100
     assign { } { }
     assign $1\main_uart_phy_rx_busy[0:0] 1'0
     sync always
@@ -132220,7 +132052,7 @@ module \ls180
       update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0]
   end
   attribute \src "ls180.v:87.5-87.46"
-  process $proc$ls180.v:87$2784
+  process $proc$ls180.v:87$2772
     assign { } { }
     assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0
     sync always
@@ -132228,7 +132060,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:875.5-875.32"
-  process $proc$ls180.v:875$3113
+  process $proc$ls180.v:875$3101
     assign { } { }
     assign $1\main_uart_tx_pending[0:0] 1'0
     sync always
@@ -132236,7 +132068,7 @@ module \ls180
       update \main_uart_tx_pending $1\main_uart_tx_pending[0:0]
   end
   attribute \src "ls180.v:877.5-877.30"
-  process $proc$ls180.v:877$3114
+  process $proc$ls180.v:877$3102
     assign { } { }
     assign $1\main_uart_tx_clear[0:0] 1'0
     sync always
@@ -132244,7 +132076,7 @@ module \ls180
       update \main_uart_tx_clear $1\main_uart_tx_clear[0:0]
   end
   attribute \src "ls180.v:878.5-878.36"
-  process $proc$ls180.v:878$3115
+  process $proc$ls180.v:878$3103
     assign { } { }
     assign $1\main_uart_tx_old_trigger[0:0] 1'0
     sync always
@@ -132252,7 +132084,7 @@ module \ls180
       update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0]
   end
   attribute \src "ls180.v:880.5-880.32"
-  process $proc$ls180.v:880$3116
+  process $proc$ls180.v:880$3104
     assign { } { }
     assign $1\main_uart_rx_pending[0:0] 1'0
     sync always
@@ -132260,7 +132092,7 @@ module \ls180
       update \main_uart_rx_pending $1\main_uart_rx_pending[0:0]
   end
   attribute \src "ls180.v:882.5-882.30"
-  process $proc$ls180.v:882$3117
+  process $proc$ls180.v:882$3105
     assign { } { }
     assign $1\main_uart_rx_clear[0:0] 1'0
     sync always
@@ -132268,7 +132100,7 @@ module \ls180
       update \main_uart_rx_clear $1\main_uart_rx_clear[0:0]
   end
   attribute \src "ls180.v:883.5-883.36"
-  process $proc$ls180.v:883$3118
+  process $proc$ls180.v:883$3106
     assign { } { }
     assign $1\main_uart_rx_old_trigger[0:0] 1'0
     sync always
@@ -132276,7 +132108,7 @@ module \ls180
       update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0]
   end
   attribute \src "ls180.v:887.11-887.49"
-  process $proc$ls180.v:887$3119
+  process $proc$ls180.v:887$3107
     assign { } { }
     assign $1\main_uart_eventmanager_status_w[1:0] 2'00
     sync always
@@ -132284,7 +132116,7 @@ module \ls180
       update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0]
   end
   attribute \src "ls180.v:891.11-891.50"
-  process $proc$ls180.v:891$3120
+  process $proc$ls180.v:891$3108
     assign { } { }
     assign $1\main_uart_eventmanager_pending_w[1:0] 2'00
     sync always
@@ -132292,7 +132124,7 @@ module \ls180
       update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0]
   end
   attribute \src "ls180.v:892.11-892.48"
-  process $proc$ls180.v:892$3121
+  process $proc$ls180.v:892$3109
     assign { } { }
     assign $1\main_uart_eventmanager_storage[1:0] 2'00
     sync always
@@ -132300,7 +132132,7 @@ module \ls180
       update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0]
   end
   attribute \src "ls180.v:893.5-893.37"
-  process $proc$ls180.v:893$3122
+  process $proc$ls180.v:893$3110
     assign { } { }
     assign $1\main_uart_eventmanager_re[0:0] 1'0
     sync always
@@ -132308,7 +132140,7 @@ module \ls180
       update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0]
   end
   attribute \src "ls180.v:910.5-910.40"
-  process $proc$ls180.v:910$3123
+  process $proc$ls180.v:910$3111
     assign { } { }
     assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0
     sync always
@@ -132316,7 +132148,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:911.5-911.39"
-  process $proc$ls180.v:911$3124
+  process $proc$ls180.v:911$3112
     assign { } { }
     assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0
     sync always
@@ -132324,7 +132156,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:919.5-919.38"
-  process $proc$ls180.v:919$3125
+  process $proc$ls180.v:919$3113
     assign { } { }
     assign $1\main_uart_tx_fifo_readable[0:0] 1'0
     sync always
@@ -132332,7 +132164,7 @@ module \ls180
       update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0]
   end
   attribute \src "ls180.v:926.11-926.42"
-  process $proc$ls180.v:926$3126
+  process $proc$ls180.v:926$3114
     assign { } { }
     assign $1\main_uart_tx_fifo_level0[4:0] 5'00000
     sync always
@@ -132340,7 +132172,7 @@ module \ls180
       update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0]
   end
   attribute \src "ls180.v:927.5-927.37"
-  process $proc$ls180.v:927$3127
+  process $proc$ls180.v:927$3115
     assign { } { }
     assign $0\main_uart_tx_fifo_replace[0:0] 1'0
     sync always
@@ -132348,7 +132180,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:928.11-928.43"
-  process $proc$ls180.v:928$3128
+  process $proc$ls180.v:928$3116
     assign { } { }
     assign $1\main_uart_tx_fifo_produce[3:0] 4'0000
     sync always
@@ -132356,7 +132188,7 @@ module \ls180
       update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0]
   end
   attribute \src "ls180.v:929.11-929.43"
-  process $proc$ls180.v:929$3129
+  process $proc$ls180.v:929$3117
     assign { } { }
     assign $1\main_uart_tx_fifo_consume[3:0] 4'0000
     sync always
@@ -132364,7 +132196,7 @@ module \ls180
       update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0]
   end
   attribute \src "ls180.v:930.11-930.46"
-  process $proc$ls180.v:930$3130
+  process $proc$ls180.v:930$3118
     assign { } { }
     assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000
     sync always
@@ -132372,7 +132204,7 @@ module \ls180
       update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0]
   end
   attribute \src "ls180.v:956.5-956.38"
-  process $proc$ls180.v:956$3131
+  process $proc$ls180.v:956$3119
     assign { } { }
     assign $1\main_uart_rx_fifo_readable[0:0] 1'0
     sync always
@@ -132380,7 +132212,7 @@ module \ls180
       update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0]
   end
   attribute \src "ls180.v:963.11-963.42"
-  process $proc$ls180.v:963$3132
+  process $proc$ls180.v:963$3120
     assign { } { }
     assign $1\main_uart_rx_fifo_level0[4:0] 5'00000
     sync always
@@ -132388,7 +132220,7 @@ module \ls180
       update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0]
   end
   attribute \src "ls180.v:964.5-964.37"
-  process $proc$ls180.v:964$3133
+  process $proc$ls180.v:964$3121
     assign { } { }
     assign $0\main_uart_rx_fifo_replace[0:0] 1'0
     sync always
@@ -132396,7 +132228,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:965.11-965.43"
-  process $proc$ls180.v:965$3134
+  process $proc$ls180.v:965$3122
     assign { } { }
     assign $1\main_uart_rx_fifo_produce[3:0] 4'0000
     sync always
@@ -132404,7 +132236,7 @@ module \ls180
       update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0]
   end
   attribute \src "ls180.v:966.11-966.43"
-  process $proc$ls180.v:966$3135
+  process $proc$ls180.v:966$3123
     assign { } { }
     assign $1\main_uart_rx_fifo_consume[3:0] 4'0000
     sync always
@@ -132412,7 +132244,7 @@ module \ls180
       update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0]
   end
   attribute \src "ls180.v:967.11-967.46"
-  process $proc$ls180.v:967$3136
+  process $proc$ls180.v:967$3124
     assign { } { }
     assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000
     sync always
@@ -132420,7 +132252,7 @@ module \ls180
       update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0]
   end
   attribute \src "ls180.v:982.5-982.27"
-  process $proc$ls180.v:982$3137
+  process $proc$ls180.v:982$3125
     assign { } { }
     assign $0\main_uart_reset[0:0] 1'0
     sync always
@@ -132428,7 +132260,7 @@ module \ls180
     sync init
   end
   attribute \src "ls180.v:983.12-983.40"
-  process $proc$ls180.v:983$3138
+  process $proc$ls180.v:983$3126
     assign { } { }
     assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000
     sync always
@@ -132436,7 +132268,7 @@ module \ls180
       update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0]
   end
   attribute \src "ls180.v:984.5-984.27"
-  process $proc$ls180.v:984$3139
+  process $proc$ls180.v:984$3127
     assign { } { }
     assign $1\main_gpio_oe_re[0:0] 1'0
     sync always
@@ -132444,7 +132276,7 @@ module \ls180
       update \main_gpio_oe_re $1\main_gpio_oe_re[0:0]
   end
   attribute \src "ls180.v:985.12-985.36"
-  process $proc$ls180.v:985$3140
+  process $proc$ls180.v:985$3128
     assign { } { }
     assign $1\main_gpio_status[15:0] 16'0000000000000000
     sync always
@@ -132452,7 +132284,7 @@ module \ls180
       update \main_gpio_status $1\main_gpio_status[15:0]
   end
   attribute \src "ls180.v:987.12-987.41"
-  process $proc$ls180.v:987$3141
+  process $proc$ls180.v:987$3129
     assign { } { }
     assign $1\main_gpio_out_storage[15:0] 16'0000000000000000
     sync always
@@ -132460,7 +132292,7 @@ module \ls180
       update \main_gpio_out_storage $1\main_gpio_out_storage[15:0]
   end
   attribute \src "ls180.v:988.5-988.28"
-  process $proc$ls180.v:988$3142
+  process $proc$ls180.v:988$3130
     assign { } { }
     assign $1\main_gpio_out_re[0:0] 1'0
     sync always
@@ -132468,7 +132300,7 @@ module \ls180
       update \main_gpio_out_re $1\main_gpio_out_re[0:0]
   end
   attribute \src "ls180.v:994.5-994.32"
-  process $proc$ls180.v:994$3143
+  process $proc$ls180.v:994$3131
     assign { } { }
     assign $1\main_spimaster2_done[0:0] 1'0
     sync always
@@ -132476,7 +132308,7 @@ module \ls180
       update \main_spimaster2_done $1\main_spimaster2_done[0:0]
   end
   attribute \src "ls180.v:995.5-995.31"
-  process $proc$ls180.v:995$3144
+  process $proc$ls180.v:995$3132
     assign { } { }
     assign $1\main_spimaster3_irq[0:0] 1'0
     sync always
@@ -132484,7 +132316,7 @@ module \ls180
       update \main_spimaster3_irq $1\main_spimaster3_irq[0:0]
   end
   attribute \src "ls180.v:997.11-997.38"
-  process $proc$ls180.v:997$3145
+  process $proc$ls180.v:997$3133
     assign { } { }
     assign $1\main_spimaster5_miso[7:0] 8'00000000
     sync always
@@ -134152,23 +133984,23 @@ module \ls180
   connect \sdrio_clk_66 \sys_clk_1
   connect \sdrio_clk_67 \sys_clk_1
   connect \sdrio_clk_68 \sys_clk_1
-  connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10071$2705_DATA
+  connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10059$2693_DATA
   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat
-  connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10089$2712_DATA
+  connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10077$2700_DATA
   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1
-  connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10103$2719_DATA
+  connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10091$2707_DATA
   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2
-  connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10117$2726_DATA
+  connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10105$2714_DATA
   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3
-  connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10131$2733_DATA
+  connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10119$2721_DATA
   connect \main_uart_tx_fifo_wrport_dat_r \memdat_4
   connect \main_uart_tx_fifo_rdport_dat_r \memdat_5
   connect \main_uart_rx_fifo_wrport_dat_r \memdat_6
   connect \main_uart_rx_fifo_rdport_dat_r \memdat_7
   connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8
-  connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10179$2754_DATA
+  connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10167$2742_DATA
   connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9
-  connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10193$2761_DATA
+  connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10181$2749_DATA
 end
 attribute \src "libresoc.v:45741.1-45785.10"
 attribute \cells_not_processed 1