From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 5 Aug 2020 09:29:44 +0000 (+0100)
Subject: add div FSM as default for test_issuer in verilog and ilang gen
X-Git-Tag: semi_working_ecp5~441^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4cb01cbff73a8e5cf74282f260be6a9a1f666b00;p=soc.git

add div FSM as default for test_issuer in verilog and ilang gen
---

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index de70df7e..9cf44a99 100644
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -72,7 +72,7 @@ from soc.fu.trap.pipeline import TrapBasePipe
 from soc.fu.trap.pipe_data import TrapPipeSpec
 
 from soc.fu.div.pipeline import DivBasePipe
-from soc.fu.div.pipe_data import DivPipeSpecDivPipeCore
+from soc.fu.div.pipe_data import DivPipeSpecFSMDivCore
 
 from soc.fu.mul.pipeline import MulBasePipe
 from soc.fu.mul.pipe_data import MulPipeSpec
@@ -162,7 +162,7 @@ class DivFunctionUnit(FunctionUnitBaseSingle):
     fnunit = Function.DIV
 
     def __init__(self, idx):
-        super().__init__(DivPipeSpecDivPipeCore, DivBasePipe, idx)
+        super().__init__(DivPipeSpecFSMDivCore, DivBasePipe, idx)
 
 
 class MulFunctionUnit(FunctionUnitBaseSingle):
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 3d168da6..168f389f 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -260,6 +260,7 @@ class TestIssuer(Elaboratable):
 if __name__ == '__main__':
     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
              'spr': 1,
+             'div': 1,
              'mul': 1,
              'shiftrot': 1}
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index d77464b5..90b83081 100644
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -11,6 +11,7 @@ from soc.simple.issuer import TestIssuer
 if __name__ == '__main__':
     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
              'spr': 1,
+             'div': 1,
              'mul': 1,
              'shiftrot': 1}
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',