From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 2 Jul 2020 21:52:52 +0000 (+0100)
Subject: allow ALU names to propagate through from FU to CompUnit ALU
X-Git-Tag: div_pipeline~168
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4cbbf3870ec5869b7ca6c885bdb076a9f73a55e2;p=soc.git

allow ALU names to propagate through from FU to CompUnit ALU
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 2767a9c3..e2f8683a 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -101,7 +101,7 @@ class CompUnitRecord(RegSpec, RecordObject):
 
 
 class MultiCompUnit(RegSpecALUAPI, Elaboratable):
-    def __init__(self, rwid, alu, opsubsetkls, n_src=2, n_dst=1):
+    def __init__(self, rwid, alu, opsubsetkls, n_src=2, n_dst=1, name=None):
         """MultiCompUnit
 
         * :rwid:        width of register latches (TODO: allocate per regspec)
@@ -111,6 +111,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         * :n_dst:       number of destination operands
         """
         RegSpecALUAPI.__init__(self, rwid, alu)
+        self.alu_name = name or "alu"
         self.opsubsetkls = opsubsetkls
         self.cu = cu = CompUnitRecord(opsubsetkls, rwid, n_src, n_dst)
         n_src, n_dst = self.n_src, self.n_dst = cu._n_src, cu._n_dst
@@ -164,7 +165,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.alu = self.alu
+        setattr(m.submodules, self.alu_name, self.alu)
         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
         m.submodules.req_l = req_l = SRLatch(False, self.n_dst, name="req")
diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index 387491b1..6a65c6af 100644
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -97,12 +97,12 @@ class FunctionUnitBaseSingle(MultiCompUnit):
     ideal (it could be a lot neater) but works for now.
     """
     def __init__(self, speckls, pipekls, idx):
+        alu_name = "alu_%s%d" % (self.fnunit.name.lower(), idx)
         pspec = speckls(id_wid=2)                # spec (NNNPipeSpec instance)
         opsubset = pspec.opsubsetkls             # get the operand subset class
         regspec = pspec.regspec                  # get the regspec
         alu = pipekls(pspec)                     # create actual NNNBasePipe
-        alu.name = "alu_%s%d" % (self.fnunit.name.lower(), idx)
-        super().__init__(regspec, alu, opsubset) # pass to MultiCompUnit
+        super().__init__(regspec, alu, opsubset, name=alu_name) # MultiCompUnit
 
 
 ##############################################################
@@ -217,7 +217,7 @@ def tst_single_fus_il():
                         ('trap', TrapFunctionUnit),
                         ('logical', LogicalFunctionUnit),
                         ('shiftrot', ShiftRotFunctionUnit)):
-        fu = kls()
+        fu = kls(0)
         vl = rtlil.convert(fu, ports=fu.ports())
         with open("fu_%s.il" % name, "w") as f:
             f.write(vl)