From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 Feb 2019 04:32:09 +0000 (+0000)
Subject: invert Cat order, use 3 zeros (3 bits)
X-Git-Tag: ls180-24jan2020~2033
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ccb4d59bd50c5d5bff9008dac0ca034fc2d8e9a;p=ieee754fpu.git

invert Cat order, use 3 zeros (3 bits)
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 1c163bf0..2d4c175d 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -80,8 +80,8 @@ class FPADD:
             with m.State("unpack"):
                     m.next = "special_cases"
                     m.d.sync += [
-                        a_m.eq(Cat(a[0:23], 0)),
-                        b_m.eq(Cat(b[0:23], 0)),
+                        a_m.eq(Cat(0, 0, 0, a[0:23])),
+                        b_m.eq(Cat(0, 0, 0, b[0:23])),
                         a_e.eq(Cat(a[23:31]) - 127),
                         b_e.eq(Cat(b[23:31]) - 127),
                         a_s.eq(Cat(a[31])),